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* [DAG] FoldSetCC - reuse valuetype + ensure its simple.Simon Pilgrim2019-03-111-4/+3
| | | | llvm-svn: 355847
* [Utils] Extract EliminateUnreachableBlocks (NFC)Brian Gesiak2019-03-112-23/+24
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Extract the functionality of eliminating unreachable basic blocks within a function, previously encapsulated within the -unreachableblockelim pass, and make it available as a function within BlockUtils.h. No functional change intended other than making the logic reusable. Exposing this logic makes it easier to implement https://reviews.llvm.org/D59068, which fixes coroutines bug https://bugs.llvm.org/show_bug.cgi?id=40979. Reviewers: mkazantsev, wmi, davidxl, silvas, davide Reviewed By: davide Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59069 llvm-svn: 355846
* [DAG] Move SetCC NaN handling into FoldSetCCSimon Pilgrim2019-03-112-79/+78
| | | | llvm-svn: 355845
* Use bitset for assembler predicatesStanislav Mekhanoshin2019-03-1117-137/+161
| | | | | | | | | | | | | | AMDGPU target run out of Subtarget feature flags hitting the limit of 64. AssemblerPredicates uses at most uint64_t for their representation. At the same time CodeGen has exhausted this a long time ago and switched to a FeatureBitset with the current limit of 192 bits. This patch completes transition to the bitset for feature bits extending it to asm matcher and MC code emitter. Differential Revision: https://reviews.llvm.org/D59002 llvm-svn: 355839
* [AMDGPU] Mark enum types in SIDefines.h as unsignedStanislav Mekhanoshin2019-03-114-21/+21
| | | | | | | | MSVC issues some warnings about signed/unsigned comparison. Differential Revision: https://reviews.llvm.org/D59171 llvm-svn: 355836
* [SimplifyCFG] Retain debug info when threading jumps with critical edgesJeremy Morse2019-03-111-1/+2
| | | | | | | | | | | | | | | | | | | | Fixes bug 38023: https://bugs.llvm.org/show_bug.cgi?id=38023 The SimplifyCFG pass will perform jump threading in some cases where doing so is trivial and would simplify the CFG. When folding a series of blocks with redundant conditional branches into an unconditional "critical edge" block, it does not keep the debug location associated with the previous conditional branch. This patch fixes the bug described by copying the debug info from the old conditional branch to the new unconditional branch instruction, and adds a regression test for the SimplifyCFG pass that covers this case. Patch by Stephen Tozer! Differential Revision: https://reviews.llvm.org/D59206 llvm-svn: 355833
* [DAG] TargetLowering::SimplifySetCC - call FoldSetCC early to handle ↵Simon Pilgrim2019-03-111-13/+6
| | | | | | | | constant/commute folds. Noticed while looking at PR40800 (and also D57921) llvm-svn: 355828
* [MIPS][microMIPS] Add a pattern to match TruncIntFPPetar Jovanovic2019-03-112-1/+8
| | | | | | | | | | | A pattern needed to match TruncIntFP was missing. This was causing multiple tests from llvm test suite to fail during compilation for micromips. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D58722 llvm-svn: 355825
* [CGP] Limit distance between overflow math and cmpSam Parker2019-03-111-0/+11
| | | | | | | | | | | | | | | Inserting an overflowing arithmetic intrinsic can increase register pressure by producing two values at a point where only one is needed, while the second use maybe several blocks away. This increase in pressure is likely to be more detrimental on performance than rematerialising one of the original instructions. So, check that the arithmetic and compare instructions are no further apart than their immediate successor/predecessor. Differential Revision: https://reviews.llvm.org/D59024 llvm-svn: 355823
* [JumpThreading] Retain debug info when replacing branch instructionsJeremy Morse2019-03-111-2/+5
| | | | | | | | | | | | | | | | | | | | Fixes bug 37966: https://bugs.llvm.org/show_bug.cgi?id=37966 The Jump Threading pass will replace certain conditional branch instructions with unconditional branches when it can prove that only one branch can occur. Prior to this patch, it would not carry the debug info from the old instruction to the new one. This patch fixes the bug described by copying the debug info from the conditional branch instruction to the new unconditional branch instruction, and adds a regression test for the Jump Threading pass that covers this case. Patch by Stephen Tozer! Differential Revision: https://reviews.llvm.org/D58963 llvm-svn: 355822
* [MIPS GlobalISel] Silence uninitialized variable warningBenjamin Kramer2019-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | The control flow here cannot ever use the uninitialized value, but it's too hard for the compiler to figure that out. Clang warns: llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:2600:28: error: variable 'CarrySum' is used uninitialized whenever 'for' loop exits because its condition is false [-Werror,-Wsometimes-uninitialized] for (unsigned i = 2; i < Factors.size(); ++i) ^~~~~~~~~~~~~~~~~~ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:2604:26: note: uninitialized use occurs here CarrySumPrevDstIdx = CarrySum; ^~~~~~~~ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:2600:28: note: remove the condition if it is always true for (unsigned i = 2; i < Factors.size(); ++i) ^~~~~~~~~~~~~~~~~~ llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp:2583:22: note: initialize the variable 'CarrySum' to silence this warning unsigned CarrySum; ^ = 0 llvm-svn: 355818
* [MIPS GlobalISel] NarrowScalar G_UMULHPetar Avramovic2019-03-112-4/+11
| | | | | | | | | | NarrowScalar G_UMULH in LegalizerHelper using multiplyRegisters helper function. NarrowScalar G_UMULH for MIPS32. Differential Revision: https://reviews.llvm.org/D58825 llvm-svn: 355815
* [MIPS GlobalISel] NarrowScalar G_MULPetar Avramovic2019-03-113-38/+88
| | | | | | | | | | | | | Narrow Scalar G_MUL for MIPS32. Revisit NarrowScalar implementation in LegalizerHelper. Introduce new helper function multiplyRegisters. It performs generic multiplication of values held in multiple registers. Generated instructions use only types NarrowTy and i1. Destination can be same or two times size of the source. Differential Revision: https://reviews.llvm.org/D58824 llvm-svn: 355814
* [X86] Enable sse2_cvtsd2ss intrinsic to use an EVEX encoded instruction.Craig Topper2019-03-112-8/+9
| | | | llvm-svn: 355810
* [X86] Remove apparently unneeded patterns for storing a bitcasted ↵Craig Topper2019-03-111-12/+0
| | | | | | | | extractelement. I suspect if this pattern was seen, DAG combine would just change the type of the store to eliminate the bitcast. llvm-svn: 355809
* [X86] Use 'UseAVX' in place of 'HasAVX, NoAVX512'. NFCCraig Topper2019-03-111-1/+1
| | | | | | They mean the same thing, but 'HasAVX, NoAVX512' only appears in this one place. Every other place uses UseAVX. llvm-svn: 355808
* [X86] Add SCALAR_SINT_TO_FP/SCALAR_UINT_TO_FP ISD opcodes without rounding mode.Craig Topper2019-03-115-22/+29
| | | | | | After this we no longer need to match FROUND_CURRENT or FROUND_NO_EXC during isel so I remove those. llvm-svn: 355807
* [X86] Split SCALEF(S) ISD opcodes into a version without rounding mode.Craig Topper2019-03-115-66/+56
| | | | llvm-svn: 355806
* [X86] Split RCP28/RSQRT/GETEXP/EXP2 ISD opcodes into SAE and current ↵Craig Topper2019-03-115-98/+99
| | | | | | direction nodes. Remove rounding mode operand. llvm-svn: 355805
* [X86] Rename _RND versions of RANGE/REDUCE/GETMANT/RDNSCALE ISD opcodes to ↵Craig Topper2019-03-115-155/+124
| | | | | | | | _SAE. Remove SAE operand. No need to explicitly store it and match it during isel. llvm-svn: 355804
* [X86] Rename X86ISD::CVTPH2PS_RND to CVTPH2PS_SAE. Remove SAE operand.Craig Topper2019-03-115-10/+8
| | | | llvm-svn: 355803
* [X86] Rename the CVTT*_RND ISD nodes to _SAE and remove the SAE operand. ↵Craig Topper2019-03-115-101/+158
| | | | | | | | Split VFPROUNDS_RND/VFPEXT(S)_RND into versions without rounding operand. For VFPEXT(S) we only need current rounding mode and an SAE version. Neither need extra operand. llvm-svn: 355802
* [X86] Rename X86ISD::CMPM_RND and X86ISD::FSETCCM_RND to _SAE instead of ↵Craig Topper2019-03-116-35/+22
| | | | | | | | _RND. Remove rounding operand. The operand could only be the SAE encoding so no need to include it. llvm-svn: 355801
* [X86] Split the VFIXUPIMM/VFIXUPIMMS nodes into a current rounding mode and ↵Craig Topper2019-03-115-92/+84
| | | | | | | | SAE ISD opcode. Remove matching of FROUND_CURRENT and FROUND_NO_EXC for these nodes from isel table. llvm-svn: 355800
* [X86] Begin removing matching of FROUND_CURRENT and FROUND_NO_EXC from isel ↵Craig Topper2019-03-115-74/+111
| | | | | | | | | | tables. Instead I plan to have dedicated nodes for FROUND_CURRENT and FROUND_NO_EXC. This patch starts with FADDS/FSUBS/FMULS/FDIVS/FMAXS/FMINS/FSQRTS. llvm-svn: 355799
* [PowerPC] Remove the override of isMachineVerifierClean() to open machine ↵Zi Xuan Wu2019-03-111-4/+0
| | | | | | | | | | | | | | | | verifier After fix all asserts found by machine verifier in PowerPC target with following patches, we can activate machine verifier as default. rL293769, rL348566, rL349030, rL349029, rL350113, rL350111, rL350799, rL350165, rL355378, rL352174, rL354762, rL350115 It's also found in PR#27456, https://bugs.llvm.org/show_bug.cgi?id=27456 Differential Revision: https://reviews.llvm.org/D59011 llvm-svn: 355798
* [X86] Remove unneeded isel patterns from VCVTSI2SDZ and VCVTUSI2SDZ. NFCCraig Topper2019-03-111-3/+3
| | | | | | | | We had patterns using X86ISD::SCALAR_SINT_TO_FP_RND/SCALAR_UINT_TO_FP_RND for these instructions. There's nothing to round. Instead, we use a regular sint_to_fp/uint_to_fp and a movsd as the pattern for these. llvm-svn: 355796
* [X86] Remove VCVTSI2SDZrrb_Int as it shouldn't exist.Craig Topper2019-03-112-2/+1
| | | | | | This would convert a signed 32-bit integer to double precision with rounding. But there's nothing to round. llvm-svn: 355795
* Remove redundant extractBooleanFlip argument. NFCAmaury Sechet2019-03-111-3/+5
| | | | llvm-svn: 355794
* [x86] add x86-specific opcodes to extractelement scalarization listSanjay Patel2019-03-101-4/+8
| | | | llvm-svn: 355792
* [CGP] fix comments; NFCSanjay Patel2019-03-101-2/+2
| | | | llvm-svn: 355791
* [X86] Remove unused variable. NFCCraig Topper2019-03-101-1/+0
| | | | llvm-svn: 355790
* [X86] Make lowering of intrinsics with rounding mode stricter so that only ↵Craig Topper2019-03-102-32/+68
| | | | | | | | | | valid rounding modes are lowered. Update tests accordingly Many of our tests were not using valid rounding mode immediates. Clang verifies this in the frontend when it creates the intrinsics from builtins, but the backend would still lower invalid immediates. With this change we will now leave them as intrinsics if the immediate is invalid. This will cause an isel selection failure. llvm-svn: 355789
* [X86] Remove dead code from the handler for INTR_TYPE_SCALAR_MASK_RM.Craig Topper2019-03-101-13/+3
| | | | | | The code in here handles nodes with 6 or 7 operands. But only the 6 operand case is ever used these days. llvm-svn: 355788
* Recommit r355224 "[TableGen][SelectionDAG][X86] Add specific isel matchers ↵Craig Topper2019-03-105-59/+59
| | | | | | | | | | | | | | | | | | for immAllZerosV/immAllOnesV. Remove bitcasts from X86 patterns that are no longer necessary." Includes a fix to emit a CheckOpcode for build_vector when immAllZerosV/immAllOnesV is used as a pattern root. This means it can't be used to look through bitcasts when used as a root, but that's probably ok. This extra CheckOpcode will ensure that the first match in the isel table will be a SwitchOpcode which is needed by the caching optimization in the ISel Matcher. Original commit message: Previously we had build_vector PatFrags that called ISD::isBuildVectorAllZeros/Ones. Internally the ISD::isBuildVectorAllZeros/Ones look through bitcasts, but we aren't able to take advantage of that in isel. Instead of we have to canonicalize the types of the all zeros/ones build_vectors and insert bitcasts. Then we have to pattern match those exact bitcasts. By emitting specific matchers for these 2 nodes, we can make isel look through any bitcasts without needing to explicitly match them. We should also be able to remove the canonicalization to vXi32 from lowering, but I've left that for a follow up. This removes something like 40,000 bytes from the X86 isel table. Differential Revision: https://reviews.llvm.org/D58595 llvm-svn: 355784
* [ValueTracking] Move constant range computation into ValueTracking; NFCNikita Popov2019-03-092-238/+239
| | | | | | | | | | | | | | | | InstructionSimplify currently has some code to determine the constant range of integer instructions for some simple cases. It is used to simplify icmps. This change moves the relevant code into ValueTracking as llvm::computeConstantRange(), so it can also be reused for other purposes. In particular this is with the optimization of overflow checks in mind (ref D59071), where constant ranges cover some cases that known bits don't. llvm-svn: 355781
* [RISCV][NFC] Minor refactoring of CC_RISCVAlex Bradbury2019-03-091-7/+7
| | | | | | | Immediately check if we need to early-exit as we have a return value that can't be returned directly. Also tweak following if/else. llvm-svn: 355773
* [RISCV][NFC] Split out emitSelectPseudo from EmitInstrWithCustomInserterAlex Bradbury2019-03-091-16/+19
| | | | | | It's cleaner and more consistent to have a separate helper function here. llvm-svn: 355772
* [RISCV] Support -target-abi at the MC layer and for codegenAlex Bradbury2019-03-0910-15/+131
| | | | | | | | | | | | | | | | This patch adds proper handling of -target-abi, as accepted by llvm-mc and llc. Lowering (codegen) for the hard-float ABIs will follow in a subsequent patch. However, this patch does add MC layer support for the hard float and RVE ABIs (emission of the appropriate ELF flags https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#-file-header). ABI parsing must be shared between codegen and the MC layer, so we add computeTargetABI to RISCVUtils. A warning will be printed if an invalid or unrecognized ABI is given. Differential Revision: https://reviews.llvm.org/D59023 llvm-svn: 355771
* [WebAssembly] Use named operands to identify loads and storesThomas Lively2019-03-098-135/+42
| | | | | | | | | | | | | | | | | | | Summary: Uses the named operands tablegen feature to look up the indices of offset, address, and p2align operands for all load and store instructions. This replaces brittle, incorrect logic for identifying loads and store when eliminating frame indices, which previously crashed on bulk-memory ops. It also cleans up the SetP2Alignment pass. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59007 llvm-svn: 355770
* Refactor isBooleanFlip into extractBooleanFlip so that users do not depend ↵Amaury Sechet2019-03-091-19/+28
| | | | | | on the patern matched. NFC llvm-svn: 355769
* [ScalarizeMaskedMemIntrin] Use IRBuilder functions that take ↵Craig Topper2019-03-091-43/+29
| | | | | | | | | | | | uint32_t/uint64_t for getelementptr, extractelement, and insertelement. This saves needing to call getInt32 ourselves. Making the code a little shorter. The test changes are because insert/extract use getInt64 internally. Shouldn't be a functional issue. This cleanup because I plan to write similar code for expandload/compressstore. llvm-svn: 355767
* Rename a local variable counter to Counter.Wei Mi2019-03-081-3/+3
| | | | llvm-svn: 355759
* [RegisterCoalescer][NFC] bind a DenseMap access to a reference to avoidWei Mi2019-03-081-2/+3
| | | | | | repeated lookup operations llvm-svn: 355757
* [ScalarizeMaskedMemIntrin] Only set the ModifiedDT flag if new basic blocks ↵Craig Topper2019-03-081-12/+16
| | | | | | | | | | were added. There are special cases in the scalarization for constant masks. If we hit one of the special cases we don't need to reset the iteration. Noticed while starting work on adding expandload/compressstore to this pass. llvm-svn: 355754
* [RISCV] Allow access to FP CSRs without F extensionAna Pazos2019-03-081-2/+0
| | | | | | | | | | | | | | | | | | Summary: Floating-point CSRs should be accessible even when F extension is not enabled. But pseudo instructions that access floating point CSRs still require the F extension. GNU tools already implement this behavior. RISC-V spec is pending update to reflect this behavior and to extend it to pseudo instructions that access floating point CSRs. Reviewers: asb Reviewed By: asb Subscribers: asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, llvm-commits Differential Revision: https://reviews.llvm.org/D58932 llvm-svn: 355753
* [CodeGenPrepare] Fix ModifiedDT flag in optimizeSelectInstRong Xu2019-03-081-16/+10
| | | | | | | | | | | | | | | r44412 fixed a huge compile time regression but it needed ModifiedDT flag to be maintained correctly in optimizations in optimizeBlock() and optimizeInst(). Function optimizeSelectInst() does not update the flag. This patch propagates the flag in optimizeSelectInst() back to optimizeBlock(). This patch also removes ModifiedDT in CodeGenPrepare class (which is not used). The property of ModifiedDT is now recorded in a ref parameter. Differential Revision: https://reviews.llvm.org/D59139 llvm-svn: 355751
* [AArch64][GlobalISel] Fix i1 arguments not being zero-extended as required ↵Amara Emerson2019-03-081-0/+3
| | | | | | | | by ABI. Fixes PR41001. llvm-svn: 355745
* Improve "llvm-nm -f sysv" output for Elf filesSunil Srivastava2019-03-081-0/+10
| | | | | | | | | | Specifically, compute and Print Type and Section columns. This is a re-commit of rL354833, after fixing the Asan problem found a a buildbot. Differential Revision: https://reviews.llvm.org/D59060 llvm-svn: 355742
* [x86] scalarize extract element 0 of FP cmpSanjay Patel2019-03-081-0/+16
| | | | | | | | | | | | | An extension of D58282 noted in PR39665: https://bugs.llvm.org/show_bug.cgi?id=39665 This doesn't answer the request to use movmsk, but that's an independent problem. We need this and probably still need scalarization of FP selects because we can't do that as a target-independent transform (although it seems likely that targets besides x86 should have this transform). llvm-svn: 355741
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