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* R600/SI: Don't print scc reg in sopc assembly stringTom Stellard2015-03-121-1/+1
| | | | | | This is how the proprietary driver prints sopc instructions. llvm-svn: 232106
* R600/SI: Remove _e32 and _e64 suffixes from mnemonicsTom Stellard2015-03-125-25/+41
| | | | | | | | Instead print them as part of the $dst operand. The AsmMatcher requires the 32-bit and 64-bit encodings have the same mnemonic in order to parse them correctly. llvm-svn: 232105
* Migrate the AArch64 TargetRegisterInfo to its TargetMachineEric Christopher2015-03-128-48/+52
| | | | | | | implementation. This requires a bit of scaffolding and a few fixups that'll go away once all of the ports have been migrated. llvm-svn: 232103
* Remove unused headers.Eric Christopher2015-03-121-2/+0
| | | | llvm-svn: 232102
* Revert "r232027 - Add infrastructure for support of multiple memory constraints"Hal Finkel2015-03-1215-60/+42
| | | | | | | | | | | | | | | | | | | | | | | | This (r232027) has caused PR22883; so it seems those bits might be used by something else after all. Reverting until we can figure out what else to do. Original commit message: The operand flag word for ISD::INLINEASM nodes now contains a 15-bit memory constraint ID when the operand kind is Kind_Mem. This constraint ID is a numeric equivalent to the constraint code string and is converted with a target specific hook in TargetLowering. This patch maps all memory constraints to InlineAsm::Constraint_m so there is no functional change at this point. It just proves that using these previously unused bits in the encoding of the flag word doesn't break anything. The next patch will make each target preserve the current mapping of everything to Constraint_m for itself while changing the target independent implementation of the hook to return Constraint_Unknown appropriately. Each target will then be adapted in separate patches to use appropriate Constraint_* values. llvm-svn: 232093
* [X86] Fix a regression introduced by r223641.Quentin Colombet2015-03-122-2/+7
| | | | | | | | | | | | | The permps and permd instructions have their operands swapped compared to the intrinsic definition. Therefore, they do not fall into the INTR_TYPE_2OP category. I did not create a new category for those two, as they are the only one AFAICT in that case. <rdar://problem/20108262> llvm-svn: 232085
* Fix comment formatting.Eric Christopher2015-03-121-2/+1
| | | | llvm-svn: 232076
* Remove the need to cache the subtarget in the X86 TargetRegisterInfoEric Christopher2015-03-123-24/+23
| | | | | | | classes. Use a Triple instead and simplify a lot of the querying logic to use lookups on the Triple. llvm-svn: 232071
* Remove unused complex patterns for addressing modes on Hexagon.Krzysztof Parzyszek2015-03-127-611/+215
| | | | llvm-svn: 232057
* make an array of constants explicitly constSanjay Patel2015-03-121-1/+1
| | | | | | | | Suggested by Craig Topper in D8184. This goes with r232047. llvm-svn: 232056
* IRBuilder: add a CreateShuffleVector function that takes an ArrayRef of intSanjay Patel2015-03-121-4/+2
| | | | | | | | | This is a convenience function to ease mask creation of ShuffleVectors in AutoUpgrade and other places. Differential Revision: http://reviews.llvm.org/D8184 llvm-svn: 232047
* [X86] Fix wrong target specific combine on SETCC nodes.Andrea Di Biagio2015-03-121-26/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Part of the folding logic implemented by function 'PerformISDSETCCCombine' only worked under the assumption that the condition code in input could have been either SETNE or SETEQ. Unfortunately that assumption was incorrect, and in some cases the algorithm ended up incorrectly folding SETCC nodes. The incorrect folding only affected SETCC dag nodes where: - one of the operands was a build_vector of all zeroes; - the other operand was a SIGN_EXTEND from a vector of MVT:i1 elements; - the condition code was neither SETNE nor SETEQ. Example: (setcc (v4i32 (sign_extend v4i1:%A)), (v4i32 VectorOfAllZeroes), setge) Before this patch, the entire dag node sequence from the example was incorrectly folded to node %A. With this patch, the dag node sequence is folded to a (xor %A, (v4i1 VectorOfAllOnes)). Added test setcc-combine.ll. Thanks to Greg Bedwell for spotting this issue. llvm-svn: 232046
* [X86, AVX] replace vextractf128 intrinsics with generic shufflesSanjay Patel2015-03-122-3/+23
| | | | | | | | | | | | | | | | | Now that we've replaced the vinsertf128 intrinsics, do the same for their extract twins. This is very much like D8086 (checked in at r231794): We want to replace as much custom x86 shuffling via intrinsics as possible because pushing the code down the generic shuffle optimization path allows for better codegen and less complexity in LLVM. This is also the LLVM sibling to the cfe D8275 patch. Differential Revision: http://reviews.llvm.org/D8276 llvm-svn: 232045
* Silencing an "enumeral and non-enumeral type in conditional expression" ↵Aaron Ballman2015-03-121-1/+1
| | | | | | warning; NFC. llvm-svn: 232035
* Add infrastructure for support of multiple memory constraints.Daniel Sanders2015-03-1215-42/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The operand flag word for ISD::INLINEASM nodes now contains a 15-bit memory constraint ID when the operand kind is Kind_Mem. This constraint ID is a numeric equivalent to the constraint code string and is converted with a target specific hook in TargetLowering. This patch maps all memory constraints to InlineAsm::Constraint_m so there is no functional change at this point. It just proves that using these previously unused bits in the encoding of the flag word doesn't break anything. The next patch will make each target preserve the current mapping of everything to Constraint_m for itself while changing the target independent implementation of the hook to return Constraint_Unknown appropriately. Each target will then be adapted in separate patches to use appropriate Constraint_* values. Reviewers: hfinkel Reviewed By: hfinkel Subscribers: hfinkel, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8171 llvm-svn: 232027
* AVX-512: Added encoding tests for VPROR, VPROL instructions,Elena Demikhovsky2015-03-121-2/+2
| | | | | | fixed opcode. llvm-svn: 232018
* Remove some unnecessary forward declarations and put a couple moreEric Christopher2015-03-128-24/+3
| | | | | | where they're supposed to reside. llvm-svn: 232014
* Remove the need to cache the subtarget in the Sparc TargetRegisterInfoEric Christopher2015-03-124-12/+11
| | | | | | classes. llvm-svn: 232013
* Remove the need to cache the subtarget in the Mips TargetRegisterInfoEric Christopher2015-03-1210-26/+26
| | | | | | classes. llvm-svn: 232012
* Reapply 'Run LICM pass after loop unrolling pass.'Kevin Qin2015-03-121-1/+12
| | | | | | | | | It's firstly committed at r231630, and reverted at r231635. Function pass InstructionSimplifier is inserted as barrier to make sure loop unroll pass won't affect on LICM pass. llvm-svn: 232011
* Remove the need to cache the subtarget in the ARM TargetRegisterInfoEric Christopher2015-03-1211-44/+39
| | | | | | | classes. Replace the frame pointer initialization with a static function that'll look it up via the subtarget on the MachineFunction. llvm-svn: 232010
* Remove the need to cache the subtarget in the AArch64 TargetRegisterInfoEric Christopher2015-03-124-21/+26
| | | | | | | classes. Replace it with a cache to the Triple and use that where applicable at the moment. llvm-svn: 232005
* [NVPTXAsmPrinter] do not print .align on function headersJingyue Wu2015-03-123-1/+5
| | | | | | | | | | | | | | | | | | | Summary: PTX does not allow .align directives on function headers. Fixes PR21551. Test Plan: test/Codegen/NVPTX/function-align.ll Reviewers: eliben, jholewinski Reviewed By: eliben, jholewinski Subscribers: llvm-commits, eliben, jpienaar, jholewinski Differential Revision: http://reviews.llvm.org/D8274 llvm-svn: 232004
* Make llvm.eh.actions an intrinsic and add docs for itReid Kleckner2015-03-121-5/+3
| | | | | | | | These docs *don't* match the way WinEHPrepare uses them yet, and verifier support isn't implemented either. The implementation will come after the documentation text is reviewed and agreed upon. llvm-svn: 232003
* Remove the need to cache the subtarget in the PowerPC TargetRegisterInfoEric Christopher2015-03-123-55/+68
| | | | | | | classes. Replace it with a cache to the TargetMachine and use that where applicable at the moment. llvm-svn: 232002
* Fix build break introduced in r231992Krzysztof Parzyszek2015-03-121-4/+2
| | | | llvm-svn: 231996
* Stop calling DwarfEHPrepare from WinEHPrepareReid Kleckner2015-03-124-52/+24
| | | | | | | | Instead, run both EH preparation passes, and have them both ignore functions with unrecognized EH personalities. Pass delegation involved some hacky code for creating an AnalysisResolver that we don't need now. llvm-svn: 231995
* Eliminate constant-extender profitability checks from Hexagon iselKrzysztof Parzyszek2015-03-127-515/+225
| | | | llvm-svn: 231992
* Move the DataLayout to the generic TargetMachine, making it mandatory.Mehdi Amini2015-03-1229-97/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: I don't know why every singled backend had to redeclare its own DataLayout. There was a virtual getDataLayout() on the common base TargetMachine, the default implementation returned nullptr. It was not clear from this that we could assume at call site that a DataLayout will be available with each Target. Now getDataLayout() is no longer virtual and return a pointer to the DataLayout member of the common base TargetMachine. I plan to turn it into a reference in a future patch. The only backend that didn't have a DataLayout previsouly was the CPPBackend. It now initializes the default DataLayout. This commit is NFC for all the other backends. Test Plan: clang+llvm ninja check-all Reviewers: echristo Subscribers: jfb, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8243 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 231987
* Fix some clang warnings in WinEHPrepareReid Kleckner2015-03-111-3/+2
| | | | llvm-svn: 231985
* Handle big index in getelementptr instructionReid Kleckner2015-03-112-21/+12
| | | | | | | | | | | | | | | CodeGen incorrectly ignores (assert from APInt) constant index bigger than 2^64 in getelementptr instruction. This is a test and fix for that. Patch by Paweł Bylica! Reviewed By: rnk Subscribers: majnemer, rnk, mcrosier, resistor, llvm-commits Differential Revision: http://reviews.llvm.org/D8219 llvm-svn: 231984
* [PowerPC] Remove canFoldAsLoad from instruction definitionsHal Finkel2015-03-115-8/+8
| | | | | | | | | | | | | | | | | The PowerPC backend had a number of loads that were marked as canFoldAsLoad (and I'm partially at fault here for copying around the relevant line of TableGen definitions without really looking at what it meant). This is not right; PPC (non-memory) instructions don't support direct memory operands, and so there is nothing a 'foldable' instruction could be folded into. Noticed by inspection, no test case. The one thing we might lose by doing this is ability to fold some loads into stackmap/patchpoint pseudo-instructions. However, this was untested, and would not obviously have worked for extending loads, and I'd rather re-add support for that once it can be tested. llvm-svn: 231982
* Extended support for native Windows C++ EH outliningAndrew Kaylor2015-03-112-139/+865
| | | | | | Differential Review: http://reviews.llvm.org/D7886 llvm-svn: 231981
* Remove useMachineScheduler and replace it with subtarget optionsEric Christopher2015-03-118-65/+34
| | | | | | | | | | | | | that control, individually, all of the disparate things it was controlling. At the same time move a FIXME in the Hexagon port to a new subtarget function that will enable a user of the machine scheduler to avoid using the source scheduler for pre-RA-scheduling. The FIXME would have this removed, but involves either testcase changes or adding -pre-RA-sched=source to a few testcases. llvm-svn: 231980
* Have getCallPreservedMask and getThisCallPreservedMask take aEric Christopher2015-03-1127-51/+75
| | | | | | | MachineFunction argument so that we can grab subtarget specific features off of it. llvm-svn: 231979
* One more getCalleeSavedRegs prototype with nullptr.Eric Christopher2015-03-111-2/+1
| | | | llvm-svn: 231977
* Have getCalleeSavedRegs take a non-null MachineFunction all theEric Christopher2015-03-1116-28/+19
| | | | | | | | time. The target independent code was passing in one all the time and targets weren't checking validity before using. Update a few calls to pass in a MachineFunction where necessary. llvm-svn: 231970
* Constify AArch64CollectLOH.cpp. NFCPete Cooper2015-03-111-7/+7
| | | | llvm-svn: 231969
* [mips][microMIPS] Make usage of NOT16 by code generatorJozef Kolek2015-03-112-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D7748 llvm-svn: 231963
* Put jump tables in unique sections on COFF.Rafael Espindola2015-03-111-0/+25
| | | | | | | | | | | If a function is going in an unique section (because of -ffunction-sections for example), putting a jump table in .rodata will keep .rodata alive and that will keep alive any other function that also has a jump table. Instead, put the jump table in a unique section that is associated with the function. llvm-svn: 231961
* ARM: simplify and extend byval handlingTim Northover2015-03-115-240/+110
| | | | | | | | | | | | | | | | | | | The main issue being fixed here is that APCS targets handling a "byval align N" parameter with N > 4 were miscounting what objects were where on the stack, leading to FrameLowering setting the frame pointer incorrectly and clobbering the stack. But byval handling had grown over many years, and had multiple layers of cruft trying to compensate for each other and calculate padding correctly. This only really needs to be done once, in the HandleByVal function. Elsewhere should just do what it's told by that call. I also stripped out unnecessary APCS/AAPCS distinctions (now that Clang emits byvals with the correct C ABI alignment), which simplified HandleByVal. rdar://20095672 llvm-svn: 231959
* Remove the need to cache the subtarget in the R600 TargetRegisterInfoEric Christopher2015-03-1112-66/+64
| | | | | | classes. llvm-svn: 231954
* Have getRegPressureSetLimit take a MachineFunction so that aEric Christopher2015-03-113-4/+6
| | | | | | we can inspect the subtarget and function when computing values. llvm-svn: 231951
* InstCombine: Don't fold call bitcast into args if callee is byvalDavid Majnemer2015-03-111-1/+4
| | | | | | | This fixes a bug reported here: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20150309/265341.html llvm-svn: 231948
* Updated with list of possible improvements we are tracking internallyKit Barton2015-03-112-0/+40
| | | | llvm-svn: 231946
* Add the "vbroadcasti128" instruction back.Juergen Ributzka2015-03-111-0/+5
| | | | | | | | | | This is a follow-up to r231182. This adds the "vbroadcasti128" instruction back, but without the intrinsic mapping. Also add a test to check the instriction encoding. This is related to rdar://problem/18742778. llvm-svn: 231945
* Make NaCl's use of .init_array for static constructors match LinuxDerek Schuff2015-03-113-6/+7
| | | | | | | | | | | | Summary: The generic ELF TargetObjectFile defaults to .ctors, but Linux's defaults to .init_array by calling InitializeELF with the value of UseInitArray from TargetMachine. Make NaCl's behavior match. Reviewers: jvoung Differential Revision: http://reviews.llvm.org/D8240 llvm-svn: 231934
* Wrap in __MINGW32__ to avoid warnings from msvc.Benjamin Kramer2015-03-111-1/+3
| | | | llvm-svn: 231933
* Add missing namespace specifier for MSVC.Benjamin Kramer2015-03-111-1/+1
| | | | llvm-svn: 231930
* RtlCaptureContext is absent from the mingw32 headers, provide a prototype.Benjamin Kramer2015-03-111-1/+4
| | | | llvm-svn: 231929
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