summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* [ValueTracking] Use APInt::setAllBits and APInt::intersects to simplify some ↵Craig Topper2017-04-211-3/+4
| | | | | | code. NFC llvm-svn: 300997
* [APInt] Add compare/compareSigned methods that return -1, 0, 1. Reimplement ↵Craig Topper2017-04-211-35/+9
| | | | | | | | | | | | | | | | slt/ult and friends using them Currently sle and ule have to call slt/ult and eq to get the proper answer. This results in extra code for both calls and additional scans of multiword APInts. This patch replaces slt/ult with a compareSigned/compare that can return -1, 0, or 1 so we can cover all the comparison functions with a single call. While I was there I removed the activeBits calls and other checks at the start of the slow part of ult. Both of the activeBits calls potentially scan through each of the APInts separately. I can't imagine that's any better than just scanning them in parallel and doing the compares. Now we just share the code with tcCompare. These changes seem to be good for about a 7-8k reduction on the size of the opt binary on my local x86-64 build. Differential Revision: https://reviews.llvm.org/D32339 llvm-svn: 300995
* [globalisel][tablegen] Import SelectionDAG's rule predicates and support the ↵Daniel Sanders2017-04-214-9/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | equivalent in GIRule. Summary: The SelectionDAG importer now imports rules with Predicate's attached via Requires, PredicateControl, etc. These predicates are implemented as bitset's to allow multiple predicates to be tested together. However, unlike the MC layer subtarget features, each target only pays for it's own predicates (e.g. AArch64 doesn't have 192 feature bits just because X86 needs a lot). Both AArch64 and X86 derive at least one predicate from the MachineFunction or Function so they must re-initialize AvailableFeatures before each function. They also declare locals in <Target>InstructionSelector so that computeAvailableFeatures() can use the code from SelectionDAG without modification. Reviewers: rovka, qcolombet, aditya_nandakumar, t.p.northover, ab Reviewed By: rovka Subscribers: aemerson, rengolin, dberris, kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D31418 llvm-svn: 300993
* [SimplifyCFG] Fix the determination of PostBB in conditional store merging ↵Craig Topper2017-04-211-2/+10
| | | | | | | | | | to handle the targets on the second branch being commuted Currently we choose PostBB as the single successor of QFB, but its possible that QTB's single successor is QFB which would make QFB the correct choice. Differential Revision: https://reviews.llvm.org/D32323 llvm-svn: 300992
* [ConstHoisting] Add BFI in constanthoisting pass and select the best insertionWei Mi2017-04-211-30/+182
| | | | | | | | | | | | | | | | | | places based on it. Existing constant hoisting pass will merge a group of contants in a small range and hoist the const materialization code to the common dominator of their uses. However, if the uses are all in cold pathes, existing implementation may hoist the materialization code from cold pathes to a hot place. This may hurt performance. The patch introduces BFI to the pass and selects the best insertion places based on it. The change is controlled by an option consthoist-with-block-frequency which is off by default for now. Differential Revision: https://reviews.llvm.org/D28962 llvm-svn: 300989
* [AArch64][Falkor] Refine modeling of store-release exclusive instructions.Chad Rosier2017-04-212-2/+8
| | | | llvm-svn: 300987
* [Mips] Document Mips Backend Relocation PrinciplesJoel Jones2017-04-211-0/+125
| | | | | | | | | | | This revision documents the combination of C++ and table-gen code that handles relocations and addresses. Thanks for Simon Dardis for the careful reviews. Differential Revision: https://reviews.llvm.org/D31628 llvm-svn: 300986
* [AArch64][Falkor] Refine resource needs of STRQ with register offset.Chad Rosier2017-04-212-0/+8
| | | | llvm-svn: 300984
* [LV] Model if-converted phi node costsMatthew Simpson2017-04-211-2/+10
| | | | | | | | | Phi nodes in non-header blocks are converted to select instructions after if-conversion. This patch updates the cost model to account for the selects. Differential Revision: https://reviews.llvm.org/D31906 llvm-svn: 300980
* Revert r300964 + r300970 - [globalisel][tablegen] Import SelectionDAG's rule ↵Daniel Sanders2017-04-214-48/+9
| | | | | | | | | predicates and support the equivalent in GIRule. It's causing llvm-clang-x86_64-expensive-checks-win to fail to compile and I haven't worked out why. Reverting to make it green while I figure it out. llvm-svn: 300978
* [InstCombine] prefer xor with -1 because 'not' is easier to understand (PR32706)Sanjay Patel2017-04-211-4/+14
| | | | | | | | | This matches the demanded bits behavior in the DAG and should fix: https://bugs.llvm.org/show_bug.cgi?id=32706 Differential Revision: https://reviews.llvm.org/D32255 llvm-svn: 300977
* [AArch64][Falkor] Refine loads/stores that require an extra LD pipe.Chad Rosier2017-04-212-5/+21
| | | | llvm-svn: 300976
* [AArch64][Falkor] Fix number of microops for WriteSTIdx missed in r300892.Chad Rosier2017-04-211-1/+1
| | | | llvm-svn: 300975
* [AArch64] Fix a few missed pre/post-inc in Falkor.Chad Rosier2017-04-211-5/+9
| | | | llvm-svn: 300974
* [ARM] GlobalISel: Add support for G_TRUNCDiana Picus2017-04-212-6/+26
| | | | | | | | Select them as copies. We only select if both the source and the destination are on the same register bank, so this shouldn't cause any trouble. llvm-svn: 300971
* [ARM] GlobalISel: Make struct arguments fail elegantlyDiana Picus2017-04-211-1/+2
| | | | | | | | | | | The condition in isSupportedType didn't handle struct/array arguments properly. Fix the check and add a test to make sure we use the fallback path in this kind of situation. The test deals with some common cases where the call lowering should error out. There are still some issues here that need to be addressed (tail calls come to mind), but they can be addressed in other patches. llvm-svn: 300967
* [globalisel][tablegen] Import SelectionDAG's rule predicates and support the ↵Daniel Sanders2017-04-214-9/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | equivalent in GIRule. Summary: The SelectionDAG importer now imports rules with Predicate's attached via Requires, PredicateControl, etc. These predicates are implemented as bitset's to allow multiple predicates to be tested together. However, unlike the MC layer subtarget features, each target only pays for it's own predicates (e.g. AArch64 doesn't have 192 feature bits just because X86 needs a lot). Both AArch64 and X86 derive at least one predicate from the MachineFunction or Function so they must re-initialize AvailableFeatures before each function. They also declare locals in <Target>InstructionSelector so that computeAvailableFeatures() can use the code from SelectionDAG without modification. Reviewers: rovka, qcolombet, aditya_nandakumar, t.p.northover, ab Reviewed By: rovka Subscribers: aemerson, rengolin, dberris, kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D31418 llvm-svn: 300964
* typoClement Courbet2017-04-211-1/+1
| | | | llvm-svn: 300963
* use repmovsb when optimizing forminsizeClement Courbet2017-04-211-8/+31
| | | | llvm-svn: 300960
* Rename FastString flag.Clement Courbet2017-04-215-12/+15
| | | | llvm-svn: 300959
* X86 memcpy: use REPMOVSB instead of REPMOVS{Q,D,W} for inline copiesClement Courbet2017-04-215-1/+20
| | | | | | | | | | | | when the subtarget has fast strings. This has two advantages: - Speed is improved. For example, on Haswell thoughput improvements increase linearly with size from 256 to 512 bytes, after which they plateau: (e.g. 1% for 260 bytes, 25% for 400 bytes, 40% for 508 bytes). - Code is much smaller (no need to handle boundaries). llvm-svn: 300957
* [DWARF] - Refactoring: localize handling of relocations in a single place.George Rimar2017-04-215-41/+27
| | | | | | | | | | | This is splitted from D32228, currently DWARF parsers code has few places that applied relocations values manually. These places has similar duplicated code. Patch introduces separate method that can be used to obtain relocated value. That helps to reduce code and simplifies things. Differential revision: https://reviews.llvm.org/D32284 llvm-svn: 300956
* Delete dead codeClement Courbet2017-04-211-15/+1
| | | | llvm-svn: 300952
* [Thumb1] The recently added tADCS and tSBCS pseudo-instructions were missing ↵Artyom Skrobov2017-04-211-1/+2
| | | | | | | | | | | | | | `Uses = [CPSR]` Summary: Thanks to Oliver Stannard for helping catch this. Reviewers: olista01, efriedma Subscribers: llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D31815 llvm-svn: 300951
* [AsmWriter] Eliminate warning. NFCSerguei Katkov2017-04-211-4/+4
| | | | | | | | | | | | | | This patch eliminates the following warning lib/IR/AsmWriter.cpp:1128:57: warning: suggest parentheses around '&&' within '||' [-Wparentheses] (StrVal[1] >= '0' && StrVal[1] <= '9')) && Reviewers: timshen, rnk, davide Reviewed By: davide Subscribers: davide, llvm-commits Differential Revision: https://reviews.llvm.org/D32337 llvm-svn: 300950
* [MSSA] Clean up the updater a bit. NFCGeorge Burgess IV2017-04-211-5/+4
| | | | | | | | - Mark an internal function static - Remove the llvm namespace (just holding on to the `using namespace llvm;` Works on My Machine(TM)) llvm-svn: 300947
* [PartialInliner] Fix crash when inlining functions with unreachable blocks.Davide Italiano2017-04-211-12/+13
| | | | | | | | | | | | | | | | CodeExtractor looks up the dominator node corresponding to return blocks when splitting them. If one of these blocks is unreachable, there's no node in the Dom and CodeExtractor crashes because it doesn't check for domtree node validity. In theory, we could add just a check for skipping null DTNodes in `splitReturnBlock` but the fix I propose here is slightly different. To the best of my knowledge, unreachable blocks are irrelevant for the algorithm, therefore we can just skip them when building the candidate set in the constructor. Differential Revision: https://reviews.llvm.org/D32335 llvm-svn: 300946
* [AsmWriter/APFloat] FP constant printing: Avoid usage of locale dependent ↵Serguei Katkov2017-04-212-31/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | snprinf This should fix the bug https://bugs.llvm.org/show_bug.cgi?id=12906 To print the FP constant AsmWriter does the following: 1) convert FP value to String (actually using snprintf function which is locale dependent). 2) Convert String back to FP Value 3) Compare original and got FP values. If they are not equal just dump as hex. The problem happens on the 2nd step when APFloat does not expect group delimiter or fraction delimiter other than period symbol and so on, which can be produced on the first step if LLVM library is used in an environment with corresponding locale set. To fix this issue the locale independent APFloat:toString function is used. However it prints FP values slightly differently than snprintf does. Specifically it suppress trailing zeros in significant, use capital E and so on. It results in 117 test failures during make check. To avoid this I've also updated APFloat.toString a bit to pass make check at least. Reviewers: sberg, bogner, majnemer, sanjoy, timshen, rnk Reviewed By: timshen, rnk Subscribers: rnk, llvm-commits Differential Revision: https://reviews.llvm.org/D32276 llvm-svn: 300943
* Revert r300932 and r300930.Akira Hatanaka2017-04-217-186/+37
| | | | | | | | | It seems that r300930 was creating an infinite loop in dag-combine when compling the following file: MultiSource/Benchmarks/MiBench/consumer-typeset/z21.c llvm-svn: 300940
* [AArch64] Use suffix ULL to shift a 64-bit value.Akira Hatanaka2017-04-211-1/+1
| | | | llvm-svn: 300932
* [CodeExtractor] Remove an unneeded level of indirection. NFCI.Davide Italiano2017-04-211-11/+6
| | | | llvm-svn: 300931
* [AArch64] Improve code generation for logical instructions takingAkira Hatanaka2017-04-217-37/+186
| | | | | | | | | | | | | | | | | | | | immediate operands. This commit adds an AArch64 dag-combine that optimizes code generation for logical instructions taking immediate operands. The optimization uses demanded bits to change a logical instruction's immediate operand so that the immediate can be folded into the immediate field of the instruction. This recommits r300913, which broke bots because I didn't fix a call to ShrinkDemandedConstant in SIISelLowering.cpp after changing the APIs of TargetLoweringOpt and TargetLowering. rdar://problem/18231627 Differential Revision: https://reviews.llvm.org/D5591 llvm-svn: 300930
* Revert r300746 (SCEV analysis for or instructions).Eli Friedman2017-04-201-6/+22
| | | | | | | | There have been multiple reports of this causing problems: a compile-time explosion on the LLVM testsuite, and a stack overflow for an opencl kernel. llvm-svn: 300928
* [InstCombine] Remove the zextOrTrunc from ShrinkDemandedConstant.Craig Topper2017-04-201-4/+2
| | | | | | | | The demanded mask and the constant should always be the same width for all callers today. Also stop copying the demanded mask as its passed in. We should avoid allocating memory unless we are going to do something. The final AND to create the new constant will take care of it. llvm-svn: 300927
* X86RegisterInfo: eliminateFrameIndex: Avoid code duplication; NFCMatthias Braun2017-04-203-35/+23
| | | | | | | | | | | | | | X86RegisterInfo::eliminateFrameIndex() and X86FrameLowering::getFrameIndexReference() both had logic to compute the base register. This consolidates the code. Also use MachineInstr::isReturn instead of manually enumerating tail call instructions (return instructions were not included in the previous list because they never reference frame indexes). Differential Revision: https://reviews.llvm.org/D32206 llvm-svn: 300923
* X86RegisterInfo: eliminateFrameIndex: Force SP for AfterFPPop; NFCMatthias Braun2017-04-201-3/+4
| | | | | | | | | | | | | AfterFPPop is used for tailcall/tailjump instructions. We shouldn't ever have frame-pointer/base-pointer relative addressing for those. After all the frame/base pointer should already be restored to their previous values at the return. Make this fact explicit in preparation for an upcoming refactoring. Differential Revision: https://reviews.llvm.org/D32205 llvm-svn: 300922
* Revert "[AArch64] Improve code generation for logical instructions taking"Akira Hatanaka2017-04-206-185/+36
| | | | | | | | This reverts r300913. This broke bots. llvm-svn: 300916
* [AArch64] Improve code generation for logical instructions takingAkira Hatanaka2017-04-206-36/+185
| | | | | | | | | | | | | | | | immediate operands. This commit adds an AArch64 dag-combine that optimizes code generation for logical instructions taking immediate operands. The optimization uses demanded bits to change a logical instruction's immediate operand so that the immediate can be folded into the immediate field of the instruction. rdar://problem/18231627 Differential Revision: https://reviews.llvm.org/D5591 llvm-svn: 300913
* [InstCombine] function names start with lower-case letter; NFCSanjay Patel2017-04-202-3/+3
| | | | | | Forgot to make this fix with the signature change in r300911. llvm-svn: 300912
* [InstCombine] allow shl+shr demanded bits folds with splat constantsSanjay Patel2017-04-202-22/+17
| | | | llvm-svn: 300911
* AArch64: lower "fence singlethread" to a pure compiler barrier.Tim Northover2017-04-204-0/+14
| | | | | | | | Single-threaded fences aren't required to provide any synchronization with other processing elements so there's no need for a DMB. They should still be a barrier for compiler optimizations though. llvm-svn: 300905
* ARM: lower "fence singlethread" to a pure compiler barrier.Tim Northover2017-04-202-1/+12
| | | | | | | | Single-threaded fences aren't required to provide any synchronization with other processing elements so there's no need for a DMB. They should still be a barrier for compiler optimizations though. llvm-svn: 300904
* Use basicblock split block utility functionXinliang David Li2017-04-201-8/+2
| | | | | | | | | Instead of calling BasicBlock::SplitBasicBlock directly in CodeExtractor. Differential Revision: https://reviews.llvm.org/D32308 llvm-svn: 300899
* [InstCombine] allow shl demanded bits folds with splat constantsSanjay Patel2017-04-201-2/+4
| | | | | | More fixes are needed to enable the helper SimplifyShrShlDemandedBits(). llvm-svn: 300898
* [InstCombine] Use APInt::intersects and APInt::isSubsetOf to improve a few ↵Craig Topper2017-04-201-4/+4
| | | | | | more places in SimplifyDemandedBits. llvm-svn: 300896
* [AArch64] Whitespace/ordering fixes for Falkor machine description. NFC.Chad Rosier2017-04-201-2/+4
| | | | llvm-svn: 300893
* [AArch64] Refine Falkor machine description for pre/post-inc and stores.Chad Rosier2017-04-201-5/+5
| | | | llvm-svn: 300892
* [InstCombine] allow ashr/lshr demanded bits folds with splat constantsSanjay Patel2017-04-201-11/+14
| | | | llvm-svn: 300888
* [InstCombine] Use APInt::isSubsetOf to simplify some code in ↵Craig Topper2017-04-201-37/+27
| | | | | | | | SimplifyDemandedBits. NFC This allows us to use less temporary APInt for And and Invert operations. llvm-svn: 300885
* Don't emit locations that need a DW_OP_stack_value in DWARF 2 & 3.Adrian Prantl2017-04-202-1/+10
| | | | | | https://bugs.llvm.org/show_bug.cgi?id=32382 llvm-svn: 300883
OpenPOWER on IntegriCloud