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* [PM] Make LowerAtomic a FunctionPass.Davide Italiano2016-05-121-5/+16
| | | | | | Differential Revision: http://reviews.llvm.org/D20025 llvm-svn: 269322
* [LoopVectorizer] LoopVectorBody doesn't need to be a vector. NFC.Michael Kuperstein2016-05-121-40/+22
| | | | | | | | | | | LoopVectorBody was changed from a single pointer to a SmallVector when store predication was introduced in r200270. Since r247139, store predication no longer splits the vector loop body in-place, so we can go back to having a single LoopVectorBody block. This reverts the no-longer-needed changes from r200270. llvm-svn: 269321
* [yaml2macho] Handle mach_header_64 reserved fieldChris Bieneman2016-05-121-0/+2
| | | | | | I've added the reserved field as an "optional" in YAML, but I've added asserts in the yaml2macho code to enforce that the field is present in mach_header_64, but not in mach_header. llvm-svn: 269320
* [ObjectYAML] filetype is a required field in MachO headersChris Bieneman2016-05-121-1/+1
| | | | | | Not sure how I managed to copy-pasta this wrong, but I did. llvm-svn: 269317
* Get rid of CVLeafTypes.def and combine with TypeRecords.defZachary Turner2016-05-121-26/+17
| | | | | | | | | | This merges the functionality of the macros in `CVLeafTypes.def` and the macros in `TypeRecords.def` into a single set of macros. Differential Revision: http://reviews.llvm.org/D20190 Reviewed By: rnk, amccarth llvm-svn: 269316
* Make CodeView record serialization more generic.Zachary Turner2016-05-123-98/+158
| | | | | | | | | | | This introduces a variadic template and some helper macros to safely and correctly deserialize many types of common record fields while maintaining error checking. Differential Revision: http://reviews.llvm.org/D20183 Reviewed By: rnk, amccarth llvm-svn: 269315
* [obj2yaml] Include all mach_header fields in yamlChris Bieneman2016-05-121-1/+3
| | | | | | Since we want to be able to use yaml to describe degenerate object files as well as valid ones, we need to be explicit of some fields in your yaml definitions. llvm-svn: 269313
* [Hexagon] Properly handle instruction selection of vsplat intrinsicsKrzysztof Parzyszek2016-05-121-2/+3
| | | | llvm-svn: 269312
* Fix option description /NFCXinliang David Li2016-05-121-2/+2
| | | | llvm-svn: 269307
* [ObjectYAML] Support Thin MachO headers to YAMLChris Bieneman2016-05-122-0/+45
| | | | | | This patch adds support to ObjectYAML for serializing mach_header structs. llvm-svn: 269303
* [mips][ias] Fix O32 .cprestore directive when inside .set noat region and ↵Daniel Sanders2016-05-123-19/+34
| | | | | | | | | | | | | | | | | | offset is in range. Summary: This expands on r269179 to fix an additional case that was not covered by our tests. The assembler temporary is not needed when the .cprestore offset fits inside a simm16 and it is not an error to use it inside a '.set noat' in this case. Reviewers: emaste, seanbruno, sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20199 llvm-svn: 269295
* [mips][ias] Work around incorrect another microMIPS relocation evaluation ↵Daniel Sanders2016-05-121-1/+1
| | | | | | | | | | | | | | | | | | | | exposed by r268900 As explained in r269196, microMIPS has a special case that is not correctly implemented in LLVM. If we have a symbol 'foo' which is equivalent to '.text+0x10'. The value of an R_MICROMIPS_LO16 relocation using 'foo' is 'foo+0x11' and not 'foo+0x10'. The in-place addend should therefore be 0x11. This commit reverts a little more of the effect of r268900 by keeping the symbol when the STO_MIPS_MICROMIPS flag is set for R_MIPS_GPREL32 relocations. This fixes SingleSource/UnitTests/2003-08-11-VaListArg, and SingleSource/UnitTests/2003-05-07-VarArgs for microMIPS. I believe there are additional relocations that have the same issue (e.g. R_MIPS_64, and R_MIPS_GPREL16) but for now I'm focusing on restoring our internal buildbots back to the green state we had in r268899. llvm-svn: 269294
* [AArch64] Remove command-line option use for testing.Chad Rosier2016-05-121-8/+0
| | | | | | | The EXTR combine has been in tree for over 2 years without complain, so go ahead and remove the option. llvm-svn: 269292
* [SelectionDAG] Attempt to split BITREVERSE vector legalization into BSWAP ↵Simon Pilgrim2016-05-121-5/+32
| | | | | | | | | | | | | | and BITREVERSE stages For BITREVERSE, bit shifting/masking every bit in a vector element is a very lengthy procedure. If the input vector type is a whole multiple of bytes wide then we can split this into a BSWAP shuffle stage (to reverse at the byte level) and then a BITREVERSE stage applied to each byte. Most vector capable targets can efficiently BSWAP using shuffles resulting in a considerable reduction in instructions. With this patch targets would only need to implement a target specific vXi8 BITREVERSE implementation to efficiently reverse most legal vector types. Differential Revision: http://reviews.llvm.org/D19978 llvm-svn: 269290
* Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions"Hrvoje Varga2016-05-1210-190/+8
| | | | | | This reverts commit r269176 as it caused test-suite failure. llvm-svn: 269287
* Refactor duplicated code. NFC.Rafael Espindola2016-05-122-33/+39
| | | | | | Linkage is always followed by visibility and dll storage. llvm-svn: 269286
* [scan-build] fix warnings emitted on LLVM ARM code baseRenato Golin2016-05-122-2/+4
| | | | | | | | | Fix "Logic error" warnings of the type "Called C++ object pointer is null" reported by Clang Static Analyzer. Patch by Apelete Seketeli. llvm-svn: 269285
* [mips][ias] Correct ELF eflags when Octeon is the target.Daniel Sanders2016-05-123-15/+28
| | | | | | | | | | Reviewers: sdardis Subscribers: petarj, mpf, dsanders, spetrovic, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D18899 llvm-svn: 269283
* [mips][ias] Handle N64 compound relocations and R_MIPS_SUB in ↵Daniel Sanders2016-05-121-5/+6
| | | | | | | | | | | | | | | | | | | needsRelocateWithSymbol() Summary: This eliminates the default case for N64 that was left out of r269047. The change to R_MIPS_SUB is needed in this patch to make this testable since %lo(%neg(%gp_rel(foo))) and %hi(%neg(%gp_rel(foo))) remain the only ways to get a compound relocation from the assembler. Reviewers: sdardis, rafael Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D20097 llvm-svn: 269280
* [WebAssembly] Fast-isel support for calls, arguments, and selects.Dan Gohman2016-05-123-55/+331
| | | | llvm-svn: 269273
* [PowerPC] Fix a DAG replacement bug in PPCTargetLowering::DAGCombineExtBoolTruncHal Finkel2016-05-121-10/+19
| | | | | | | | | | | | | | | While promoting nodes in PPCTargetLowering::DAGCombineExtBoolTrunc, it is possible for one of the nodes to be replaced by another. To make sure we do not visit the deleted nodes, and to make sure we visit the replacement nodes, use a list of HandleSDNodes to track the to-be-promoted nodes during the promotion process. The same fix has been applied to the analogous code in PPCTargetLowering::DAGCombineTruncBoolExt. Fixes PR26985. llvm-svn: 269272
* [SCCP] Resolve shifts beyond the bitwidth to undefDavid Majnemer2016-05-121-0/+16
| | | | | | | | | Shifts beyond the bitwidth are undef but SCCP resolved them to zero. Instead, DTRT and resolve them to undef. This reimplements the transform which caused PR27712. llvm-svn: 269269
* AMDGPU: Fix getIntegerAttribute type and error messageMatt Arsenault2016-05-122-4/+6
| | | | llvm-svn: 269268
* [Layout] Add a new option (NFC)Xinliang David Li2016-05-121-1/+7
| | | | | | | | | | Currently cost based loop rotation algo can only be turned on with two conditions: the function has real profile data, and -precise-rotation-cost flag is turned on. This is not convenient for developers to experiment when profile is not available. Add a new option to force the new rotation algorithm -force-precise-rotation-cost llvm-svn: 269266
* AMDGPU: Fix breaking IR on instructions with multiple pointer operandsMatt Arsenault2016-05-121-8/+91
| | | | | | | | | | | | | The promote alloca pass would attempt to promote an alloca with a select, icmp, or phi user, even though the other operand was from a non-promotable source, producing a select on two different pointer types. Only do this if we know that both operands derive from the same alloca. In the future we should be able to relax this to an alloca which will also be promoted. llvm-svn: 269265
* [AArch64] Add support for unscaled narrow stores in getUsefulBitsForUse.Chad Rosier2016-05-121-0/+2
| | | | llvm-svn: 269263
* Appease MSVC with curly bracesSanjoy Das2016-05-121-1/+2
| | | | llvm-svn: 269262
* All llvm.deoptimize declarations must use the same calling conventionSanjoy Das2016-05-122-2/+32
| | | | | | | | | | | | | | | | | This new verifier rule lets us unambigously pick a calling convention when creating a new declaration for `@llvm.experimental.deoptimize.<ty>`. It is also congruent with our lowering strategy -- since all calls to `@llvm.experimental.deoptimize` are lowered to calls to `__llvm_deoptimize`, it is reasonable to enforce a unique calling convention. Some of the tests that were breaking this verifier rule have had to be split up into different .ll files. The inliner was violating this rule as well, and has been fixed to avoid producing invalid IR. llvm-svn: 269261
* [AArch64] Remove floating-point narrow stores from getUsefulBitsForUse.Chad Rosier2016-05-121-2/+0
| | | | | | | While not impossible, it's unlikely we'd be performing bitwise operations on FP values. llvm-svn: 269260
* SDAG: Implement Select instead of SelectImpl in ARMDAGToDAGISelJustin Bogner2016-05-121-258/+347
| | | | | | | | | | | | This is a large change, but it's pretty mechanical: - Where we were returning a node before, call ReplaceNode instead. - Where we would return null to fall back to another selector, rename the method to try* and return a bool for success. - Where we were calling SelectNodeTo, just return afterwards. Part of llvm.org/pr26808. llvm-svn: 269258
* SDAG: Clean up dangling nodes in ARMISelDAGToDAG::SelectImplJustin Bogner2016-05-121-1/+7
| | | | | | | | | When we convert to the void Select interface, leaving unreferenced nodes around won't be allowed anymore. Part of llvm.org/pr26808. llvm-svn: 269256
* Revert "[SCCP] Partially propagate informations when the input is not fully ↵Davide Italiano2016-05-111-3/+0
| | | | | | | | defined." This reverts commit r269105 as it caused PR27712. llvm-svn: 269252
* [ThinLTO] Don't re-analyze callee at same threshold unnecessarilyTeresa Johnson2016-05-111-1/+1
| | | | | | | | | This should just be a compile-time change. Correct the check for whether we have already analyzed the callee when making summary based decisions. There is no need to reprocess one at the same threshold as when it was last processed. llvm-svn: 269251
* Fix a bug when hoist spill to a BB with landingpad successor.Wei Mi2016-05-111-6/+10
| | | | | | | | | | | | | | | This is to fix the bug in https://llvm.org/bugs/show_bug.cgi?id=27612. When spill is hoisted to a BB with landingpad successor, and if the VNI of the spill reg lives into the landingpad successor, the spill should be inserted before the call which may throw exception. InsertPointAnalysis is used to compute the safe insert point. http://reviews.llvm.org/D20027 is a preparing patch for this patch. Differential Revision: http://reviews.llvm.org/D19884. llvm-svn: 269249
* [NFC] Extract LastSplitPoint computation from SplitAnalysis to a new classWei Mi2016-05-112-64/+101
| | | | | | | | | | | | InsertPointAnalysis. Because both split and spill hoisting want to use LastSplitPoint computation result, extract the LastSplitPoint computation from SplitAnalysis class which also contains a bunch of other analysises only related to split. Differential Revision: http://reviews.llvm.org/D20027. llvm-svn: 269248
* SDAG: Use ReplaceNode here, not ReplaceUsesJustin Bogner2016-05-111-1/+1
| | | | | | | | | This was a typo in an earlier commit - there's no point in keeping the old node around here. Noticed by Meador Inge. Thanks! llvm-svn: 269245
* MachineVerifier: Fix error reporting.Matthias Braun2016-05-111-4/+10
| | | | | | | Do not use getVRegDef() to print "the definition" of a vreg. If there are multiple or none the function will fail. llvm-svn: 269239
* SDAG: Add a helper to replace and remove a node during ISelJustin Bogner2016-05-111-7/+3
| | | | | | | | | It's very common to want to replace a node and then remove it since it's dead, especially as we port backends from the SDNode *Select API to the void Select one. This helper makes this sequence a bit less verbose. llvm-svn: 269236
* SDAG: Have SelectNodeTo replace uses if it CSE's instead of morphing a nodeJustin Bogner2016-05-112-9/+8
| | | | | | | | It's awkward to force callers of SelectNodeTo to figure out whether the node was morphed or CSE'd. Update uses here instead of requiring callers to (sometimes) do it. llvm-svn: 269235
* [ThinLTO] Fix Windows debug failure in new iteratorTeresa Johnson2016-05-111-2/+13
| | | | | | | | | | | | This fixes a debug assert on Windows from the new iterator implementation added in r269059. The Windows std::vector iterator operator== checks in debug mode that the containers being iterated over are the same, which they may not be. Fixed by checking that we are iterating over the same container before comparing the container iterators. llvm-svn: 269232
* [AArch64] Improve getUsefulBitsForUse for narrow stores.Chad Rosier2016-05-111-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For narrow stores (e.g., strb, srth) we know the upper bits of the register are unused/not useful. In some cases we can use this information to eliminate unnecessary instructions. For example, without this patch we generate (from the 2nd test case): ldr w8, [x0] and w8, w8, #0xfff0 bfxil w8, w2, #16, #4 strh w8, [x1] and after the patch the 'and' is removed: ldr w8, [x0] bfxil w8, w2, #16, #4 strh w8, [x1] ret During the lowering of the bitfield insert instruction the 'and' is eliminated because we know the upper 16-bits that are masked off are unused and the lower 4-bits that are masked off are overwritten by the insert itself. Therefore, the 'and' is unnecessary. Differential Revision: http://reviews.llvm.org/D20175 llvm-svn: 269226
* [ProfileData] Use SoftInstrProfErrors to count soft errors, NFCVedant Kumar2016-05-112-44/+56
| | | | | | Differential Revision: http://reviews.llvm.org/D20082 llvm-svn: 269222
* [X86][AVX512] Fixed VPERMILPD/VPERMILPS shuffle comments.Simon Pilgrim2016-05-111-2/+2
| | | | | | Fixed incorrect operands indices used to access src registers llvm-svn: 269221
* Return a StringRef from getSection.Rafael Espindola2016-05-118-9/+16
| | | | | | This is similar to how getName is handled. llvm-svn: 269218
* Fix build breakage in DebugInfoCodeviewZachary Turner2016-05-111-1/+1
| | | | llvm-svn: 269217
* Refactor CodeView type records to use common code.Zachary Turner2016-05-115-375/+269
| | | | | | | Differential Revision: http://reviews.llvm.org/D20138 Reviewed By: rnk llvm-svn: 269216
* SDAG: Minor cleanup in X86Justin Bogner2016-05-111-7/+6
| | | | | | | | Don't bother returning a result we don't use here. I've also renamed this from selectGather to tryGather to better indicate that it may not do anything. llvm-svn: 269215
* [SCEVExpander] Fix a failed cast<> assertionSanjoy Das2016-05-111-43/+47
| | | | | | | | | SCEVExpander::replaceCongruentIVs assumes the backedge value of an SCEV-analysable PHI to always be an instruction, when this is not necessarily true. For now address this by bailing out of the optimization if the backedge value of the PHI is a non-Instruction. llvm-svn: 269213
* [SCEVExpander] Don't break SSA in replaceCongruentIVsSanjoy Das2016-05-111-2/+1
| | | | | | | | | | | | `SCEVExpander::replaceCongruentIVs` bypasses `hoistIVInc` if both the original and the isomorphic increments are PHI nodes. Doing this can break SSA if the isomorphic increment is not dominated by the original increment. Get rid of the bypass, and let `hoistIVInc` do the right thing. Fixes PR27232 (compile time crash/hang). llvm-svn: 269212
* [SCEV] Be more aggressive around proving no-wrapSanjoy Das2016-05-111-4/+17
| | | | | | | | | | | | | | | ... for AddRec's in loops for which SCEV is unable to compute a max tripcount. This is not a problem for "normal" loops[0] that don't have guards or assumes, but helps in cases where we have guards or assumes in the loop that can be used to constrain incoming values over the backedge. This partially fixes PR27691 (we still don't handle the NUW case). [0]: for "normal" loops, in the cases where we'd be able to prove no-wrap via isKnownPredicate, we'd also be able to compute a max tripcount. llvm-svn: 269211
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