summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* [Hexagon] Generate PIC-specific versions of save/restore routinesKrzysztof Parzyszek2016-03-243-9/+43
| | | | | | | | | | | | In PIC mode, the registers R14, R15 and R28 are reserved for use by the PLT handling code. This causes all functions to clobber these registers. While this is not new for regular function calls, it does also apply to save/restore functions, which do not follow the standard ABI conventions with respect to the volatile/non-volatile registers. Patch by Jyotsna Verma. llvm-svn: 264324
* [Statepoints] Fix yet another issue around gc pointer uniqueingSanjoy Das2016-03-242-19/+22
| | | | | | | | | | | | | Given that StatepointLowering now uniques derived pointers before putting them in the per-statepoint spill map, we may end up with missing entries for derived pointers when we visit a gc.relocate on a pointer that was de-duplicated away. Fix this by keeping two maps, one mapping gc pointers to their de-duplicated values, and one mapping a de-duplicated value to the slot it is spilled in. llvm-svn: 264320
* Minor cosmestic changes (NFC)Sanjoy Das2016-03-241-7/+7
| | | | | | | - Reflow comments - Rename function llvm-svn: 264319
* [debuginfo] Include dwo_name in the split unit to improve dwp diagnosticsDavid Blaikie2016-03-241-1/+4
| | | | | | | | | | | | | | | | | | | When multiple DWP files are merged together and duplicate DWO IDs are found it's currently difficult to give an actionable error message - the DW_AT_name of the CU could be provided, but might be identical (if the same source file is built into two different configurations), which doesn't help the user identify the problem. When no intermediate DWP files are generated, the path to the two DWO files could be provided - but is lost once the DWOs are merged into a DWP. So, include the name of the DWO (dwo_name) in the split file so that collissions involving a source CU from a DWP can be better diagnosed. (improvements to llvm-dwp using this to come shortly) llvm-svn: 264316
* [LLE] Check for mismatching types between the store and the load earlierAdam Nemet2016-03-241-4/+6
| | | | | | | | | | | | | | | isDependenceDistanceOfOne asserts that the store and the load access through the same type. This function is also used by removeDependencesFromMultipleStores so we need to make sure we filter out mismatching types before reaching this point. Now we do this when the initial candidates are gathered. This is a refinement of the fix made in r262267. Fixes PR27048. llvm-svn: 264313
* [MC][mips] Add MipsMCInstrAnalysis class and register it as MC instruction ↵Simon Atanasyan2016-03-241-0/+36
| | | | | | | | | | | | | analyzer The `MipsMCInstrAnalysis` class overrides the `evaluateBranch` method and calculates target addresses for branch and calls instructions. That allows llvm-objdump to print functions' names in branch instructions in the disassemble mode. Differential Revision: http://reviews.llvm.org/D18209 llvm-svn: 264309
* [X86][XOP] Fixed instruction postfixes to more closely match operandsSimon Pilgrim2016-03-242-91/+91
| | | | | | Suggested by Sanjay in D18189 as the multiple folding options in XOP instructions can be tricky llvm-svn: 264305
* BitcodeWriter: Move abbreviation for GenericDINode; almost NFCDuncan P. N. Exon Smith2016-03-243-21/+19
| | | | | | | | | | | | Simplify ValueEnumerator and WriteModuleMetadata by shifting the logic for the METADATA_GENERIC_DEBUG abbreviation into WriteGenericDINode. (This is just like r264302, but for GenericDINode.) The only change is that the abbreviation is emitted later in the bitcode, just before the first `GenericDINode` record. This shouldn't be observable though. llvm-svn: 264303
* BitcodeWriter: Move abbreviation for DILocation; almost NFCDuncan P. N. Exon Smith2016-03-243-20/+18
| | | | | | | | | | | Simplify ValueEnumerator and WriteModuleMetadata by shifting the logic for the METADATA_LOCATION abbreviation into WriteDILocation. The only change is that the abbreviation is emitted later in the bitcode, just before the first `DILocation` record. This shouldn't be observable though. llvm-svn: 264302
* BitcodeWriter: Split out named metadata; almost NFCDuncan P. N. Exon Smith2016-03-241-25/+31
| | | | | | | | | | | | Split writeNamedMetadata out of WriteModuleMetadata to write named metadata, and createNamedMetadataAbbrev for the abbreviation. There should be no effective functionality change, although the layout of the bitcode will change. Previously, the abbreviation was emitted at the top of the block, but now it is delayed until immediately before the named metadata records are emitted. llvm-svn: 264301
* Bitcode: Module* -> Module&, NFCDuncan P. N. Exon Smith2016-03-241-5/+5
| | | | llvm-svn: 264299
* AVX-512: Generate KTEST instead of TEST fir i1 vectorsElena Demikhovsky2016-03-241-5/+27
| | | | | | | | | | | | KTEST instruction may be used instead of TEST in this case: %int_sel3 = bitcast <8 x i1> %sel3 to i8 %res = icmp eq i8 %int_sel3, zeroinitializer br i1 %res, label %L2, label %L1 Differential Revision: http://reviews.llvm.org/D18444 llvm-svn: 264298
* CodeGen: extend RHS when splitting ATOMIC_CMP_SWAP_WITH_SUCCESS.Tim Northover2016-03-242-3/+22
| | | | | | | | | | | | | If the operation's type has been promoted during type legalization, we need to account for the fact that the high bits of the comparison operand are likely unspecified. The LHS is usually zero-extended, but MIPS sign extends it, so we have to be slightly careful. Patch by Simon Dardis. llvm-svn: 264296
* AMDGPU/SI: Add Polaris supportTom Stellard2016-03-241-0/+8
| | | | | | Patch By: Sonny Jiang llvm-svn: 264295
* [X86][XOP] Merged 128/256 bit 4op instruction definitions. NFCI.Simon Pilgrim2016-03-241-15/+14
| | | | llvm-svn: 264294
* Define ErrorInfo::ID explicitly.NAKAMURA Takumi2016-03-241-0/+3
| | | | llvm-svn: 264293
* Fix another case where we were unconditionally linking linkonce GVs.Rafael Espindola2016-03-241-0/+6
| | | | | | | With this I think that now llvm-link, lld and the gold plugin should agree on which symbol is kept. llvm-svn: 264292
* Error.cpp: Fix a warning. [-Wpedantic]NAKAMURA Takumi2016-03-241-1/+1
| | | | llvm-svn: 264291
* Fix resolution of linkonce symbols in comdats.Rafael Espindola2016-03-241-2/+8
| | | | | | | | | | | After comdat processing, the symbols still go through regular symbol resolution. We were not doing it for linkonce symbols since they are lazy linked. This fixes pr27044. llvm-svn: 264288
* [mips] Range check vsplat_simm5 and vsplat_simm10Daniel Sanders2016-03-242-5/+6
| | | | | | | | | | | | Summary: Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18177 llvm-svn: 264287
* Remove unsafe AssertZext after promoting result of FP_TO_FP16Pirama Arumuga Nainar2016-03-241-4/+1
| | | | | | | | | | | | | | | Summary: Some target lowerings of FP_TO_FP16, for instance ARM's vcvtb.f16.f32 instruction, do not guarantee that the top 16 bits are zeroed out. Remove the unsafe AssertZext and add tests to exercise this. Reviewers: jmolloy, sbaranga, kristof.beyls, aadg Subscribers: llvm-commits, srhines, aemerson Differential Revision: http://reviews.llvm.org/D18426 llvm-svn: 264285
* [PowerPC] Disable direct moves for extractelement and bitcast in 32-bit modeNemanja Ivanovic2016-03-241-2/+2
| | | | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D17711 It disables direct moves on these operations in 32-bit mode since the patterns assume 64-bit registers. The final patch is slightly different from the Phabricator review as the bitcast operations needed to be disabled in 32-bit mode as well. This fixes PR26617. llvm-svn: 264282
* Recommitted r263424 "Supporting all entities declared in lexical scope in ↵Amjad Aboud2016-03-246-51/+211
| | | | | | | | | | LLVM debug info." After fixing PR26942 (the fix is included in this commit). Differential Revision: http://reviews.llvm.org/D18350 llvm-svn: 264280
* [mips] Range check simm10Daniel Sanders2016-03-243-4/+13
| | | | | | | | | | | | Summary: Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18148 llvm-svn: 264279
* [X86][XOP] Support for VPPERM byte shuffle instructionSimon Pilgrim2016-03-245-3/+49
| | | | | | | | This patch begins adding support for lowering to the XOP VPPERM instruction - adding the X86ISD::VPPERM opcode. Differential Revision: http://reviews.llvm.org/D18189 llvm-svn: 264260
* [mips] Tidy up cnMIPS tablegen definitions. NFC.Daniel Sanders2016-03-242-51/+58
| | | | | | | | | | | | | | | | | | | Summary: In particular, make the cnMIPS predicates much more obvious and prefer def ... : ... { let Foo = bar; } over: let Foo = bar in def ... : ...; Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D18354 llvm-svn: 264258
* Fix sequence point warning. NFC.Vasileios Kalintiris2016-03-241-1/+1
| | | | llvm-svn: 264255
* [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, ↵Zlatko Buljan2016-03-249-42/+89
| | | | | | | | DDIVU and DMODU instructions Differential Revision: http://reviews.llvm.org/D17137 llvm-svn: 264248
* [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructionsHrvoje Varga2016-03-249-11/+192
| | | | | | Differential Revision: http://reviews.llvm.org/D17328 llvm-svn: 264246
* [mips][microMIPS] Fix for "Cannot copy registers" assertionHrvoje Varga2016-03-243-9/+17
| | | | | | Differential Revision: http://reviews.llvm.org/D17068 llvm-svn: 264245
* [LAA] Formatting fix in previous changeAdam Nemet2016-03-241-2/+1
| | | | llvm-svn: 264244
* [LAA] Support memchecks involving loop-invariant addressesAdam Nemet2016-03-241-17/+31
| | | | | | | | | | | | | | | | | | | | We used to only allow SCEVAddRecExpr for pointer expressions in order to be able to compute the bounds. However this is also trivially possible for loop-invariant addresses (scUnknown) since then the bounds are the address itself. Interestingly, we used allow this for the special case when the loop-invariant address happens to also be an SCEVAddRecExpr (in an outer loop). There are a couple more loops that are vectorized in SPEC after this. My guess is that the main reason we don't see more because for example a loop-invariant load is vectorized into a splat vector with several vector-inserts. This is likely to make the vectorization unprofitable. I.e. we don't notice that a later LICM will move all of this out of the loop so the cost estimate should really be 0. llvm-svn: 264243
* [libFuzzer] don't report memory leaks if we are dying due to a timeout (just ↵Kostya Serebryany2016-03-245-5/+25
| | | | | | use _Exit instead of exit in the timeout callback) llvm-svn: 264237
* [libFuzzer] use fdopen+vfprintf instead of fsnprintf+writeKostya Serebryany2016-03-241-11/+10
| | | | llvm-svn: 264230
* [PS4] Guarantee an instruction after a 'noreturn' call.Paul Robinson2016-03-241-1/+3
| | | | | | | | | | We need the "return address" of a noreturn call to be within the bounds of the calling function; TrapUnreachable turns 'unreachable' into a 'ud2' instruction, which has that desired effect. Differential Revision: http://reviews.llvm.org/D18414 llvm-svn: 264224
* Fix lazy linking of comdat members.Rafael Espindola2016-03-241-13/+15
| | | | | | | | | | | If not for lazy linking of linkonce GVs, comdats are just a preprocessing before symbol resolution. Lazy linking complicates it since when we pick a visible member of comdat, we have to make sure the rest of it passes symbol resolution too. llvm-svn: 264223
* [Support] Make all Errors convertible to std::error_code.Lang Hames2016-03-233-3/+46
| | | | | | | | | | | | This is a temporary crutch to enable code that currently uses std::error_code to be incrementally moved over to Error. Requiring all Error instances be convertible enables clients to call errorToErrorCode on any error (not just ECErrors created by conversion *from* an error_code). This patch also moves code for Error from ErrorHandling.cpp into a new Error.cpp file. llvm-svn: 264221
* APFloat: Fix signalling nans for scalbnMatt Arsenault2016-03-231-0/+2
| | | | llvm-svn: 264219
* AMDGPU: Remove atomic inc/dec patternsMatt Arsenault2016-03-231-23/+0
| | | | | | | There is no benefit to these since materializing the constant 1 requires the same number of instructions as materializing uint_max llvm-svn: 264215
* AMDGPU: Promote alloca should skip volatilesMatt Arsenault2016-03-231-0/+13
| | | | llvm-svn: 264214
* [sancov] code readability improvement.Mike Aizatsky2016-03-231-11/+26
| | | | | | | | Summary: Reply to http://reviews.llvm.org/D18341 Differential Revision: http://reviews.llvm.org/D18406 llvm-svn: 264213
* AMDGPU: Insert moves of frame index to value operandsMatt Arsenault2016-03-231-0/+56
| | | | | | | | | | | | | | | | | | | | | | | Strengthen tests of storing frame indices. Right now this just creates irrelevant scheduling changes. We don't want to have multiple frame index operands on an instruction. There seem to be various assumptions that at least the same frame index will not appear twice in the LocalStackSlotAllocation pass. There's no reason to have this happen, and it just makes it easy to introduce bugs where the immediate offset is appplied to the storing instruction when it should really be applied to the value being stored as a separate add. This might not be sufficient. It might still be problematic to have an add fi, fi situation, but that's even less unlikely to happen in real code. llvm-svn: 264200
* Allow X86::COND_NE_OR_P and X86::COND_NP_OR_E to be reversed.Cong Hou2016-03-233-77/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, AnalyzeBranch() fails non-equality comparison between floating points on X86 (see https://llvm.org/bugs/show_bug.cgi?id=23875). This is because this function can modify the branch by reversing the conditional jump and removing unconditional jump if there is a proper fall-through. However, in the case of non-equality comparison between floating points, this can turn the branch "unanalyzable". Consider the following case: jne.BB1 jp.BB1 jmp.BB2 .BB1: ... .BB2: ... AnalyzeBranch() will reverse "jp .BB1" to "jnp .BB2" and then "jmp .BB2" will be removed: jne.BB1 jnp.BB2 .BB1: ... .BB2: ... However, AnalyzeBranch() cannot analyze this branch anymore as there are two conditional jumps with different targets. This may disable some optimizations like block-placement: in this case the fall-through behavior is enforced even if the fall-through block is very cold, which is suboptimal. Actually this optimization is also done in block-placement pass, which means we can remove this optimization from AnalyzeBranch(). However, currently X86::COND_NE_OR_P and X86::COND_NP_OR_E are not reversible: there is no defined negation conditions for them. In order to reverse them, this patch defines two new CondCode X86::COND_E_AND_NP and X86::COND_P_AND_NE. It also defines how to synthesize instructions for them. Here only the second conditional jump is reversed. This is valid as we only need them to do this "unconditional jump removal" optimization. Differential Revision: http://reviews.llvm.org/D11393 llvm-svn: 264199
* More more change need as part of r264187 where ErrorOr<> was addedKevin Enderby2016-03-231-1/+5
| | | | | | to getSymbolType(). llvm-svn: 264194
* Fix logic for which symbols to keep with comdats.Rafael Espindola2016-03-231-4/+4
| | | | | | | | | | | | If a comdat is dropped, all symbols in it are dropped. If a comdat is kept, the symbols survive to pass regular symbol resolution. With this patch we do that for all global symbols. The added test is a copy of test/tools/gold/X86/comdat.ll that we now pass. llvm-svn: 264192
* Fix a crash in running llvm-objdump -t with an invalid Mach-O file alreadyKevin Enderby2016-03-235-7/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | in the test suite. While this is not really an interesting tool and option to run on a Mach-O file to show the symbol table in a generic libObject format it shouldn’t crash. The reason for the crash was in MachOObjectFile::getSymbolType() when it was calling MachOObjectFile::getSymbolSection() without checking its return value for the error case. What makes this fix require a fair bit of diffs is that the method getSymbolType() is in the class ObjectFile defined without an ErrorOr<> so I needed to add that all the sub classes.  And all of the uses needed to be updated and the return value needed to be checked for the error case. The MachOObjectFile version of getSymbolType() “can” get an error in trying to come up with the libObject’s internal SymbolRef::Type when the Mach-O symbol symbol type is an N_SECT type because the code is trying to select from the SymbolRef::ST_Data or SymbolRef::ST_Function values for the SymbolRef::Type. And it needs the Mach-O section to use isData() and isBSS to determine if it will return SymbolRef::ST_Data. One other possible fix I considered is to simply return SymbolRef::ST_Other when MachOObjectFile::getSymbolSection() returned an error. But since in the past when I did such changes that “ate an error in the libObject code” I was asked instead to push the error out of the libObject code I chose not to implement the fix this way. As currently written both the COFF and ELF versions of getSymbolType() can’t get an error. But if isReservedSectionNumber() wanted to check for the two known negative values rather than allowing all negative values or the code wanted to add the same check as in getSymbolAddress() to use getSection() and check for the error then these versions of getSymbolType() could return errors. At the end of the day the error printed now is the generic “Invalid data was encountered while parsing the file” for object_error::parse_failed. In the future when we thread Lang’s new TypedError for recoverable error handling though libObject this will improve. And where the added // Diagnostic(… comment is, it would be changed to produce and error message like “bad section index (42) for symbol at index 8” for this case. llvm-svn: 264187
* [x86] make peekThroughBitcasts() a helper functionSanjay Patel2016-03-231-60/+31
| | | | | | | | | | This should be hoisted further up so it can be used in DAGCombiner and other backends, but I'm limiting the scope in the interest of patch minimalism. It's not quite NFC because some of the replaced code was using an 'if' check rather than a 'while' loop, so those cases would only look through a single bitcast. llvm-svn: 264186
* [AArch64] Replace return 0 with return false. NFC.Chad Rosier2016-03-231-3/+3
| | | | llvm-svn: 264185
* Codegen: [PPC] Word Rotates are Zero Extending.Kyle Butt2016-03-231-1/+8
| | | | | | | Add Word rotates to the list of instructions that are zero extending. This allows them to be used in dot form to compare with zero. llvm-svn: 264183
* Fix bugs in the MemorySSA walker.George Burgess IV2016-03-231-17/+35
| | | | | | | | | | | | | | | | | | There are a few bugs in the walker that this patch addresses. Primarily: - Caching can break when we have multiple BBs without phis - We weren't optimizing some phis properly - Because of how the DFS iterator works, there were times where we wouldn't cache any results of our DFS I left the test cases with FIXMEs in, because I'm not sure how much effort it will take to get those to work (read: We'll probably ultimately have to end up redoing the walker, or we'll have to come up with some creative caching tricks), and more test coverage = better. Differential Revision: http://reviews.llvm.org/D18065 llvm-svn: 264180
OpenPOWER on IntegriCloud