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* [LV] Fix insertion point for shuffle vectors in first order recurrenceAnna Thomas2017-05-091-2/+5
| | | | | | | | | | | | | | | | | | Summary: In first order recurrence vectorization, when the previous value is a phi node, we need to set the insertion point to the first non-phi node. We can have the previous value being a phi node, due to the generation of new IVs as part of trunc optimization [1]. [1] https://reviews.llvm.org/rL294967 Reviewers: mssimpso, mkuper Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D32969 llvm-svn: 302532
* Removing a file that is not necessary (and was causing link diagnostics with ↵Aaron Ballman2017-05-092-11/+0
| | | | | | MSVC 2015); NFC. llvm-svn: 302531
* Add extra operand to CALLSEQ_START to keep frame part set up previouslySerge Pavlov2017-05-0951-140/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using arguments with attribute inalloca creates problems for verification of machine representation. This attribute instructs the backend that the argument is prepared in stack prior to CALLSEQ_START..CALLSEQ_END sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size stored in CALLSEQ_START in this case does not count the size of this argument. However CALLSEQ_END still keeps total frame size, as caller can be responsible for cleanup of entire frame. So CALLSEQ_START and CALLSEQ_END keep different frame size and the difference is treated by MachineVerifier as stack error. Currently there is no way to distinguish this case from actual errors. This patch adds additional argument to CALLSEQ_START and its target-specific counterparts to keep size of stack that is set up prior to the call frame sequence. This argument allows MachineVerifier to calculate actual frame size associated with frame setup instruction and correctly process the case of inalloca arguments. The changes made by the patch are: - Frame setup instructions get the second mandatory argument. It affects all targets that use frame pseudo instructions and touched many files although the changes are uniform. - Access to frame properties are implemented using special instructions rather than calls getOperand(N).getImm(). For X86 and ARM such replacement was made previously. - Changes that reflect appearance of additional argument of frame setup instruction. These involve proper instruction initialization and methods that access instruction arguments. - MachineVerifier retrieves frame size using method, which reports sum of frame parts initialized inside frame instruction pair and outside it. The patch implements approach proposed by Quentin Colombet in https://bugs.llvm.org/show_bug.cgi?id=27481#c1. It fixes 9 tests failed with machine verifier enabled and listed in PR27481. Differential Revision: https://reviews.llvm.org/D32394 llvm-svn: 302527
* Revert "[MIPS] Add support to match more patterns for DINS instruction"Simon Dardis2017-05-091-59/+25
| | | | | | This reverts commit rL302512. This broke the mips buildbots. llvm-svn: 302526
* [X86][SSE42] Lower v2i64/v4i64 ASHR(X, 63) as PCMPGTQ(0, X)Simon Pilgrim2017-05-091-0/+8
| | | | | | | | | | Similar to what we do for vXi8 ASHR(X, 7), use SSE42's PCMPGTQ to splat the sign instead of using the PSRAD+PSHUFD. Avoiding bitcasts this improves combines that utilize computeNumSignBits, permits memory folding and reduces pipe pressure. Although it does require a second register, given that this is a (cheap) zero register the impact is minimal. Differential Revision: https://reviews.llvm.org/D32973 llvm-svn: 302525
* Revert "[Dwarf] Disable reference verification for now (PR32972)"Diana Picus2017-05-091-2/+1
| | | | | | This reverts commit r302520 because it break the unit tests. llvm-svn: 302524
* [Dwarf] Disable reference verification for now (PR32972)Renato Golin2017-05-091-1/+2
| | | | | | | | | | | | | | | There is no other explanation about why this only started happening now, even though it crashes on old code (supposedly reachable from here). The only common factor between the failing bots is that they use GCC (4.9 and 5.3) to compile Clang, while the others use Clang 3.8, but the failure is while building the tests, as an assertion, on Clang. Commenting it out for now in hope the bots will go back green, but we should keep looking for the real cause, and update bugzilla. llvm-svn: 302520
* Introduce experimental generic intrinsics for horizontal vector reductions.Amara Emerson2017-05-0912-66/+480
| | | | | | | | | | | | | | - This change allows targets to opt-in to using them instead of the log2 shufflevector algorithm. - The SLP and Loop vectorizers have the common code to do shuffle reductions factored out into LoopUtils, and now have a unified interface for generating reductions regardless of the preference of the target. LoopUtils now uses TTI to determine what kind of reductions the target wants to handle. - For CodeGen, basic legalization support is added. Differential Revision: https://reviews.llvm.org/D30086 llvm-svn: 302514
* [X86] Clang option -fuse-init-array has no effect when generating for MCU targetNikolai Bozhenov2017-05-091-1/+1
| | | | | | | | | | | | | Reviewers: Eugene.Zelenko, dschuff, craig.topper Reviewed By: craig.topper Subscribers: ahatanak, aaboud, DavidKreitzer, llvm-commits, cfe-commits Differential Revision: https://reviews.llvm.org/D32543 Patch by AndreiGrischenko <andrei.l.grischenko@intel.com> llvm-svn: 302513
* [MIPS] Add support to match more patterns for DINS instructionStrahinja Petrovic2017-05-091-25/+59
| | | | | | | | | This patch adds support for recognizing patterns to match DINS instruction. Differential Revision: https://reviews.llvm.org/D31465 llvm-svn: 302512
* [ARM GlobalISel] Remove hand-written G_FADD selectionDiana Picus2017-05-091-26/+0
| | | | | | | Remove the code selecting G_FADD - now that TableGen can handle more opcodes, it's not needed anymore. llvm-svn: 302511
* [ConstantRange] Rewrite shl to avoid repeated calls to getUnsignedMax and ↵Craig Topper2017-05-091-7/+11
| | | | | | avoid creating the min APInt until we're sure we need it. Use inplace shift operations. llvm-svn: 302510
* [ConstantRange] Combine the two adds max+1 in lshr into a single addition.Craig Topper2017-05-091-4/+4
| | | | llvm-svn: 302509
* [ConstantRange] Use APInt::isNullValue in place of comparing with 0. The ↵Craig Topper2017-05-091-4/+4
| | | | | | compiler should be able to generate slightly better code for the former. NFC llvm-svn: 302508
* Revert "Don't add DBG_VALUE instructions for static allocas in dbg.declare"Reid Kleckner2017-05-091-0/+14
| | | | | | | | | | This reverts commit r302461. It appears to be causing failures compiling gtest with debug info on the Linux sanitizer bot. I was unable to reproduce the failure locally, however. llvm-svn: 302504
* Fix code section prefix for proper layoutTeresa Johnson2017-05-091-1/+1
| | | | | | | | | | | | | | | | | | Summary: r284533 added hot and cold section prefixes based on profile information, to enable grouping of hot/cold functions at link time. However, it used "cold" as the prefix for cold sections, but gold only recognizes "unlikely" (which is used by gcc for cold sections). Therefore, cold sections were not properly being grouped. Switch to using "unlikely" Reviewers: danielcdh, davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32983 llvm-svn: 302502
* [libFuzzer] update docs on -print_coverage/-dump_coverageKostya Serebryany2017-05-091-4/+4
| | | | llvm-svn: 302498
* [libFuzzer] make sure the input data is not overwritten in the fuzz target ↵Kostya Serebryany2017-05-096-1/+39
| | | | | | (if it is -- report an error) llvm-svn: 302494
* Revert "Use the frame index side table for byval and inalloca arguments"Reid Kleckner2017-05-094-68/+41
| | | | | | This reverts r302483 and it's follow up fix. llvm-svn: 302493
* [APInt] Use default constructor instead of explicitly creating a 1-bit APInt ↵Craig Topper2017-05-081-2/+2
| | | | | | | | in udiv and urem. NFC The default constructor does the same thing. llvm-svn: 302487
* [APInt] Remove 'else' after 'return' in udiv and urem. NFCCraig Topper2017-05-081-9/+7
| | | | llvm-svn: 302486
* Ignore !associated metadata with null argument.Evgeniy Stepanov2017-05-081-1/+5
| | | | | | | Fixes PR32577 (comment 10). Such metadata may legitimately appear in LTO. llvm-svn: 302485
* Use the frame index side table for byval and inalloca argumentsReid Kleckner2017-05-084-41/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: For inalloca functions, this is a very common code pattern: %argpack = type <{ i32, i32, i32 }> define void @f(%argpack* inalloca %args) { entry: %a = getelementptr inbounds %argpack, %argpack* %args, i32 0, i32 0 %b = getelementptr inbounds %argpack, %argpack* %args, i32 0, i32 1 %c = getelementptr inbounds %argpack, %argpack* %args, i32 0, i32 2 tail call void @llvm.dbg.declare(metadata i32* %a, ... "a") tail call void @llvm.dbg.declare(metadata i32* %c, ... "b") tail call void @llvm.dbg.declare(metadata i32* %b, ... "c") Even though these GEPs can be simplified to a constant offset from EBP or RSP, we don't do that at -O0, and each GEP is computed into a register. Registers used to compute argument addresses are typically spilled and clobbered very quickly after the initial computation, so live debug variable tracking loses information very quickly if we use DBG_VALUE instructions. This change moves processing of dbg.declare between argument lowering and basic block isel, so that we can ask if an argument has a frame index or not. If the argument lives in a register as is the case for byval arguments on some targets, then we don't put it in the side table and during ISel we emit DBG_VALUE instructions. Reviewers: aprantl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32980 llvm-svn: 302483
* [InstNamer] Use range-forSanjoy Das2017-05-081-4/+3
| | | | llvm-svn: 302481
* [InstNamer] Don't check type of arguments (they're never void)Sanjoy Das2017-05-081-1/+1
| | | | llvm-svn: 302480
* Delete trailing whitespaceSanjoy Das2017-05-081-3/+3
| | | | llvm-svn: 302479
* Add const to "DWARFDie &Die" in a few functions as they can't change the ↵Greg Clayton2017-05-081-2/+2
| | | | | | DWARFDie. llvm-svn: 302471
* Fix typoEugene Zemtsov2017-05-081-1/+1
| | | | llvm-svn: 302470
* Make it illegal for two Functions to point to the same DISubprogramAdrian Prantl2017-05-084-46/+156
| | | | | | | | | | | | | | | | As recently discussed on llvm-dev [1], this patch makes it illegal for two Functions to point to the same DISubprogram and updates FunctionCloner to also clone the debug info of a function to conform to the new requirement. To simplify the implementation it also factors out the creation of inlineAt locations from the Inliner into a general-purpose utility in DILocation. [1] http://lists.llvm.org/pipermail/llvm-dev/2017-May/112661.html <rdar://problem/31926379> Differential Revision: https://reviews.llvm.org/D32975 llvm-svn: 302469
* Fix typo "veify" to "verify".Greg Clayton2017-05-081-1/+1
| | | | llvm-svn: 302466
* [InstCombine] add folds for not-of-shift-rightSanjay Patel2017-05-081-15/+32
| | | | | | | | | | | | | | | This is another step towards getting rid of dyn_castNotVal, so we can recommit: https://reviews.llvm.org/rL300977 As the tests show, we were missing the lshr case for constants and both ashr/lshr vector splat folds. The ashr case with constant was being performed inefficiently in 2 steps. It's also possible there was a latent bug in that case because we can't do that fold if the constant is positive: http://rise4fun.com/Alive/Bge llvm-svn: 302465
* [PartialInlining] Capture by reference rather than by value.Davide Italiano2017-05-081-3/+3
| | | | llvm-svn: 302464
* ARM: use divmod libcalls on embedded MachO platforms too.Tim Northover2017-05-081-3/+3
| | | | | | | The separated libcalls are implemented in terms of __divmodsi4 and __udivmodsi4 anyway, so we should always use them if possible. llvm-svn: 302462
* Don't add DBG_VALUE instructions for static allocas in dbg.declareReid Kleckner2017-05-081-14/+0
| | | | | | | | | | | | | | | | | | | | | | | Summary: An llvm.dbg.declare of a static alloca is always added to the MachineFunction dbg variable map, so these values are entirely redundant. They survive all the way through codegen to be ignored by DWARF emission. Effectively revert r113967 Two bugpoint-reduced test cases from 2012 broke as a result of this change. Despite my best efforts, I haven't been able to rewrite the test case using dbg.value. I'm not too concerned about the lost coverage because these were reduced from the test-suite, which we still run. Reviewers: aprantl, dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32920 llvm-svn: 302461
* [CodeView] Add support for random access type visitors.Zachary Turner2017-05-083-31/+136
| | | | | | | | | | | | | | | | | | | | | | | Previously type visitation was done strictly sequentially, and TypeIndexes were computed by incrementing the TypeIndex of the last visited record. This works fine for situations like dumping, but not when you want to visit types in random order. For example, in a debug session someone might lookup a symbol by name, find that it has TypeIndex 10,000 and then want to go straight to TypeIndex 10,000. In order to make this work, the visitation framework needs a mode where it can plumb TypeIndices through the callback pipeline. This patch adds such a mode. In doing so, it is necessary to provide an alternative implementation of TypeDatabase that supports random access, so that is done as well. Nothing actually uses these random access capabilities yet, but this will be done in subsequent patches. Differential Revision: https://reviews.llvm.org/D32928 llvm-svn: 302454
* [AArch64][RegisterBankInfo] Change the default mapping of fp loads.Quentin Colombet2017-05-081-0/+14
| | | | | | | | | | | This fixes PR32550, in a way that does not imply running the greedy mode at O0. The fix consists in checking if a load is used by any floating point instruction and if yes, we return a default mapping with FPR instead of GPR. llvm-svn: 302453
* [AArch64][RegisterBankInfo] Fix mapping cost for GPR.Quentin Colombet2017-05-081-1/+1
| | | | | | | | | | | | | | | | In r292478, we changed the order of the enum that is referenced by PMI_FirstXXX. This had the side effect of changing the cost of the mapping of all the loads, instead of just the FPRs ones. Reinstate the higher cost for all but GPR loads. Note: This did not have any external visible effects: - For Fast mode, the cost would have been higher, but we don't care because we don't try to use alternative mappings. - For Greedy mode, the higher cost of the GPR loads, would have triggered the use of the supposedly alternative mapping, that would be in fact the same GPR mapping but with a lower cost. llvm-svn: 302452
* [ARM] Use a Changed flag to avoid making a pass's return value dependent on ↵Craig Topper2017-05-081-1/+3
| | | | | | | | | | a compare with a Statistic object. Statistic compile to always be 0 in release build so this compare would always return false. And in the debug builds Statistic are global variables and remember their values across pass runs. So this compare returns true anytime the pass runs after the first time it modifies something. This was found after reviewing all usages of comparison operators on a Statistic object. We had some internal code that did a compare with a statistic that caused a mismatch in output between debug and release builds. So we did an audit out of paranoia. llvm-svn: 302450
* [SCEV] Don't use std::move on both inputs to APInt::operator+ or operator-. ↵Craig Topper2017-05-081-4/+4
| | | | | | It might be confusing to the reader. NFC llvm-svn: 302448
* ConstantFold: Handle gep nonnull, undef as wellDaniel Berlin2017-05-081-3/+4
| | | | llvm-svn: 302447
* ConstantFold: Fold getelementptr (i32, i32* null, i64 undef) to null.Daniel Berlin2017-05-081-1/+2
| | | | | | | | Transforms/IndVarSimplify/2011-10-27-lftrnull will fail if this regresses. Transforms/GVN/PRE/2011-06-01-NonLocalMemdepMiscompile.ll has been changed to still test what it was trying to test. llvm-svn: 302446
* [ValueTracking] Use KnownOnes to provide a better bound on known zeros for ↵Craig Topper2017-05-081-3/+16
| | | | | | | | | | ctlz/cttz intrinics This patch uses KnownOnes of the input of ctlz/cttz to bound the value that can be returned from these intrinsics. This makes these intrinsics more similar to the handling for ctpop which already uses known bits to produce a similar bound. Differential Revision: https://reviews.llvm.org/D32521 llvm-svn: 302444
* [InstSimplify] fix typo; NFCSanjay Patel2017-05-081-1/+1
| | | | llvm-svn: 302439
* [InstCombine] use local variable to reduce code duplication; NFCISanjay Patel2017-05-081-14/+11
| | | | llvm-svn: 302438
* [ValueTracking] Introduce a version of computeKnownBits that returns a ↵Craig Topper2017-05-081-67/+52
| | | | | | | | | | | | | | | | KnownBits struct. Begin using it to replace internal usages of ComputeSignBit This introduces a new interface for computeKnownBits that returns the KnownBits object instead of requiring it to be pre-constructed and passed in by reference. This is a much more convenient interface as it doesn't require the caller to figure out the BitWidth to pre-construct the object. It's so convenient that I believe we can use this interface to remove the special ComputeSignBit flavor of computeKnownBits. As a step towards that idea, this patch replaces all of the internal usages of ComputeSignBit with this new interface. As you can see from the patch there were a couple places where we called ComputeSignBit which really called computeKnownBits, and then called computeKnownBits again directly. I've reduced those places to only making one call to computeKnownBits. I bet there are probably external users that do it too. A future patch will update the external users and remove the ComputeSignBit interface. I'll also working on moving more locations to the KnownBits returning interface for computeKnownBits. Differential Revision: https://reviews.llvm.org/D32848 llvm-svn: 302437
* [InstCombine/InstSimplify] add comments about code duplication; NFCSanjay Patel2017-05-082-0/+6
| | | | llvm-svn: 302436
* InstructionSimplify: Refactor foldIdentityShuffles. NFC.Zvi Rackover2017-05-081-13/+7
| | | | | | | | | | | | | | | | | | | Summary: Minor refactoring of foldIdentityShuffles() which allows the removal of a ConstantDataVector::get() in SimplifyShuffleVectorInstruction. Reviewers: spatel Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32955 Conflicts: lib/Analysis/InstructionSimplify.cpp llvm-svn: 302433
* [X86][SSE] Improve combineLogicBlendIntoPBLENDV to use general masks.Simon Pilgrim2017-05-081-23/+13
| | | | | | | | | | | | | | | Currently combineLogicBlendIntoPBLENDV can only match ASHR to detect sign splatting of a bit mask, this patch generalises this to use computeNumSignBits instead. This is a first step in several things we can do to improve PBLENDV support: * Better matching of X86ISD::ANDNP patterns. * Handle floating point cases. * Better vector and bitcast support in computeNumSignBits. * Recognise that PBLENDV only uses the sign bit of the mask, we should be able strip away sign splats (ASHR, PCMPGT isNeg tests etc.). Differential Revision: https://reviews.llvm.org/D32953 llvm-svn: 302424
* IR: Add a shufflevector mask commutation helper function. NFC.Zvi Rackover2017-05-081-7/+1
| | | | | | | | | | | | | | | | Summary: Following up on Sanjay's suggetion in D32955, move this functionality into ShuffleVectornstruction. Reviewers: spatel, RKSimon Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32956 llvm-svn: 302420
* [ARM][NEON] Add support for ISD::ABS lowering Simon Pilgrim2017-05-082-26/+5
| | | | | | | | | | Update NEON int_arm_neon_vabs intrinsic to use the ISD::ABS opcode directly Added constant folding tests. Differential Revision: https://reviews.llvm.org/D32938 llvm-svn: 302417
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