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* [X86][SSE] Relax 0/-1 vector element insertion to work for any vector with ↵Simon Pilgrim2017-06-201-1/+2
| | | | | | | | >=16bit elements Shuffle lowering/combining now does a good job for 256/512-bit vectors - we don't need to prevent this llvm-svn: 305801
* DAG: correctly legalize UMULO.Tim Northover2017-06-201-11/+18
| | | | | | | | | We were incorrectly sign extending into the high word (as you would for SMULO) when legalizing UMULO in terms of a wider full multiplication. Patch by James Duley. llvm-svn: 305800
* [InstCombine] fix code/test comments for r305792; NFCSanjay Patel2017-06-201-1/+1
| | | | | | | These diffs were in the last version of the patch in D33342, but I accidentally committed the previous rev. llvm-svn: 305793
* [InstCombine] try to canonicalize xor-of-icmps to and-of-icmpsSanjay Patel2017-06-201-0/+24
| | | | | | | | | | | | | | | | We have a large portfolio of folds for and-of-icmps and or-of-icmps in InstSimplify and InstCombine, but hardly anything for xor-of-icmps. Rather than trying to rethink and translate all of those folds, we can use the truth table definition of xor: X ^ Y --> (X | Y) & !(X & Y) ...to see if we can convert the xor to and/or and then use the existing folds. http://rise4fun.com/Alive/J9v Differential Revision: https://reviews.llvm.org/D33342 llvm-svn: 305792
* [globalisel][tablegen] Add support for COPY_TO_REGCLASS.Daniel Sanders2017-06-202-10/+30
| | | | | | | | | | | | | | | | | | | | | | Summary: As part of this * Emitted instructions now have named MachineInstr variables associated with them. This isn't particularly important yet but it's a small step towards multiple-insn emission. * constrainSelectedInstRegOperands() is no longer hardcoded. It's now added as the ConstrainOperandsToDefinitionAction() action. COPY_TO_REGCLASS uses an alternate constraint mechanism ConstrainOperandToRegClassAction() which supports arbitrary constraints such as that defined by COPY_TO_REGCLASS. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D33590 llvm-svn: 305791
* [X86][SSE] Dropped old INSERT_VECTOR_ELT lowering TODOSimon Pilgrim2017-06-201-2/+0
| | | | | | Target shuffle combining now supports the matching of INSERT_VECTOR_ELT/PINSRW/PINSRB for merging multiple insertions into shuffles/bitmasks. llvm-svn: 305788
* [GlobalISel][X86] fix compilation error ( -Werror=unused-function )Igor Breger2017-06-201-2/+2
| | | | llvm-svn: 305786
* [SelectionDAG] Fix an use-after-free issue introduced in r305775.Haojian Wu2017-06-201-2/+2
| | | | | | vector.back() will be invalidated when memory reallocation happens. llvm-svn: 305785
* [GlobalISel][X86] Get correct RegClass for given RegBank.Igor Breger2017-06-201-17/+26
| | | | | | | | | | | | | | | | | | | Summary: In some cases RegClass depends on target feature. Hight (16-31) vector registers exist only if AVX512f available. Split from https://reviews.llvm.org/D33665 Reviewers: qcolombet, t.p.northover, zvi, guyblank Reviewed By: t.p.northover, guyblank Subscribers: guyblank, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D33952 Conflicts: test/CodeGen/X86/GlobalISel/select-memop-scalar.mir llvm-svn: 305784
* [GlobalISel] combine not symmetric merge/unmerge nodes.Igor Breger2017-06-201-13/+58
| | | | | | | | | | | | | | | | Summary: In some cases legalization ends up with not symmetric merge/unmerge nodes. Transform it to merge/unmerge nodes. Reviewers: t.p.northover, qcolombet, zvi Reviewed By: t.p.northover Subscribers: rovka, kristof.beyls, guyblank, llvm-commits Differential Revision: https://reviews.llvm.org/D33626 llvm-svn: 305783
* [SCEV][NFC] Fix a misleading description of AddOpsInlineThresholdMax Kazantsev2017-06-201-1/+1
| | | | | | | | | The description of this option was copy-pasted from another one and does not correspond to reality. Differential Revision: https://reviews.llvm.org/D34390 llvm-svn: 305782
* WasmObjectWriter.cpp: Tweak a comment line. [-Wdocumentation]NAKAMURA Takumi2017-06-201-1/+1
| | | | llvm-svn: 305777
* [ARM] Support constant pools in data when generating execute-only code.Alexandros Lamprineas2017-06-203-15/+44
| | | | | | | | | | | | | | | | | | Resubmission of r305387, which was reverted at r305390. The Address Sanitizer caught a stack-use-after-scope of a Twine variable. This is now fixed by passing the Twine directly as a function parameter. The ARM backend asserts against constant pool lowering when it generates execute-only code in order to prevent the generation of constant pools in the text section. It appears that target independent optimizations might generate DAG nodes that represent constant pools. By lowering such nodes as global addresses we don't violate the semantics of execute-only code and also it is guaranteed that execute-only behaves correct with the position-independent addressing modes that support execute-only code. Differential Revision: https://reviews.llvm.org/D33773 llvm-svn: 305776
* [SelectionDAG] Get rid of recursion in CalcNodeSethiUllmanNumberMax Kazantsev2017-06-201-19/+59
| | | | | | | | | | The recursive implementation of CalcNodeSethiUllmanNumber may overflow stack on extremely long pred chains. This patch replaces it with an equivalent iterative implementation. Differential Revision: https://reviews.llvm.org/D33769 llvm-svn: 305775
* Fix unused function build error in lldSam Clegg2017-06-201-0/+2
| | | | | | | | | | | | The lld-x86_64-darwin13 is failing with: error: unused function 'operator<<' Wrap the declation in ifndef NDEBUG, which matches what is done in MipsELFObjectWriter.cpp. Differential Revision: https://reviews.llvm.org/D34384 llvm-svn: 305771
* [WebAssembly] Fix build failures introduced in r305769Sam Clegg2017-06-202-2/+2
| | | | | | | | | | | This fixes two build failures that only occur in certain configurations: - error: unused function 'operator<<' - error: control reaches end of non-void function Differential Revision: https://reviews.llvm.org/D34382 llvm-svn: 305770
* [WebAssembly] Add support for weak symbols in the binary formatSam Clegg2017-06-204-60/+259
| | | | | | | | | | | This also introduces the updated format for the "linking" section which can represent extra symbol information. See: https://github.com/WebAssembly/tool-conventions/pull/10 Differential Revision: https://reviews.llvm.org/D34019 llvm-svn: 305769
* [DAG] Simplify BaseIndexOffset. NFCI.Nirav Dave2017-06-201-59/+57
| | | | | | Remove tail calls and cleanup codeflow. llvm-svn: 305768
* [Coverage] PR33517: Check for failure to load func recordsVedant Kumar2017-06-201-0/+3
| | | | | | | | | | | | With PR33517, it became apparent that symbol table creation can fail when presented with malformed inputs. This patch makes that sort of error detectable, so llvm-cov etc. can fail more gracefully. Specifically, we now check that function records loaded from corrupted coverage mapping data are rejected, e.g when the recorded function name is garbage. Testing: check-{llvm,clang,profile}, some unit test updates. llvm-svn: 305767
* [ProfileData] PR33517: Check for failure of symtab creationVedant Kumar2017-06-205-10/+27
| | | | | | | | | | | | With PR33517, it became apparent that symbol table creation can fail when presented with malformed inputs. This patch makes that sort of error detectable, so llvm-cov etc. can fail more gracefully. Specifically, we now check that function names within the symbol table aren't empty. Testing: check-{llvm,clang,profile}, some unit test updates. llvm-svn: 305765
* AMDGPU: Fix scratch wave offset relative FI expansionMatt Arsenault2017-06-191-9/+20
| | | | | | | | The offset may not be an inline immediate, so this needs to be materialized into a register. The post-RA run of SIShrinkInstructions is able to fold it later if it can. llvm-svn: 305761
* [ExecutionEngine] Fix some Clang-tidy modernize-use-using and Include What ↵Eugene Zelenko2017-06-192-30/+53
| | | | | | You Use warnings; other minor fixes (NFC). llvm-svn: 305760
* [AMDGPU] Add infer address spaces pass before SROAStanislav Mekhanoshin2017-06-191-0/+8
| | | | | | | | | It adds it for the target after inlining but before SROA where we can get most out of it. Differential Revision: https://reviews.llvm.org/D34366 llvm-svn: 305759
* [Target] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-06-194-28/+60
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 305757
* [IR] Fix some Clang-tidy modernize-use-using warnings; other minor fixes (NFC).Eugene Zelenko2017-06-196-125/+232
| | | | llvm-svn: 305755
* Mark LLVMTestingSupport as not installed in LLVMBuild.Zachary Turner2017-06-191-0/+1
| | | | | | This is causing downstream issues with llvm-config. llvm-svn: 305754
* [AArch64][Falkor] Fix MOVZ sched predicate to not assert on non-imm operands ↵Geoff Berry2017-06-191-1/+2
| | | | | | (e.g. blockaddress). llvm-svn: 305752
* [AArch64][Kryo] Add missing write latency for LDAXP, LDXP second destination.Geoff Berry2017-06-191-2/+4
| | | | | | Fixes PR33491 and PR33512. llvm-svn: 305751
* [AArch64][Falkor] Refine load/store increment latencies.Geoff Berry2017-06-191-164/+242
| | | | | | Also fix LDXP & LDAXP write latency to avoid similar assert as PR33491 and PR33512. llvm-svn: 305750
* Fix typosMatt Arsenault2017-06-191-2/+2
| | | | llvm-svn: 305749
* AMDGPU: Cleanup CreateLiveInRegisterMatt Arsenault2017-06-195-34/+45
| | | | llvm-svn: 305748
* [BDCE] Add comments. NFCXin Tong2017-06-191-0/+2
| | | | llvm-svn: 305739
* [PATCH] [PGO] Fixed cast operation in ↵Ana Pazos2017-06-191-1/+1
| | | | | | | | | | | | | | emIntrinsicVisitor::instrumentOneMemIntrinsic. Reviewers: xur, efriedma, davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34293 llvm-svn: 305737
* Revert r305382, it caused PR33513.Nico Weber2017-06-191-6/+6
| | | | llvm-svn: 305735
* [CGP, PowerPC] try to constant fold before creating loads for memcmp expansionSanjay Patel2017-06-191-3/+13
| | | | | | | | | | | | | | | This is the last step needed to avoid regressions for x86 before we flip the switch to allow expansion of the smallest set of memcpy() via CGP. The DAG version checks for constant strings, so we need to do that here too. FWIW, the 2 constant test is not handled by LibCallSimplifier::optimizeMemCmp() because that code is limited to 8-bit constant arrays. LibCallSimplifier will also fail to optimize some 1 constant tests because its alignment requirements are too strict (shouldn't require alignment for a constant operand). Differential Revision: https://reviews.llvm.org/D34071 llvm-svn: 305734
* Remove convenient but probably not worthwhile macro for lambda workaroundDavid Blaikie2017-06-191-15/+18
| | | | | | Cleanup from r305405 llvm-svn: 305731
* Have writeCOFFWriter return Expected<unique_ptr>.Eric Beckmann2017-06-191-16/+14
| | | | | | | | | | | | Summary: Have writeCOFFWriter return Expected<unique_ptr> instead of requiring being passed an uninitialized unique_ptr. Reviewers: zturner, ruiu Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D34307 llvm-svn: 305730
* Improve profile-guided heuristics to use estimated trip count.Taewook Oh2017-06-191-27/+20
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Existing heuristic uses the ratio between the function entry frequency and the loop invocation frequency to find cold loops. However, even if the loop executes frequently, if it has a small trip count per each invocation, vectorization is not beneficial. On the other hand, even if the loop invocation frequency is much smaller than the function invocation frequency, if the trip count is high it is still beneficial to vectorize the loop. This patch uses estimated trip count computed from the profile metadata as a primary metric to determine coldness of the loop. If the estimated trip count cannot be computed, it falls back to the original heuristics. Reviewers: Ayal, mssimpso, mkuper, danielcdh, wmi, tejohnson Reviewed By: tejohnson Subscribers: tejohnson, mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D32451 llvm-svn: 305729
* [InstCombine] Make sure AddReachableCodeToWorklist sets MadeIRChangeBjorn Pettersson2017-06-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Some optimizations in AddReachableCodeToWorklist did not update the MadeIRChange state. This could happen both when removing trivially dead instructions (DCE) and at constant folds. It is essential that changes to the IR is reported correctly, since for example InstCombinePass::run() will indicate that all analyses are preserved otherwise. And the CGPassManager determines if the CallGraph is up-to-date based on status from InstructionCombiningPass::runOnFunction(). The new test case early_dce_clobbers_callgraph.ll is a reproducer for some asserts that started to trigger after changes in the inliner in r305245. With this patch the test case passes again. Reviewers: sanjoy, craig.topper, dblaikie Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34346 llvm-svn: 305725
* Revert r304824 "Fix PR23384 (part 3 of 3)"Hans Wennborg2017-06-193-14/+1
| | | | | | | | | | | | | | | | | This seems to be interacting badly with ASan somehow, causing false reports of heap-buffer overflows: PR33514. > Summary: > The patch makes instruction count the highest priority for > LSR solution for X86 (previously registers had highest priority). > > Reviewers: qcolombet > > Differential Revision: http://reviews.llvm.org/D30562 > > From: Evgeny Stupachenko <evstupac@gmail.com> llvm-svn: 305720
* [PDB] Start emitting source file and line informationReid Kleckner2017-06-193-12/+32
| | | | | | | | | | | | | | | | | | | | | | | Summary: This is a first step towards getting line info to show up in VS and windbg. So far, only llvm-pdbutil can parse the PDBs that we produce. cvdump doesn't like something about our file checksum tables. I'll have to dig into that next. This patch adds a new DebugSubsectionRecordBuilder which takes bytes directly from some other producer, such as a linker, and sticks it into the PDB. Line tables only need to be relocated. No data needs to be rewritten. File checksums and string tables, on the other hand, need to be re-done. Reviewers: zturner, ruiu Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D34257 llvm-svn: 305713
* [CodeView] Fix dumping of public symbol record flagsReid Kleckner2017-06-194-3/+22
| | | | | | | I noticed nonsensical type information while dumping PDBs produced by MSVC. llvm-svn: 305708
* [NewGVN] Simplify findConditionEquivalence(). NFCI.Davide Italiano2017-06-191-3/+1
| | | | llvm-svn: 305707
* Remove brackets, NFC.Dinar Temirbulatov2017-06-191-4/+2
| | | | llvm-svn: 305706
* [InstCombine] Cleanup some duplicated one use checksCraig Topper2017-06-191-10/+4
| | | | | | | | | | | | | | | | | | | Summary: These 4 patterns have the same one use check repeated twice for each. Once without a cast and one with. But the cast has no effect on what method is called. For the OR case I believe it is always profitable regardless of the number of uses since we'll never increase the instruction count. For the AND case I believe it is profitable if the pair of xors has one use such that we'll get rid of it completely. Or if the C value is something freely invertible, in which case the not doesn't cost anything. Reviewers: spatel, majnemer Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34308 llvm-svn: 305705
* [Reassociate] Support some reassociation of vector xorsCraig Topper2017-06-191-6/+7
| | | | | | | | | | | | | | | | | Summary: Currently we don't try to do anything with vector xors. This patch adds support for removing duplicate pairs from a chain of vector xors as its pretty easy to support. We still dont' try to combine the xors with and/ors, but I might try that in a future patch. Reviewers: mcrosier, davide, resistor Reviewed By: mcrosier Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34338 llvm-svn: 305704
* [Reassociate] Make one of the helper methods static because it doesn't use ↵Craig Topper2017-06-191-2/+2
| | | | | | any class variables. NFC llvm-svn: 305703
* Allow truncated and extend memory operations in Store Merge. NFCI.Nirav Dave2017-06-191-24/+46
| | | | | | | | | | As all store merges checks are based on the memory operation performed, allow use of truncated stores and extended loads as valid input candidates for merging. Relanding after fixing selection between truncated and normal store. llvm-svn: 305701
* [JumpThreading][LVI] Invalidate LVI information after blocks are mergedAnna Thomas2017-06-191-0/+31
| | | | | | | | | | | | | | | | | | | Summary: After a single predecessor is merged into a basic block, we need to invalidate the LVI information for the new merged block, when LVI is not provably true for all of instructions in the new block. The test cases added show the correct LVI information using the LVI printer pass. Reviewers: reames, dberlin, davide, sanjoy Reviewed by: dberlin, davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34108 llvm-svn: 305699
* [TRE] Improve code motion in TRE, use AA to tell whether a load can be moved ↵Xin Tong2017-06-191-19/+27
| | | | | | | | | | | | | | | | before a call that writes to memory. Summary: use AA to tell whether a load can be moved before a call that writes to memory. Reviewers: dberlin, davide, sanjoy, hfinkel Reviewed By: hfinkel Subscribers: hfinkel, llvm-commits Differential Revision: https://reviews.llvm.org/D34115 llvm-svn: 305698
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