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* XformToShuffleWithZero - Added clearer early outs and general tidy up. NFCISimon Pilgrim2015-03-171-31/+38
| | | | llvm-svn: 232557
* Selection DAG preprocessing on HexagonKrzysztof Parzyszek2015-03-171-2/+52
| | | | | | Simplify: (or (select c x 0) z) -> (select c (or x z) z) (or (select c 0 y) z) -> (select c z (or y z)) llvm-svn: 232553
* DebugInfo: Drop fake DW_TAG_expressionDuncan P. N. Exon Smith2015-03-171-1/+0
| | | | | | | | | | | | | Break MDExpression off of DebugNode (inherit directly from `MDNode`) and drop the fake `DW_TAG_expression` tag in the process. AFAICT, there's no real functionality change here. The tag was originally used by `DIDescriptor::isExpression()` to discriminate between `MDNode`s, but in the new hierarchy we don't need that. Fixes PR22780. llvm-svn: 232550
* Emit the offset directly instead of creating a dummy expression.Rafael Espindola2015-03-171-26/+1
| | | | | | | | We were creating an expression of the form (S+C)-S which is just C. Patch by Frédéric Riss. I just added the testcase. llvm-svn: 232549
* Revert "COFF: Let globals with private linkage reside in their own section"David Majnemer2015-03-173-31/+1
| | | | | | This reverts commit r232539. This was committed accidently. llvm-svn: 232543
* Internalize BitcodeReader. Not used outside of BitcodeReader.cpp.Benjamin Kramer2015-03-172-385/+342
| | | | | | NFC. llvm-svn: 232542
* Revert "Address review comments"David Majnemer2015-03-172-8/+11
| | | | | | This reverts commit r232540. This was committed accidently. llvm-svn: 232541
* Address review commentsDavid Majnemer2015-03-172-11/+8
| | | | llvm-svn: 232540
* COFF: Let globals with private linkage reside in their own sectionDavid Majnemer2015-03-173-1/+31
| | | | | | | | | | | | | | | Summary: COFF COMDATs (for selection kinds other than 'select any') require at least one non-section symbol in the symbol table. Satisfy this by morally enhancing the linkage from private to internal. Reviewers: rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8374 llvm-svn: 232539
* Try to fix a test broken by one of my previous commits.Michael Zolotukhin2015-03-171-0/+3
| | | | llvm-svn: 232536
* Centralize the handling of unique ids for temporary labels.Rafael Espindola2015-03-179-69/+51
| | | | | | | | | | | | | | | | Before this patch code wanting to create temporary labels for a given entity (function, cu, exception range, etc) had to keep its own counter to have stable symbol names. createTempSymbol would still add a suffix to make sure a new symbol was always returned, but it kept a single counter. Because of that, if we were to use just createTempSymbol("cu_begin"), the label could change from cu_begin42 to cu_begin43 because some other code started using temporary labels. Simplify this by just keeping one counter per prefix and removing the various specialized counters. llvm-svn: 232535
* Internalize llvm::AssemblyWriter. It's not used outside of AsmWriter.cpp.Benjamin Kramer2015-03-172-136/+86
| | | | | | | This is an artifact of an implementation detail of DebugIR that has been long refactored away. NFC. llvm-svn: 232532
* TLI: Add addVectorizableFunctionsFromVecLib.Michael Zolotukhin2015-03-171-0/+34
| | | | | | | | Also, add several entries to vectorizable functions table, and corresponding tests. The table isn't complete, it'll be populated later. Review: http://reviews.llvm.org/D8131 llvm-svn: 232531
* LoopVectorize: teach loop vectorizer to vectorize calls.Michael Zolotukhin2015-03-172-35/+164
| | | | | | | The tests would be committed in a commit for http://reviews.llvm.org/D8131 Review: http://reviews.llvm.org/D8095 llvm-svn: 232530
* Add assertion to detect invalid registers in the PowerPC MC instruction ↵Samuel Antao2015-03-171-0/+3
| | | | | | | | lowering. We have observed that noreg was being generated due to a bug in FastIsel and was not being detected during emission. It happens that in the Asm emission there is an assertion that detects this in getRegisterName() from the tbl-generated file PPCGenAsmWriter.inc. However, when emitting an Obj file, invalid registers can be emitted given that no check are made in getBinaryCodeFromInstr() from PPCGenMCCodeEmitter.inc. In order to cover all cases this adds an assertion for reg operands in LowerPPCMachineInstrToMCInst. llvm-svn: 232525
* TTI: Add getCallInstrCost.Michael Zolotukhin2015-03-171-0/+5
| | | | | Review: http://reviews.llvm.org/D8094 llvm-svn: 232524
* TLI: Add interface for querying whether a function is vectorizable.Michael Zolotukhin2015-03-171-0/+70
| | | | | Review: http://reviews.llvm.org/D8093 llvm-svn: 232523
* LoopVectorizer: Add TargetTransformInfo.Michael Zolotukhin2015-03-171-9/+12
| | | | | Review: http://reviews.llvm.org/D8092 llvm-svn: 232522
* [asan] remove redundant ifndefs. NFCKostya Serebryany2015-03-171-9/+5
| | | | llvm-svn: 232521
* Remove LookupSymbol(StringRef) and optimize LookupSymbol(Twine).Yaron Keren2015-03-171-7/+3
| | | | | | | | Same as MakeArgString in r232465, keep only LookupSymbol(Twine) while making sure it handles the StringRef like cases efficiently using twine::toStringRef. llvm-svn: 232517
* [ARM] Fix offset calculation in ARMBaseRegisterInfo::needsFrameBaseRegRichard Barton2015-03-171-1/+0
| | | | | | | | | | | | | The input offset to needsFrameBaseReg is a negative value below the top of the stack frame, but when converting to a positive offset from the bottom of the stack frame this value was negated, causing the final offset to be too large by twice the input offset's magnitude. Fix that by not negating the offset. Patch by John Brawn Differential Revision: http://reviews.llvm.org/D8316 llvm-svn: 232513
* [SwitchLowering] Remove incoming values in the reverse orderMichael Liao2015-03-171-1/+6
| | | | | | | - To prevent invalidating *successive* indices. llvm-svn: 232510
* Fix GCC -Wparentheses warning (& reformat now that the precedence is fixed)David Blaikie2015-03-171-2/+2
| | | | | | | Benign warning (clang deliberately suppresses this case) but does regularly produce bad formatting, so it's nice to fix/reformat. llvm-svn: 232508
* Verifier: Set --verify-debug-info=true by defaultDuncan P. N. Exon Smith2015-03-171-1/+1
| | | | | | | | | | | | | | | | | | | r186634 started verifying debug info, and r194986 disabled it by default because it was too expensive to run the checks on every function (since most of the graph was reachable from each function). r206300 moved the checks to module-level to make it cheaper, but there was already quite a bit of testcase bitrot (and the verifier would only print `<badref>`) so I guess no one had time to turn it back on. This does just that. Upgrade scripts this past autumn and winter probably fixed some of the bitrot, and this weekend I fixed the verifier output (r232275, r232417, r232418) and thusly the remaining failing testcases (r232290, r232415). This is part of PR22777. llvm-svn: 232505
* asan: optimization experimentsDmitry Vyukov2015-03-171-60/+114
| | | | | | | | | | | | | | | | | | | | The experiments can be used to evaluate potential optimizations that remove instrumentation (assess false negatives). Instead of completely removing some instrumentation, you set Exp to a non-zero value (mask of optimization experiments that want to remove instrumentation of this instruction). If Exp is non-zero, this pass will emit special calls into runtime (e.g. __asan_report_exp_load1 instead of __asan_report_load1). These calls make runtime terminate the program in a special way (with a different exit status). Then you run the new compiler on a buggy corpus, collect the special terminations (ideally, you don't see them at all -- no false negatives) and make the decision on the optimization. The exact reaction to experiments in runtime is not implemented in this patch. It will be defined and implemented in a subsequent patch. http://reviews.llvm.org/D8198 llvm-svn: 232502
* Use an underlying enum type of unsigned to silence a -Wmicrosoft warning ↵Reid Kleckner2015-03-171-1/+1
| | | | | | about being unable to put (unsigned)-1 into the default underyling type of int llvm-svn: 232498
* [systemz] Distinguish the 'Q', 'R', 'S', and 'T' inline assembly memory ↵Daniel Sanders2015-03-172-15/+38
| | | | | | | | | | | | | | | | | | | | constraints. Summary: But still handle them the same way since I don't know how they differ on this target. No functional change intended. Reviewers: uweigand Reviewed By: uweigand Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8251 llvm-svn: 232495
* Remove the error prone GetTempSymbol API.Rafael Espindola2015-03-171-12/+0
| | | | llvm-svn: 232487
* Fix R0 use in PowerPC VSX store for FastIsel.Samuel Antao2015-03-171-2/+12
| | | | | | The VSX stores are sometimes generated with a undefined index register, causing %noreg to be used and R0 to be emitted later on. The semantics of the VSX store (e.g. stdsdx) requires R0 to be used as base if we want zero to be used in the computation of the effective address instead of the content of R0. This patch checks if no index register was generated and forces R0 to be used as base address. llvm-svn: 232486
* Convert the last 4 users of GetTempSymbol to createTempSymbol.Rafael Espindola2015-03-171-2/+2
| | | | | | Despite using the same name these are unrelated. llvm-svn: 232485
* Use createTempSymbol to avoid collisions instead of an ad hoc method.Rafael Espindola2015-03-171-10/+2
| | | | llvm-svn: 232483
* Make EmitFunctionHeader a private helper.Rafael Espindola2015-03-174-7/+2
| | | | llvm-svn: 232481
* Re-commit: [hexagon] Distinguish the 'o', 'v', and 'm' inline assembly ↵Daniel Sanders2015-03-172-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | memory constraints. Summary: But still handle them the same way since I don't know how they differ on this target. No functional change intended. Reviewers: kparzysz, adasgupt Reviewed By: kparzysz, adasgupt Subscribers: colinl, llvm-commits Differential Revision: http://reviews.llvm.org/D8204 Like for the PowerPC target, I've had to add 'i' to the constraint mappings in order to pass 2007-12-17-InvokeAsm.ll. It's not clear why 'i' has historically been treated as a memory constraint. llvm-svn: 232480
* Call EmitFunctionHeader just before EmitFunctionBody.Rafael Espindola2015-03-171-3/+1
| | | | | | | This avoids switching to .AMDGPU.config and back and hardcoding the section it switches back to. llvm-svn: 232479
* Convert the easy cases of GetTempSymbol to createTempSymbol.Rafael Espindola2015-03-176-7/+7
| | | | | | | In these cases no code was depending on GetTempSymbol finding an existing symbol. llvm-svn: 232478
* Don't duplicate comment from the .h. NFC.Rafael Espindola2015-03-171-4/+0
| | | | llvm-svn: 232476
* Move the EH symbol to the asm printer and use it for the SJLJ case too.Rafael Espindola2015-03-177-35/+12
| | | | llvm-svn: 232475
* [mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction.Toma Tabacu2015-03-171-0/+2
| | | | | | | | | | | | | | | | Summary: This adds a MipsInstAlias which expands to XORi $reg,$reg,imm. For example, "xor $6, 0x3A" should be expanded to "xori $6, $6, 58". This should work for all MIPS ISAs. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8284 llvm-svn: 232473
* Remove dead code. NFC.Rafael Espindola2015-03-172-28/+0
| | | | llvm-svn: 232472
* Replace a use of GetTempSymbol with createTempSymbol.Rafael Espindola2015-03-175-12/+26
| | | | | | This is cleaner and avoids a crash in a corner case. llvm-svn: 232471
* Fix r232466 by adding 'i' to the mappings for inline assembly memory ↵Daniel Sanders2015-03-171-0/+1
| | | | | | | | | constraints. It's not completely clear why 'i' has historically been treated as a memory constraint. According to the documentation, it represents a constant immediate. llvm-svn: 232470
* [ARM] Add support for ARMV6K subtarget (LLVM)Renato Golin2015-03-179-16/+33
| | | | | | | | | | | | | | | | | | | | | ARMv6K is another layer between ARMV6 and ARMV6T2. This is the LLVM side of the changes. ARMV6 family LLVM implementation. +-------------------------------------+ | ARMV6 | +----------------+--------------------+ | ARMV6M (thumb) | ARMV6K (arm,thumb) | <- From ARMV6K and ARMV6M processors +----------------+--------------------+ have support for hint instructions | ARMV6T2 (arm,thumb,thumb2) | (SEV/WFE/WFI/NOP/YIELD). They can +-------------------------------------+ be either real or default to NOP. | ARMV7 (arm,thumb,thumb2) | The two processors also use +-------------------------------------+ different encoding for them. Patch by Vinicius Tinti. llvm-svn: 232468
* [ppc] Distinguish the 'es', 'o', 'm', 'Q', 'Z', and 'Zy' inline assembly ↵Daniel Sanders2015-03-172-14/+36
| | | | | | | | | | | | | | | | | | | | | | | memory constraints. Summary: But still handle them the same way since I don't know how they differ on this target. Of these, 'es', and 'Q' do not have backend tests but are accepted by clang. No functional change intended. Depends on D8173. Reviewers: hfinkel Reviewed By: hfinkel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8213 llvm-svn: 232466
* Teach Twine to support SmallString.Yaron Keren2015-03-173-23/+15
| | | | | | | | Enable removing .str() member calls for these frequent cases. http://reviews.llvm.org/D6372 llvm-svn: 232465
* [AArch64] Use intermediate step for concat_vectors of illegal truncs.Ahmed Bougacha2015-03-171-0/+31
| | | | | | | | | | | | | | | | | | Optimize concat_vectors of truncated vectors, where the intermediate type is illegal, to avoid said illegality, e.g., (v4i16 (concat_vectors (v2i16 (truncate (v2i64))), (v2i16 (truncate (v2i64))))) -> (v4i16 (truncate (v4i32 (concat_vectors (v2i32 (truncate (v2i64))), (v2i32 (truncate (v2i64))))))) This isn't really target-specific, and, as such, would best go in the DAGCombiner. However, ISD::TRUNCATE legality isn't keyed on both input and result type, so we might generate worse code when we don't know better. On AArch64 we know it's fine for v2i64->v4i16 and v4i32->v8i8. rdar://20022387 llvm-svn: 232459
* [AArch64] Factor out N->getOperand()s; format. NFCI.Ahmed Bougacha2015-03-171-13/+12
| | | | llvm-svn: 232458
* [IRCE] Add a -irce-print-range-checks option.Sanjoy Das2015-03-171-6/+15
| | | | | | | -irce-print-range-checks prints out the set of range checks recognized by IRCE. llvm-svn: 232451
* MapMetadata: Allow unresolved metadata if it won't changeDuncan P. N. Exon Smith2015-03-171-1/+5
| | | | | | | | | Allow unresolved nodes through the `MapMetadata()` if `RF_NoModuleLevelChanges`, since there's no remapping to do anyway. This fixes PR22929. I'll add a clang test as a follow-up. llvm-svn: 232449
* [IRCE] Add comments, NFC.Sanjoy Das2015-03-171-4/+27
| | | | | | | This change adds some comments that justify why a potentially overflowing operation is safe. llvm-svn: 232445
* [IRCE] Support half-range checks.Sanjoy Das2015-03-171-128/+152
| | | | | | | | | | | | This change to IRCE gets it to recognize "half" range checks. Half range checks are range checks that only either check if the index is `slt` some positive integer ("length") or if the index is `sge` `0`. The range solver does not try to be clever / aggressive about solving half-range checks -- it transforms "I < L" to "0 <= I < L" and "0 <= I" to "0 <= I < INT_SMAX". This is safe, but not always optimal. llvm-svn: 232444
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