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* Revert "[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)"Martin Storsjo2018-05-032-36/+6
| | | | | | | This reverts SVN r331337, see PR37321 for details on the regression it introduced. llvm-svn: 331441
* [TableGen][NFC] Make ResourceCycles definitions more explicit.Clement Courbet2018-05-033-12/+12
| | | | | | https://reviews.llvm.org/D46356 llvm-svn: 331439
* [LoopIdiomRecognize] When looking for 'x & (x -1)' for popcnt, make sure the ↵Craig Topper2018-05-031-1/+1
| | | | | | left hand side of the 'and' matches the left hand side of the 'subtract' llvm-svn: 331437
* [LoopIdiomRecognize] Remove unnecessary cast from BinaryOperator to ↵Craig Topper2018-05-031-4/+3
| | | | | | | | Instruction. NFC BinaryOperator is a sub class of Instruction. We don't need an explicit cast back to Instruction. llvm-svn: 331432
* Re-enable "[SCEV] Make computeExitLimit more simple and more powerful"Max Kazantsev2018-05-031-58/+17
| | | | | | | | | | | This patch was temporarily reverted because it has exposed bug 37229 on PowerPC platform. The bug is unrelated to the patch and was just a general bug in the optimization done for PowerPC platform only. The bug was fixed by the patch rL331410. This patch returns the disabled commit since the bug was fixed. llvm-svn: 331427
* [Support] Support building LLVM for FuchsiaPetr Hosek2018-05-031-0/+3
| | | | | | | | | | These are necessary changes to support building LLVM for Fuchsia. While these are not sufficient to run on Fuchsia, they are still useful when cross-compiling LLVM libraries and runtimes for Fuchsia. Differential Revision: https://reviews.llvm.org/D46345 llvm-svn: 331423
* [ObjCARC] Convert an if to an early continue. NFCShoaib Meenai2018-05-031-29/+29
| | | | | | | | This reduces nesting and makes the logic slightly easier to follow. Differential Revision: https://reviews.llvm.org/D46371 llvm-svn: 331422
* Commit r331416 breaks the big-endian PPC bot. On the big endian build, weNemanja Ivanovic2018-05-031-0/+3
| | | | | | | actually encounter constants wider than 64-bits. Add the guard to prevent tripping the assert. llvm-svn: 331420
* [gcov] Switch to an explicit if clunky array to satisfy some compilersChandler Carruth2018-05-031-9/+8
| | | | | | | on various build bots that are unhappy with using makeArrayRef with an initializer list. llvm-svn: 331418
* MachineInst support mapping SDNode fast math flags for support in Back End ↵Michael Berg2018-05-035-6/+71
| | | | | | | | | | | | | | | | | | code generation Summary: Machine Instruction flags for fast math support and MIR print support Reviewers: spatel, arsenm Reviewed By: arsenm Subscribers: wdng Differential Revision: https://reviews.llvm.org/D45781 llvm-svn: 331417
* [PowerPC] Implement isMaskAndCmp0FoldingBeneficialNemanja Ivanovic2018-05-022-0/+15
| | | | | | | | | | | Sinking the and closer to a compare against zero is beneficial on PPC as it allows us to emit record-form instructions. In the future, we may expand this to a larger set of operations that feed compares against zero since PPC has lots of record-form instructions. Differential revision: https://reviews.llvm.org/D46060 llvm-svn: 331416
* [WebAssembly] MC: Create and use first class section symbolsSam Clegg2018-05-024-162/+117
| | | | | | Differential Revision: https://reviews.llvm.org/D46335 llvm-svn: 331413
* [MC] Factor MCObjectStreamer::addFragmentAtoms out of MachO streamer.Sam Clegg2018-05-023-24/+30
| | | | | | | | | This code previously existed only in MCMachOStreamer but is useful for WebAssembly too. See: D46335 Differential Revision: https://reviews.llvm.org/D46297 llvm-svn: 331412
* [PowerPC] No CTR loop if the candidate exiting block is in a different loopNemanja Ivanovic2018-05-021-0/+14
| | | | | | | | | | | | | | | | The CTR loops pass will insert the decrementing branch instruction in an exiting block for the loop being transformed. However if that block is part of another loop as well (whether a nested loop or with irreducible CFG), it is not valid to use that exiting block. In fact, if the loop hass irreducible CFG, we don't bother analyzing it and we just bail on the transformation. In practice, this doesn't lead to a noticeable reduction in the number of loops transformed by this pass. Fixes https://bugs.llvm.org/show_bug.cgi?id=37229 Differential Revision: https://reviews.llvm.org/D46162 llvm-svn: 331410
* [GCOV] Emit the writeout function as nested loops of global data.Chandler Carruth2018-05-021-35/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Prior to this change, LLVM would in some cases emit *massive* writeout functions with many 10s of 1000s of function calls in straight-line code. This is a very wasteful way to represent what are fundamentally loops and creates a number of scalability issues. Among other things, register allocating these calls is extremely expensive. While D46127 makes this less severe, we'll still run into scaling issues with this eventually. If not in the compile time, just from the code size. Now the pass builds up global data structures modeling the inputs to these functions, and simply loops over the data structures calling the relevant functions with those values. This ensures that the code size is a fixed and only data size grows with larger amounts of coverage data. A trivial change to IRBuilder is included to make it easier to build the constants that make up the global data. Reviewers: wmi, echristo Subscribers: sanjoy, mcrosier, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D46357 llvm-svn: 331407
* [X86][SNB] Fix scheduling of MMX integer multiply instructions.Simon Pilgrim2018-05-021-8/+8
| | | | | | The entries were being bound to the wrong class. llvm-svn: 331388
* [X86] Split WriteShuffle/WriteVarShuffle + WriteBlend/WriteVarBlend into XMM ↵Simon Pilgrim2018-05-0210-136/+75
| | | | | | and YMM/ZMM scheduler classes llvm-svn: 331386
* [COFF, ARM64] Hook up a few remaining relocationsMartin Storsjo2018-05-021-0/+9
| | | | | | Differential Revision: https://reviews.llvm.org/D46355 llvm-svn: 331384
* [AMDGPU] A trivial fix for a buildbot failure caused by "commit ↵Farhana Aleen2018-05-021-1/+1
| | | | | | | 224a839fcbbead221f872cd32a1dd0c308d37299". Author: FarhanaAleen llvm-svn: 331383
* [reassociate] Fix excessive revisits when processing long chains of ↵Daniel Sanders2018-05-021-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | reassociatable instructions. Summary: Some of our internal testing detected a major compile time regression which I've tracked down to: r278938 - Revert "Reassociate: Reprocess RedoInsts after each inst". It appears that processing long chains of reassociatable instructions causes non-linear (potentially exponential) growth in the number of times an instruction is revisited. For example, the included test revisits instructions 220 times in a 20-instruction test. It appears that r278938 reversed the order instructions were visited and that this is preventing scheduled revisits from being cancelled as a result of visiting the instructions naturally during normal processing. However, simply reversing the order also harmed the generated code. Upon closer inspection, it was discovered that revisits occurred in the opposite order to the first pass (Thanks to escha for spotting that). This patch makes the revisit order consistent with the first pass which allows more revisits to be cancelled. This does appear to have a small impact on the generated code in few cases but it significantly reduces compile-time. After this patch, our internal test that was most affected by the regression dropped from ~2 million revisits to ~4k resulting in Reassociate having 0.46% of the runtime it had before (99.54% improvement). Here's the summaries reported by lnt for the LLVM test-suite with --benchmarking-only: | metric | geomean before patch | geomean after patch | delta | | ----- | ----- | ----- | ----- | | compile time | 0.1956 | 0.1261 | -35.54% | | execution time | 0.3240 | 0.3237 | - | | code size | 7365.4459 | 7365.6079 | - | The results have a few wins and losses on compile-time, mostly in the +/- 2.5% range. There was one outlier though: | Performance Regressions - compile_time | Δ | Previous | Current | | MultiSource/Benchmarks/ASC_Sequoia/CrystalMk/CrystalMk | 9.82% | 2.0473 | 2.2483 | Reviewers: javed.absar, dberlin Reviewed By: dberlin Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45734 llvm-svn: 331381
* [X86] Cleanup WriteFShuffle/WriteFVarShuffle (+256 variants) scheduler ↵Simon Pilgrim2018-05-025-252/+54
| | | | | | classes with more common default values llvm-svn: 331380
* Add assertion to padding size calculation, NFCKrzysztof Parzyszek2018-05-021-0/+1
| | | | | | | | | | The size of an object cannot be less than the emitted size of all the contained elements. This would cause an overflow in padding size calculation. Add an assert to catch this. Patch by Suyog Sarda. llvm-svn: 331376
* Revert "[AMDGPU] performAddCombine should run after DAG is legalized."Farhana Aleen2018-05-021-1/+1
| | | | | | This reverts commit 6b97d2995566b4dddd6bf0d75579ff44501d4494. llvm-svn: 331371
* [X86] Convert most remaining XOP uses of X86SchedWritePair scheduler classes ↵Simon Pilgrim2018-05-021-88/+102
| | | | | | to X86SchedWriteWidths. llvm-svn: 331369
* [AMDGPU] performAddCombine should run after DAG is legalized.Farhana Aleen2018-05-021-1/+1
| | | | | | | | | | | | | | | | Summary: performAddCombine should run after DAG is legalized; Otherwise generic optimization in the DAGCombiner can optimize an addcarry+trunc into an addcarry instruction with illegal types. Author: FarhanaAleen Reviewed By: rampitec Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D46337 llvm-svn: 331368
* Fix line-endings. NFCI.Simon Pilgrim2018-05-021-3/+3
| | | | llvm-svn: 331367
* Re-land rL331357 "[X86] Fix scheduling info for VMPSADBWYrmi."Clement Courbet2018-05-021-1/+1
| | | | | | | | Without the rebase mess. https://reviews.llvm.org/D46356 llvm-svn: 331362
* [X86] Cleanup WriteFMul scheduler classes with more common default valuesSimon Pilgrim2018-05-023-70/+14
| | | | | | Intel models were targeting x87 instead of packed sse. llvm-svn: 331360
* Fix '32-bit shift implicitly converted to 64 bits' warning by using ↵Simon Pilgrim2018-05-021-1/+1
| | | | | | APInt::setBit instead. llvm-svn: 331359
* Revert rL331355 "[X86] Fix scheduling info for VMPSADBWYrmi."Clement Courbet2018-05-021-16/+5
| | | | | | It contains unrelated changes. llvm-svn: 331357
* [X86] Fix scheduling info for (V?)SQRTPDm on silvermont.Clement Courbet2018-05-021-1/+1
| | | | | | https://reviews.llvm.org/D46356 llvm-svn: 331356
* [X86] Fix scheduling info for VMPSADBWYrmi.Clement Courbet2018-05-021-5/+16
| | | | | | https://reviews.llvm.org/D46356 llvm-svn: 331355
* [MIPS] Fix DIV/DIVU scheduling classes.Clement Courbet2018-05-021-2/+2
| | | | | | https://reviews.llvm.org/D46356. llvm-svn: 331354
* [X86] Convert most remaining AVX512 uses of X86SchedWritePair scheduler ↵Simon Pilgrim2018-05-022-245/+279
| | | | | | | | classes to X86SchedWriteWidths. We've dealt with the majority already. llvm-svn: 331353
* [AArch64][SVE] Asm: Support for LDR/STR fill and spill instructions.Sander de Smalen2018-05-022-1/+109
| | | | | | | | | | Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: samparker Differential Revision: https://reviews.llvm.org/D46270 llvm-svn: 331352
* [TableGen] Don't quote variable name when printing !foreach.Simon Tatham2018-05-021-3/+5
| | | | | | | | | | | | | | | | | An input !foreach expression such as !foreach(a, lst, !add(a, 1)) would be re-emitted by llvm-tblgen -print-records with the first argument in quotes, giving !foreach("a", lst, !add(a, 1)), which isn't valid TableGen input syntax. Reviewers: nhaehnle Reviewed By: nhaehnle Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46352 llvm-svn: 331351
* [AArch64][SVE] Asm: Support for scatter ST1 store instructions.Sander de Smalen2018-05-022-0/+172
| | | | | | | | | | Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46248 llvm-svn: 331349
* Revert "[mips] Correct the predicates of sign extension instructions"Simon Dardis2018-05-024-5/+29
| | | | | | | | | I accidently committed this patch after asking for a review, but it has not been reviewed yet. This reverts r331346. llvm-svn: 331348
* [X86] Convert most remaining uses of X86SchedWritePair scheduler classes to ↵Simon Pilgrim2018-05-022-194/+222
| | | | | | | | X86SchedWriteWidths. We've dealt with the majority already. llvm-svn: 331347
* [mips] Correct the predicates of sign extension instructionsSimon Dardis2018-05-024-29/+5
| | | | | | And eliminate the duplication of those instructions for microMIPS32r6. llvm-svn: 331346
* [AArch64][SVE] Asm: Support for non-temporal, contiguous LDNT1/STNT1 ↵Sander de Smalen2018-05-022-0/+150
| | | | | | | | | | | | load/store instructions. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: samparker Differential Revision: https://reviews.llvm.org/D46269 llvm-svn: 331343
* [LoopInterchange] Update some loops to use range base for loops (NFC).Florian Hahn2018-05-021-30/+24
| | | | llvm-svn: 331342
* [mips] Correct the predicates for shifts.Simon Dardis2018-05-022-23/+21
| | | | | | | | Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
* [X86] Cleanup WriteFAdd/WriteFCmp scheduler classes with more common default ↵Simon Pilgrim2018-05-026-105/+41
| | | | | | | | | | values Intel models were targeting x87 instead of packed sse. Also fixes XOP's VFRCZ to use WriteFAdd/WriteFAddY. llvm-svn: 331340
* [AArch64][SVE] Asm: Support for LD1RQ load-and-replicate quad-word vector ↵Sander de Smalen2018-05-024-0/+77
| | | | | | | | | | | | instructions. Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D46250 llvm-svn: 331339
* [SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)Bjorn Pettersson2018-05-022-6/+36
| | | | | | | | | | | | | | | | | | | | | Summary: This is a follow up to rL331182. A PHI node can be split up into several MIR PHI nodes when being selected. When there is a dbg.value intrinsic that uses the result of such a PHI node we need to select several DBG_VALUE instructions, with fragment expressions, in order to do a correct selection. Reviewers: rnk, aprantl, vsk Reviewed By: vsk Subscribers: mattd, llvm-commits, JDevlieghere, aprantl, gbedwell, rnk Tags: #debug-info Differential Revision: https://reviews.llvm.org/D46329 llvm-svn: 331337
* Fix release build breakageSam Clegg2018-05-021-0/+2
| | | | | | | This function was added in rL331220 but wasn't testing in release configurations. llvm-svn: 331320
* [AMDGPU] Support horizontal vectorization.Farhana Aleen2018-05-013-0/+43
| | | | | | | | | | | | Author: FarhanaAleen Reviewed By: rampitec, arsenm Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D46213 llvm-svn: 331313
* [CFLGraph][NFC] Simplify/reorder switch in visitConstantExprDavid Bolvansky2018-05-011-37/+17
| | | | | | | | | | | | Reviewers: hfinkel, efriedma, spatel, dsanders, Danil, rjmccall Reviewed By: rjmccall Subscribers: dberlin, llvm-commits Differential Revision: https://reviews.llvm.org/D46259 llvm-svn: 331312
* [AggressiveInstCombine] convert a chain of 'or-shift' bits into masked compareSanjay Patel2018-05-011-21/+94
| | | | | | | | | | | | | | | | | | | | | and (or (lshr X, C), ...), 1 --> (X & C') != 0 I initially thought about implementing the minimal pattern in instcombine as mentioned here: https://bugs.llvm.org/show_bug.cgi?id=37098#c6 ...but we need to do better to catch the more general sequence from the motivating test (more than 2 bits in the compare). And a test-suite run with statistics showed that this pattern only happened 2 times currently. It would potentially happen more often if reassociation worked better (D45842), but it's probably still not too frequent? This is small enough that I didn't see a need to create a whole new class/file within AggressiveInstCombine. There are likely other relatively small matchers like what was discussed in D44266 that would slide under foldUnusualPatterns() (name suggestions welcome). We could potentially also consolidate matchers for ctpop, bswap, etc under here. Differential Revision: https://reviews.llvm.org/D45986 llvm-svn: 331311
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