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* Revert "Revert r311552: [Bash-autocompletion] Add support for static ↵Yuka Takahashi2017-08-291-6/+19
| | | | | | | | | | | analyzer flags" This reverts commit 7c46b80c022e18d43c1fdafb117b0c409c5a6d1e. r311552 broke lld buildbot because I've changed OptionInfos type from ArrayRef to vector. However the bug is fixed, so I'll commit this again. llvm-svn: 311958
* [codeview] support more DW_OPs for more complete debug infoBob Haarman2017-08-294-86/+192
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Some variables show up in Visual Studio as "optimized out" even in -O0 -Od builds. This change fixes two issues that would cause this to happen. The first issue is that not all DIExpressions we generate were recognized by the CodeView writer. This has been addressed by adding support for DW_OP_constu, DW_OP_minus, and DW_OP_plus. The second issue is that we had no way to encode DW_OP_deref in CodeView. We get around that by changinge the type we encode in the debug info to be a reference to the type in the source code. This fixes PR34261. Reviewers: aprantl, rnk, zturner Reviewed By: rnk Subscribers: mgorny, llvm-commits, aprantl, hiraditya Differential Revision: https://reviews.llvm.org/D36907 llvm-svn: 311957
* [sanitizer-coverage] Return the array from CreatePCArray. NFCJustin Bogner2017-08-281-9/+12
| | | | | | | | | | | Be more consistent with CreateFunctionLocalArrayInSection in the API of CreatePCArray, and assign the member variable in the caller like we do for the guard and 8-bit counter arrays. This also tweaks the order of method declarations to match the order of definitions in the file. llvm-svn: 311955
* [sanitizer-coverage] Clean up trailing whitespace. NFCJustin Bogner2017-08-281-6/+6
| | | | llvm-svn: 311954
* Fix a logic error in DwarfExpression::addMachineReg()Adrian Prantl2017-08-281-4/+3
| | | | | | | | | This fixes PR34323 and thus splitting undescribable registers into smaller, describable sub-registers. https://bugs.llvm.org/show_bug.cgi?id=34323 llvm-svn: 311951
* Remove an unnecessary const_cast.Adam Nemet2017-08-281-1/+2
| | | | | | I think that this is dating back to when emit used to take a const reference. llvm-svn: 311948
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-08-281-13/+34
| | | | | | | | Add new predicate to more accurately model the scheduling around branches and function calls and of loads and stores of pairs and integer multiplications. llvm-svn: 311944
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-08-283-46/+97
| | | | | | | | | Add new predicate to more accurately model the cost of arithmetic and logical operations shifted left. Differential revision: https://reviews.llvm.org/D37151 llvm-svn: 311943
* Define NetBSD/amd64 ASAN Shadow OffsetKamil Rytarowski2017-08-281-0/+4
| | | | | | | | | | | | | | | | | | | | Summary: Catch up after compiler-rt changes and define kNetBSD_ShadowOffset64 as (1ULL << 46). Sponsored by <The NetBSD Foundation> Reviewers: kcc, joerg, filcab, vitalybuka, eugenis Reviewed By: eugenis Subscribers: llvm-commits, #sanitizers Tags: #sanitizers Differential Revision: https://reviews.llvm.org/D37234 llvm-svn: 311941
* [InstCombine] Teach select01 helper of foldSelectIntoOp to handle vector splatsCraig Topper2017-08-281-7/+6
| | | | | | | | We were handling some vectors in foldSelectIntoOp, but not if the operand of the bin op was any kind of vector constant. This patch fixes it to treat vector splats the same as scalars. Differential Revision: https://reviews.llvm.org/D37232 llvm-svn: 311940
* [AArch64][Falkor] Avoid generating STRQro* instructionsGeoff Berry2017-08-284-10/+25
| | | | | | | | | | | | | | | Summary: STRQro* instructions are slower than the alternative ADD/STRQui expanded instructions on Falkor, so avoid generating them unless we're optimizing for code size. Reviewers: t.p.northover, mcrosier Subscribers: aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D37020 llvm-svn: 311931
* [LoopUnroll] Properly update loop structure in case of successful peeling.Davide Italiano2017-08-281-2/+13
| | | | | | | | | | | When peeling kicks in, it updates the loop preheader. Later, a successful full unroll of the loop needs to update a PHI which i-th argument comes from the loop preheader, so it'd better look at the correct block. Fixes PR33437. Differential Revision: https://reviews.llvm.org/D37153 llvm-svn: 311922
* Fix ARMv4 supportJoerg Sonnenberger2017-08-289-10/+35
| | | | | | | | | | | | | | | | | | ARMv4 doesn't support the "BX" instruction, which has been introduced with ARMv4t. Adjust the call lowering and tail call implementation accordingly. Further changes are necessary to ensure that presence of the v4t feature is correctly set. Most importantly, the "generic" CPU for thumb-* triples should include ARMv4t, since thumb mode without thumb support would naturally be pointless. Add a couple of asserts to ensure thumb instructions are not emitted without CPU support. Differential Revision: https://reviews.llvm.org/D37030 llvm-svn: 311921
* [LoopUnroll] Add a cl::opt to force peeling, for testing purposes.Davide Italiano2017-08-281-0/+6
| | | | | | Will be used to test the patch proposed in D37153. llvm-svn: 311915
* [ARM] Fix bug in ARMLoadStoreOptimizer when kill flags are missing.Geoff Berry2017-08-281-30/+19
| | | | | | | | | | | | | | | | | | | | | | Summary: ARMLoadStoreOpt::FixInvalidRegPairOp() was only checking if one of the load destination registers to be split overlapped with the base register if the base register was marked as killed. Since kill flags may not always be present, this can lead to incorrect code. This bug was exposed by my MachineCopyPropagation change D30751 breaking the sanitizer-x86_64-linux-android buildbot. Also clean up some dead code and add an assert that a register offset is never encountered by this code, since it does not handle them correctly. Reviewers: MatzeB, qcolombet, t.p.northover Subscribers: aemerson, javed.absar, kristof.beyls, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D37164 llvm-svn: 311907
* Create PHI node for the return value only when the return value has uses.Taewook Oh2017-08-281-0/+3
| | | | | | | | | | | | | | | | | | | Summary: Currently, a phi node is created in the normal destination to unify the return values from promoted calls and the original indirect call. This patch makes this phi node to be created only when the return value has uses. This patch is necessary to generate valid code, as compiler crashes with the attached test case without this patch. Without this patch, an illegal phi node that has no incoming value from `entry`/`catch` is created in `cleanup` block. I think existing implementation is good as far as there is at least one use of the original indirect call. `insertCallRetPHI` creates a new phi node in the normal destination block only when the original indirect call dominates its use and the normal destination block. Otherwise, `fixupPHINodeForNormalDest` will handle the unification of return values naturally without creating a new phi node. However, if there's no use, `insertCallRetPHI` still creates a new phi node even when the original indirect call does not dominate the normal destination block, because `getCallRetPHINode` returns false. Reviewers: xur, davidxl, danielcdh Reviewed By: xur Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37176 llvm-svn: 311906
* [CodeView] Don't output S_UDT symbols for forward decls.Zachary Turner2017-08-282-16/+35
| | | | | | | | | | | | | | | | | | | | | | S_UDT symbols are the debugger's "index" for all the structs, typedefs, classes, and enums in a program. If any of those structs/classes don't have a complete declaration, or if there is a typedef to something that doesn't have a complete definition, then emitting the S_UDT is unhelpful because it doesn't give the debugger enough information to do anything useful. On the other hand, it results in a huge size blow-up in the resulting PDB, which is exacerbated by an order of magnitude when linking with /DEBUG:FASTLINK. With this patch, we drop S_UDT records for types that refer either directly or indirectly (e.g. through a typedef, pointer, etc) to a class/struct/union/enum without a complete definition. This brings us about 50% of the way towards parity with /DEBUG:FASTLINK PDBs generated from cl-compiled object files. Differential Revision: https://reviews.llvm.org/D37162 llvm-svn: 311904
* [Power9] Add new instructions for floating point status and control registers.Stefan Pintilie2017-08-282-0/+91
| | | | | | | | | Added the following P9 instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl Differential Revision: https://reviews.llvm.org/D37167 llvm-svn: 311903
* [InstCombine] Call hasNoSignedWrap instead of hasNoUnsignedWrap to get the ↵Craig Topper2017-08-281-1/+1
| | | | | | | | | | NSW flag when handling Add in SimplifyDemandedUseBits. This is a typo from r311789. This should fix PR34349. llvm-svn: 311902
* [Hexagon] Check for potential bank conflicts in post-RA schedulingKrzysztof Parzyszek2017-08-283-0/+55
| | | | | | | Insert artificial edges between loads that could cause a cache bank conflict. llvm-svn: 311901
* [AMDGPU] Fix regression in AMDGPULibCalls allowing native for doublesStanislav Mekhanoshin2017-08-281-3/+3
| | | | | | | | | | | | | Under -cl-fast-relaxed-math we could use native_sqrt, but f64 was allowed to produce HSAIL's nsqrt instruction. HSAIL is not here and we stick with non-existing native_sqrt(double) as a result. Add check for f64 to not return native functions and also remove handling of f64 case for fold_sqrt. Differential Revision: https://reviews.llvm.org/D37223 llvm-svn: 311900
* [AMDGPU] computeKnownBitsForTargetNode for 24 bit mulStanislav Mekhanoshin2017-08-281-1/+31
| | | | | | Differential Revision: https://reviews.llvm.org/D37168 llvm-svn: 311896
* [Hexagon] Break up DAG mutations into separate classes, move to subtargetKrzysztof Parzyszek2017-08-286-139/+141
| | | | llvm-svn: 311895
* [Hexagon] Move pre-RA DAG mutations to scheduler constructorKrzysztof Parzyszek2017-08-283-15/+15
| | | | llvm-svn: 311894
* [X86] Make 128/256-bit extract_subvector Legal instead of Custom. Move ↵Craig Topper2017-08-281-32/+25
| | | | | | | | | | | | combining with BUILD_VECTOR from Legalization to DAG combine EXTRACT_SUBVECTOR was marked Custom solely so we could combine it with BUILD_VECTOR operations to create smaller BUILD_VECTORS during Legalization. But that sort of combining should really be done by the DAG combiner. This patch adds the last piece of needed supported DAG combine to handle this. Once that's done we can make the EXTRACT_SUBVECTOR operations Legal. Differential Revision: https://reviews.llvm.org/D37197 llvm-svn: 311893
* [DAGCombiner] Teach visitEXTRACT_SUBVECTOR to turn extracts of BUILD_VECTOR ↵Craig Topper2017-08-281-0/+23
| | | | | | | | | | into smaller BUILD_VECTORs Only do this before operations are legalized of BUILD_VECTOR is Legal for the target. Differential Revision: https://reviews.llvm.org/D37186 llvm-svn: 311892
* The current version of LLVM X86 disassembler incorrectly interprets some ↵Andrew V. Tischenko2017-08-282-17/+71
| | | | | | | | | | | | | | possible sets of x86 prefixes. This patch is the first step to close PR7709 and PR17697. There will be next patch(es) to close relative PRs. Differential Revision: https://reviews.llvm.org/D36788 M lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp M lib/Target/X86/Disassembler/X86DisassemblerDecoder.h A test/MC/Disassembler/X86/prefixes-i386.s A test/MC/Disassembler/X86/prefixes-x86_64.s M test/MC/Disassembler/X86/prefixes.txt llvm-svn: 311882
* [X86][Haswell] Updating HSW instruction scheduling informationGadi Haber2017-08-281-1204/+3475
| | | | | | | | | | | | | | | This patch completely replaces the instruction scheduling information for the Haswell architecture target by modifying the file X86SchedHaswell.td located under the X86 Target. We used the scheduling information retrieved from the Haswell architects in order to replace and modify the existing scheduling. The patch continues the scheduling replacement effort started with the SNB target in r307529 and r310792. Information includes latency, number of micro-Ops and used ports by each HSW instruction. Please expect some performance fluctuations due to code alignment effects. Reviewers: RKSimon, zvi, aymanmus, craig.topper, m_zuckerman, igorb, dim, chandlerc, aaboud Differential Revision: https://reviews.llvm.org/D36663 llvm-svn: 311879
* Untabify.NAKAMURA Takumi2017-08-2813-65/+65
| | | | llvm-svn: 311875
* [X86] Use getUnpackl helper to create an ISD::VECTOR_SHUFFLE instead of ↵Craig Topper2017-08-281-1/+1
| | | | | | | | using X86ISD::UNPCKL in reduceVMULWidth. This runs fairly early, we should use target independent nodes if possible. llvm-svn: 311873
* [X86] Add an early out to combineLoopMAddPattern and combineLoopSADPattern ↵Craig Topper2017-08-281-0/+6
| | | | | | | | when SSE2 is disabled. Without this the madd.ll and sad.ll test cases both throw assertions if you run them with SSE2 disabled. llvm-svn: 311872
* revert r310985 which breaks for the following case:Dehao Chen2017-08-271-2/+0
| | | | | | | | | | | | | | | | | | | | | struct string { ~string(); }; void f2(); void f1(int) { f2(); } void run(int c) { string body; while (true) { if (c) f1(c); else f1(c); } } Will recommit once the issue is fixed. llvm-svn: 311864
* [mips] Generate NMADD and NMSUB instructions when fneg node is presentPetar Jovanovic2017-08-272-0/+20
| | | | | | | | | | | | This patch enables generation of NMADD and NMSUB instructions when fneg node is present. These instructions are currently only generated if fsub node is present. Patch by Stanislav Ocovaj. Differential Revision: https://reviews.llvm.org/D34507 llvm-svn: 311862
* [ARM] Tidy-up condition-code support functionsJaved Absar2017-08-273-102/+89
| | | | | | | | | Move condition code support functions to Utils and remove code duplication. Reviewed by: @fhahn, @asb Differential Revision: https://reviews.llvm.org/D37179 llvm-svn: 311860
* [AVX512] Add more patterns for using masked moves for subvector extracts of ↵Craig Topper2017-08-271-123/+58
| | | | | | the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
* [DAGCombiner] allow undef shuffle operands when eliminating bitcasts (PR34111)Sanjay Patel2017-08-271-1/+4
| | | | | | | | As noted in the FIXME, this could be improved more, but this is the smallest fix that helps: https://bugs.llvm.org/show_bug.cgi?id=34111 llvm-svn: 311853
* [ARM] Tidy-up ARMAsmParser. NFC.Javed Absar2017-08-271-23/+5
| | | | | | | | | Simplify getDRegFromQReg function Reviewed by: @fhahn, @asb Differential Revision: https://reviews.llvm.org/D37118 llvm-svn: 311850
* [LV] Fix PR34248 - recommit D32871 after revert r311304Ayal Zaks2017-08-274-523/+2247
| | | | | | | | | | | Original commit r311077 of D32871 was reverted in r311304 due to failures reported in PR34248. This recommit fixes PR34248 by restricting the packing of predicated scalars into vectors only when vectorizing, avoiding doing so when unrolling w/o vectorizing. Added a test derived from the reproducer of PR34248. llvm-svn: 311849
* [X86] Add a target-specific DAG combine to combine extract_subvector from ↵Craig Topper2017-08-271-0/+22
| | | | | | all zero/one build_vectors. llvm-svn: 311841
* [X86] Use getOnesVector instead of using DAG.getConstant(-1).Craig Topper2017-08-271-1/+1
| | | | llvm-svn: 311840
* [NewGVN] Use `auto` when the type is obvious NFCI.Davide Italiano2017-08-261-2/+2
| | | | llvm-svn: 311838
* [AVX512] Add patterns to match masked extract_subvector with bitcasts ↵Craig Topper2017-08-262-21/+106
| | | | | | | | | | between the vselect and the extract_subvector. Remove the late DAG combine. We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't. Add some more test cases to ensure we've also got most of the zero masking covered too. llvm-svn: 311837
* [Dominators] Remove redundant explicit template instantiation.Don Hinton2017-08-261-2/+0
| | | | | | | | | | | | | | | Summary: Remove redundant explicit template instantiation. This was reported by Andrew Kelley building release_50 with gcc7.2.0 on MacOS: duplicate symbol llvm::DominatorTreeBase. Reviewers: kuhar, andrewrk, davide, hans Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37185 llvm-svn: 311835
* [DAGCombiner] Extending pattern detection for vector shuffle.Jatin Bhateja2017-08-261-3/+53
| | | | | | | | | | | | | | | | | | Summary: If all the operands of a BUILD_VECTOR extract elements from same vector then split the vector efficiently based on the maximum vector access index. This will also fix PR 33784 Reviewers: zvi, delena, RKSimon, thakis Reviewed By: RKSimon Subscribers: chandlerc, eladcohen, llvm-commits Differential Revision: https://reviews.llvm.org/D35788 llvm-svn: 311833
* Revert rL311247 : To rectify commit message.Jatin Bhateja2017-08-261-53/+3
| | | | | | | | Summary: This reverts commit rL311247. Differential Revision: https://reviews.llvm.org/D36927 llvm-svn: 311832
* NewGVN: Fix PR33204 - We need to add memory users when we bypass memorydefs ↵Daniel Berlin2017-08-261-4/+8
| | | | | | for loads, not just when we do it for stores. llvm-svn: 311829
* [X86] Qualify the RMW INC/DEC patterns with NotSlowIncDec.Craig Topper2017-08-261-2/+2
| | | | | | We were suppressing most uses of INC/DEC, but this one seems to have been missed. llvm-svn: 311828
* Add options to dump block frequency/branch probability info in text.Hiroshi Yamauchi2017-08-263-0/+42
| | | | | | | | | | | | | | | | | | | | | Summary: Add options -print-bfi/-print-bpi that dump block frequency and branch probability info like -view-block-freq-propagation-dags and -view-machine-block-freq-propagation-dags do but in text. This is useful when the graph is very large and complex (the dot command crashes, lines/edges too close to tell apart, hard to navigate without textual search) or simply when text is preferred. Reviewers: davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37165 llvm-svn: 311822
* [AVX512] Add patterns to use masked moves to implement masked ↵Craig Topper2017-08-251-0/+133
| | | | | | | | extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
* [x86] Teach the backend to fold more read-modify-write memory operandsChandler Carruth2017-08-251-53/+73
| | | | | | | | | | | | | | | | | | | | | | | | to instructions. These can't be reasonably matched in tablegen due to the handling of flags, so we have to do this in C++ code. We only did it for `inc` and `dec` historically, this starts fleshing that out to more interesting instructions. Notably, this handles transfering operands to `add` and `sub`. Currently this forces them into a register. The next patch will add support for keeping immediate operands as immediates. Then I'll extend this beyond just `add` and `sub`. I'm not super thrilled by the repeated switches in the code but everything else I tried was really ugly or problematic. Many thanks to Craig Topper for the suggestions about where to even begin here and how to make this stuff work. Differential Revision: https://reviews.llvm.org/D37130 llvm-svn: 311806
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