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* ARM non-scattered MachO relocations for movw/movt.Jim Grosbach2012-03-201-22/+58
| | | | | | | | Needed when building -mdynamic-no-pic code. rdar://10459256 llvm-svn: 153097
* [avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads.Chad Rosier2012-03-201-3/+3
| | | | | | | | | | | | | | | This results in things such as vmovups 16(%rdi), %xmm0 vinsertf128 $1, %xmm0, %ymm0, %ymm0 to be combined to vinsertf128 $1, 16(%rdi), %ymm0, %ymm0 rdar://11076953 llvm-svn: 153092
* The ARM instructions that have an unpredictable behavior when the pc ↵Silviu Baranga2012-03-202-4/+10
| | | | | | register operand is given now fail with soft fail. Modified the regression tests to reflect this. llvm-svn: 153089
* Test Commit - add a newlineRichard Barton2012-03-201-0/+1
| | | | llvm-svn: 153083
* It's possible to have a constant expression who's size is quite big (e.g.,Bill Wendling2012-03-201-11/+17
| | | | | | | | | | | | | | i128). In that case, we may not be able to print out the MCExpr as an expression. For instance, we could have an MCExpr like this: 0xBEEF0000BEEF0000 | (0xBEEF0000BEEF0000 << 64) The MCExpr printer handles sizes up to 64-bits, but this expression would require 128-bits. In this situation, try to evaluate the constant expression and emit that as the value into 64-bit chunks. <rdar://problem/11070338> llvm-svn: 153081
* Remove code that prevented lowering shuffles if they are used by load and ↵Craig Topper2012-03-201-92/+111
| | | | | | themselves used by a extract_vector_elt. This was done to allow the DAG combiner to collapse to a single element load. Unfortunately, sometimes the extract_vector_elt would disappear before DAG combine could do the transformation leaving a vector_shuffle that isel couldn't handle. New code lets the shuffle be converted to a target specific node, but then adds a combine routine that can convert target specific nodes back to vector_shuffles if the folding criteria are met. llvm-svn: 153080
* Factor out target shuffle mask decoding from getShuffleScalarElt and use a ↵Craig Topper2012-03-204-96/+95
| | | | | | SmallVector of int instead of unsigned for shuffle mask in decode functions. Preparation for another change. llvm-svn: 153079
* When combining (vextract shuffle (load ), <1,u,u,u>), 0) -> (load ), add ↵Craig Topper2012-03-201-0/+1
| | | | | | users of the final load to the worklist too. Needed by changes I'm preparing to make to X86 backend. llvm-svn: 153078
* Do everything up to generating code to try to get a register forEric Christopher2012-03-201-1/+6
| | | | | | | | | | a variable. The previous code would break the debug info changing code invariant. This will regress debug info for arguments where we elide the alloca created. Fixes rdar://11066468 llvm-svn: 153074
* Untabify.Eric Christopher2012-03-201-2/+2
| | | | llvm-svn: 153073
* Add another debugging statement here.Eric Christopher2012-03-201-0/+4
| | | | llvm-svn: 153072
* Use lookUpRegForValue here instead of duplicating the code.Eric Christopher2012-03-201-9/+2
| | | | llvm-svn: 153071
* f16 FDIV can now be legalized by promoting to f32Pete Cooper2012-03-191-1/+2
| | | | llvm-svn: 153064
* fix a build failure with libc++Chris Lattner2012-03-191-0/+1
| | | | llvm-svn: 153063
* ARM branch relaxation for unconditional t1 branches.Jim Grosbach2012-03-191-0/+11
| | | | | | rdar://11059157 llvm-svn: 153055
* ARM assembly, accept optional '#' on lane index number.Jim Grosbach2012-03-191-0/+6
| | | | | | rdar://11057160 llvm-svn: 153053
* [Object/COFF]: Expose getSectionContents.Michael J. Spencer2012-03-191-10/+19
| | | | llvm-svn: 153051
* [Object/COFF]: Expose getSectionName.Michael J. Spencer2012-03-191-19/+24
| | | | | | Also add some documentation. llvm-svn: 153050
* Perform mul combine when multiplying wiht negative constants.Anton Korobeynikov2012-03-191-18/+48
| | | | | | | Patch by Weiming Zhao! This fixes PR12212 llvm-svn: 153049
* Add an option to the MI scheduler to cut off scheduling after a fixed number ofLang Hames2012-03-191-1/+19
| | | | | | | instructions have been scheduled. Handy for tracking down scheduler bugs, or bugs exposed by scheduling. llvm-svn: 153045
* [asan] don't emit __asan_mapping_offset/__asan_mapping_scale by default -- ↵Kostya Serebryany2012-03-191-12/+17
| | | | | | they are currently used only for experiments llvm-svn: 153040
* Fix DAG combine which creates illegal vector shuffles. Patch by Heikki Kultala.Duncan Sands2012-03-191-0/+6
| | | | llvm-svn: 153035
* This patch adds X86 instruction itineraries for non-pseudo opcodes inPreston Gurd2012-03-193-51/+82
| | | | | | | | | | X86InstrCompiler.td. It also adds –mcpu-generic to the legalize-shift-64.ll test so the test will pass if run on an Intel Atom CPU, which would otherwise produce an instruction schedule which differs from that which the test expects. llvm-svn: 153033
* Add a note for -ffast-math optimization of vector norm.Benjamin Kramer2012-03-191-0/+19
| | | | llvm-svn: 153031
* Factor out the multiply analysis code in ComputeMaskedBits and apply it to theNick Lewycky2012-03-181-62/+76
| | | | | | | | overflow checking multiply intrinsic as well. Add a test for this, updating the test from grep to FileCheck. llvm-svn: 153028
* isCommutedMOVLMask should only look at 128-bit vectors to match isMOVLMask.Craig Topper2012-03-181-0/+2
| | | | llvm-svn: 153027
* CriticalAntiDepBreaker: Replace a SmallSet of regs with a much denser BitVector.Benjamin Kramer2012-03-172-11/+12
| | | | llvm-svn: 152999
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-1788-134/+102
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* MachineInstr: Inline the fast path (non-bundle instruction) of hasProperty.Benjamin Kramer2012-03-171-6/+2
| | | | | | This is particularly helpful as both arguments tend to be constants. llvm-svn: 152991
* Fix some copy and paste remnants of Cell and SPU in Hexagon files.Craig Topper2012-03-174-6/+6
| | | | llvm-svn: 152981
* Fix typo in file header.Craig Topper2012-03-171-1/+1
| | | | llvm-svn: 152980
* Pass TargetOptions to HexagonTargetMachine constructor by reference to match ↵Craig Topper2012-03-172-3/+4
| | | | | | other targets and the base class. llvm-svn: 152979
* Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper2012-03-1718-29/+20
| | | | llvm-svn: 152978
* MC asm parser macro argument count was wrong when empty.Jim Grosbach2012-03-171-0/+5
| | | | | | | | evaluated to '1' when the argument list was empty (should be '0'). rdar://11057257 llvm-svn: 152967
* Check if we can handle the arguments of a call (and therefore the call) inBill Wendling2012-03-161-8/+52
| | | | | | | | | | fast-isel before emitting code. If the program bails after code was emitted, then it could lead to the stack being adjusted more than once (two CALLSEQ_BEGINs emitted) but being adjuste back only once after the call. This leads to general badness and gnashing of teeth. <rdar://problem/11050630> llvm-svn: 152959
* ARM fix silly typo in optional operand alias.Jim Grosbach2012-03-161-1/+1
| | | | | | rdar://11065671 llvm-svn: 152954
* ARM divided syntax fmrx/fmxr mnemonics.Jim Grosbach2012-03-161-0/+2
| | | | llvm-svn: 152946
* ARM ldm/stm register lists can be out of order.Jim Grosbach2012-03-161-2/+6
| | | | | | | | | | It's not a good style idea, as the registers will be laid down in memory in numerical order, not the order they're in the list, but it's legal. vldm/vstm are stricter. rdar://11064740 llvm-svn: 152943
* Revert r152907.Bill Wendling2012-03-161-15/+3
| | | | llvm-svn: 152935
* ScheduleDAGInstrs: When adding uses we add them into a set that's empty at ↵Benjamin Kramer2012-03-161-2/+2
| | | | | | the beginning, no need to maintain another set for the added regs. llvm-svn: 152934
* Limit the number of memory operands in MachineInstr to 2^16 and store the ↵Benjamin Kramer2012-03-161-11/+10
| | | | | | | | number in padding. Saves one machine word on MachineInstr (88->80 bytes on x86_64, 48->44 on i386). llvm-svn: 152930
* CriticalAntiDepBreaker: BasicBlock::size is an expensive operation, reuse ↵Benjamin Kramer2012-03-161-7/+7
| | | | | | | | the cached value. No functionality change. llvm-svn: 152927
* The alignment of the pointer part of the store instruction may have anBill Wendling2012-03-161-3/+15
| | | | | | | | | | alignment. If that's the case, then we want to make sure that we don't increase the alignment of the store instruction. Because if we increase it to be "more aligned" than the pointer, code-gen may use instructions which require a greater alignment than the pointer guarantees. <rdar://problem/11043589> llvm-svn: 152907
* Rip out support for 'llvm.noinline'. This thing has a strange history...Chandler Carruth2012-03-161-45/+0
| | | | | | | | | | | | | | | | | | | | | It was added in 2007 as the first cut at supporting no-inline attributes, but we didn't have function attributes of any form at the time. However, it was added without any mention in the LangRef or other documentation. Later on, in 2008, Devang added function notes for 'inline=never' and then turned them into proper function attributes. From that point onward, as far as I can tell, the world moved on, and no one has touched 'llvm.noinline' in any meaningful way since. It's time has now come. We have had better mechanisms for doing this for a long time, all the frontends I'm aware of use them, and this is just holding back progress. Given that it was never a documented feature of the IR, I've provided no auto-upgrade support. If people know of real, in-the-wild bitcode that relies on this, yell at me and I'll add it, but I *seriously* doubt anyone cares. llvm-svn: 152904
* Start removing the use of an ad-hoc 'never inline' set and insteadChandler Carruth2012-03-164-42/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | directly query the function information which this set was representing. This simplifies the interface of the inline cost analysis, and makes the always-inline pass significantly more efficient. Previously, always-inline would first make a single set of every function in the module *except* those marked with the always-inline attribute. It would then query this set at every call site to see if the function was a member of the set, and if so, refuse to inline it. This is quite wasteful. Instead, simply check the function attribute directly when looking at the callsite. The normal inliner also had similar redundancy. It added every function in the module with the noinline attribute to its set to ignore, even though inside the cost analysis function we *already tested* the noinline attribute and produced the same result. The only tricky part of removing this is that we have to be able to correctly remove only the functions inlined by the always-inline pass when finalizing, which requires a bit of a hack. Still, much less of a hack than the set of all non-always-inline functions was. While I was touching this function, I switched a heavy-weight set to a vector with sort+unique. The algorithm already had a two-phase insert and removal pattern, we were just needlessly paying the uniquing cost on every insert. This probably speeds up some compiles by a small amount (-O0 compiles with lots of always-inline, so potentially heavy libc++ users), but I've not tried to measure it. I believe there is no functional change here, but yell if you spot one. None are intended. Finally, the direction this is going in is to greatly simplify the inline cost query interface so that we can replace its implementation with a much more clever one. Along the way, all the APIs get simplified, so it seems incrementally good. llvm-svn: 152903
* Pull the implementation of the code metrics out of the inline costChandler Carruth2012-03-163-158/+177
| | | | | | | | | | | analysis implementation. The header was already separated. Also cleanup all the comments in the header to follow a nice modern doxygen form. There is still plenty of cruft here, but some of that will fall out in subsequent refactorings and this was an easy step in the right direction. No functionality changed here. llvm-svn: 152898
* misched: add DAG edges from vreg defs to ExitSU.Andrew Trick2012-03-161-1/+3
| | | | | | | | | | These edges are not really necessary, but it is consistent with the way we currently create physreg edges. Scheduler heuristics that expect a DAG edge to the block terminator could benefit from this change. Although in the future I hope we have a better mechanism for modeling latency across scheduling regions. llvm-svn: 152895
* LSR fix: Add isSimplifiedLoopNest to IVUsers analysis.Andrew Trick2012-03-164-17/+63
| | | | | | | | | | | | | | Only record IVUsers that are dominated by simplified loop headers. Otherwise SCEVExpander will crash while looking for a preheader. I previously tried to work around this in LSR itself, but that was insufficient. This way, LSR can continue to run if some uses are not in simple loops, as long as we don't attempt to analyze those users. Fixes <rdar://problem/11049788> Segmentation fault: 11 in LoopStrengthReduce llvm-svn: 152892
* Revert r152705, which reapplied r152486 as this appears to be causing failuresChad Rosier2012-03-161-128/+34
| | | | | | | | | | | on our internal nightly testers. So, basically revert r152486 again. Abbreviated original commit message: Implement a more intelligent way of spilling uses across an invoke boundary. It looks as if Chander's inlining work, r152737, exposed an issue. llvm-svn: 152887
* In InstCombiner::visitOr, make sure we reverse the operand swap used for ↵Eli Friedman2012-03-161-1/+7
| | | | | | checking for or-of-xor operations after those checks; a later check expects that any constant will be in Op1. PR12234. llvm-svn: 152884
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