| Commit message (Collapse) | Author | Age | Files | Lines | 
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llvm-svn: 134703
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llvm-svn: 134702
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Should fix llvm-gcc selfhost.
llvm-svn: 134699
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We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building.
  struct foo { char x[24]; };
  long bar(struct foo *a, struct foo *b) { return a-b; }
is now compiled into
  movl	4(%esp), %eax
  subl	8(%esp), %eax
  sarl	$3, %eax
  imull	$-1431655765, %eax, %eax
instead of
  movl	4(%esp), %eax
  subl	8(%esp), %eax
  movl	$715827883, %ecx
  imull	%ecx
  movl	%edx, %eax
  shrl	$31, %eax
  sarl	$2, %edx
  addl	%eax, %edx
  movl	%edx, %eax
llvm-svn: 134695
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- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
  to generate asm matcher subtarget feature queries. e.g.
  "ModeThumb,FeatureThumb2" is translated to
  "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
llvm-svn: 134678
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CSE ops that match values produced by the intrinsics.
llvm-svn: 134677
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llvm-svn: 134671
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llvm-svn: 134668
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Fixes PR9602!
llvm-svn: 134665
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processor supports it just fine.
Fixes PR9675 and rdar://9740801
llvm-svn: 134664
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llvm-svn: 134661
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Part of PR10299 and rdar://9740322
llvm-svn: 134653
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Fixes PR10149 and rdar://9738585
llvm-svn: 134648
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llvm-svn: 134647
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llvm-svn: 134645
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llvm-svn: 134643
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llvm-svn: 134641
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llvm-svn: 134640
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based on a modifier, split it into two functions.
llvm-svn: 134637
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numbers should be printed instead of symbolic register names in
MCAsmStreamer::EmitRegisterName. This is necessary because some versions of
GNU assembler won't accept code in which symbolic register names are used in
cfi directives. There is no change in behavior unless the flag is explicitly
set to true by a backend.
llvm-svn: 134635
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llvm-svn: 134633
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llvm-svn: 134630
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llvm-svn: 134629
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llvm-svn: 134628
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llvm-svn: 134627
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llvm-svn: 134626
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before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.
llvm-svn: 134625
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llvm-svn: 134622
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not identical. For example,
        DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:32:10 ]
        DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:31:10 ]
These two MIs represent identical value, 3.31...,  for one variable, ds, but they are not identical because the represent two separate instances of inlined variable "ds". 
llvm-svn: 134620
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llvm-svn: 134617
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llvm-svn: 134616
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llvm-svn: 134614
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multiply-accumulate instructions with separate rounding steps.
llvm-svn: 134609
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llvm-svn: 134608
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llvm-svn: 134606
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llvm-svn: 134601
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llvm-svn: 134599
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llvm-svn: 134595
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hasPredecessorHelper function allows predecessors to be cached to speed up
repeated invocations. This fixes PR10186.
X.isPredecessorOf(Y) now just calls Y.hasPredecessor(X)
Y.hasPredecessor(X) calls Y.hasPredecessorHelper(X, Visited, Worklist) with
empty Visited and Worklist sets (i.e. no caching over invocations).
Y.hasPredecessorHelper(X, Visited, Worklist) caches search state in Visited
and Worklist to speed up repeated calls. The Visited set is searched for X
before going to the worklist to further search the DAG if necessary.
llvm-svn: 134592
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them down to MC layer. Also fix tests.
llvm-svn: 134590
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llvm-svn: 134577
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llvm-svn: 134572
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ARM subtarget info available to MC.
llvm-svn: 134569
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llvm-svn: 134568
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llvm-svn: 134566
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list on the merged block to correctly account for the live-outs of all the predecessors.  They might not be the same in all cases (the testcase I have involves a PHI node where one of the operands is an IMPLICIT_DEF).
Unfortunately, the testcase I have is large and confidential, so I don't have a test to commit at the moment; I'll see if I can come up with something smaller where this issue reproduces.
<rdar://problem/9716278>
llvm-svn: 134565
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llvm-svn: 134561
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llvm-svn: 134559
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llvm-svn: 134557
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llvm-svn: 134555
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