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* Make writeToResolutionFile a static helper.Rafael Espindola2016-08-261-10/+10
| | | | llvm-svn: 279859
* TailDuplication: Record blocks that received the duplicated block. NFC.Kyle Butt2016-08-261-2/+10
| | | | | | | This will allow tail duplication during layout to handle the cfg changes more cleanly. llvm-svn: 279858
* Next set of additional error checks for invalid Mach-O files for bad ↵Kevin Enderby2016-08-261-5/+50
| | | | | | | | LC_SYMTAB’s. This contains the missing checks for LC_SYMTAB load command fields. llvm-svn: 279854
* Swift Calling Convetion: add support for AArch64.Manman Ren2016-08-262-1/+2
| | | | | | | | It will just be the same as the regular calling convention. rdar://28029509 llvm-svn: 279853
* AArch64: avoid assertion on illegal types in performFDivCombine.Tim Northover2016-08-261-3/+8
| | | | | | | | In the code to detect fixed-point conversions and make use of AArch64's special instructions, we weren't prepared for weird types. The fptosi direction got fixed recently, but not the similar sitofp code. llvm-svn: 279852
* [InstCombine] add helper function for icmp (and (sh X, Y), C2), C1 ; NFCSanjay Patel2016-08-262-45/+64
| | | | | | | | Like other recent changes near here, the goal is to allow vector types for all of these folds. Splitting things up makes it easier to incrementally enhance the code and easier to read. llvm-svn: 279851
* [AArch64] Avoid materializing constant values when generating csel instructions.Chad Rosier2016-08-261-0/+16
| | | | | | Differential Revision: https://reviews.llvm.org/D23677 llvm-svn: 279849
* [AsmParser] Placate a -Wmisleading-indentantion warning (GCC7).Davide Italiano2016-08-261-1/+3
| | | | llvm-svn: 279848
* [MC] Move .cv_loc management logic out of MCContextReid Kleckner2016-08-2612-29/+32
| | | | | | | | | | | MCContext already has many tasks, and separating CodeView out from it is probably a good idea. The .cv_loc tracking was modelled on the DWARF tracking which lived directly in MCContext. Removes the inclusion of MCCodeView.h from MCContext.h, so now there are only 10 build actions while I hack on CodeView support instead of 265. llvm-svn: 279847
* GlobalISel: mark G_FPEXT legal from float to double.Tim Northover2016-08-261-0/+3
| | | | llvm-svn: 279845
* GlobalISel: mark G_FCMP legal on float & double.Tim Northover2016-08-261-0/+4
| | | | llvm-svn: 279844
* GlobalISel: simplify G_ICMP legalization regime.Tim Northover2016-08-262-41/+26
| | | | | | | | | | | | | | It's unclear how the old %res(32) = G_ICMP { s32, s32 } intpred(eq), %0, %1 is actually different from an s1 verison %res(1) = G_ICMP { s1, s32 } intpred(eq), %0, %1 so we'll remove it for now. llvm-svn: 279843
* GlobalISel: legalize sdiv and srem operations.Tim Northover2016-08-264-0/+50
| | | | llvm-svn: 279842
* GlobalISel: legalize under-width divisions.Tim Northover2016-08-262-2/+33
| | | | llvm-svn: 279841
* GlobalISel: mark selects legalTim Northover2016-08-261-0/+6
| | | | llvm-svn: 279840
* GlobalISel: mark float/int conversions legalTim Northover2016-08-261-0/+14
| | | | llvm-svn: 279839
* [InstCombine] clean up foldICmpAndConstConst(); NFCSanjay Patel2016-08-261-172/+166
| | | | | | | | 1. Early exit to reduce indent 2. Fix comments and variable names to match 3. Reformat comments / clang-format code llvm-svn: 279837
* Missed a semicolon in r279835Krzysztof Parzyszek2016-08-261-1/+1
| | | | llvm-svn: 279836
* Add some more detailed debugging information in RegisterCoalescerKrzysztof Parzyszek2016-08-261-5/+19
| | | | llvm-svn: 279835
* [InstCombine] add helper function for folding of icmp (and X, C2), C; NFCSanjay Patel2016-08-262-6/+21
| | | | llvm-svn: 279834
* limit the number of instructions per block examined by dead store eliminationBob Haarman2016-08-262-8/+27
| | | | | | | | | | | | Summary: Dead store elimination gets very expensive when large numbers of instructions need to be analyzed. This patch limits the number of instructions analyzed per store to the value of the memdep-block-scan-limit parameter (which defaults to 100). This resulted in no observed difference in performance of the generated code, and no change in the statistics for the dead store elimination pass, but improved compilation time on some files by more than an order of magnitude. Reviewers: dexonsmith, bruno, george.burgess.iv, dberlin, reames, davidxl Subscribers: davide, chandlerc, dberlin, davidxl, eraman, tejohnson, mbodart, llvm-commits Differential Revision: https://reviews.llvm.org/D15537 llvm-svn: 279833
* [InstCombine] rename variables in foldICmpAndConstant(); NFCSanjay Patel2016-08-261-54/+55
| | | | llvm-svn: 279831
* test commitBob Haarman2016-08-261-1/+0
| | | | llvm-svn: 279830
* [LoopUnroll] Use OptimizationRemarkEmitter directly not via the analysis passAdam Nemet2016-08-262-5/+4
| | | | | | | | | | | | | | | | We can't mark ORE (a function pass) preserved as required by the loop passes because that is how we ensure that the required passes like LazyBFI are all available any time ORE is used. See the new comments in the patch. Instead we use it directly just like the inliner does in D22694. As expected there is some additional overhead after removing the caching provided by analysis passes. The worst case, I measured was LNT/CINT2006_ref/401.bzip2 which regresses by 12%. As before, this only affects -Rpass-with-hotness and not default compilation. llvm-svn: 279829
* [InstCombine] rename variables in foldICmpDivConstant(); NFCSanjay Patel2016-08-261-29/+28
| | | | | | | | | | | Removing the redundant 'CmpRHSV' local variable exposes a bug in the caller foldICmpShrConstant() - it was sending in the div constant instead of the cmp constant. But I have not been able to expose this in a regression test yet - the affected folds all appear to be handled before we ever reach this code. I'll keep trying to find a case as I make changes to allow vector folds in both functions. llvm-svn: 279828
* [lib/LTO] Add an assertion to catch invalid opt levels.Davide Italiano2016-08-261-4/+5
| | | | llvm-svn: 279823
* [AArch64] Avoid materializing constant 1 by using csinc, rather than csel.Chad Rosier2016-08-261-0/+8
| | | | | | | | This is similar to what was done in r261675, but for CSINC rather than CSINV. Differential Revision: https://reviews.llvm.org/D23892 llvm-svn: 279822
* Handle empty functions with debug info in load/store opt passPablo Barrio2016-08-261-1/+1
| | | | | | | | | | | | | | | | | | | | Summary: In fuctions that contained debug info but were empty otherwise, the ARM load/store optimizer could abort. This was because function MergeReturnIntoLDM handled the special case where a Machine Basic BLock is empty by calling MBB.empty(). However, this returns false in presence of debug info, although the function should be considered empty in the eyes of the load/store optimizer. This has been fixed by handling the case where searching through the block finds only debug instructions. Reviewers: rengolin, dexonsmith, llvm-commits, jmolloy Subscribers: t.p.northover, aemerson, rengolin, samparker Differential Revision: https://reviews.llvm.org/D23847 llvm-svn: 279820
* [X86][SSE4A] The EXTRQ/INSERTQ bit extraction/insertion ops should be in the ↵Simon Pilgrim2016-08-261-0/+2
| | | | | | integer domain llvm-svn: 279811
* Implement getRandomBytes() functionEugene Leviant2016-08-262-0/+38
| | | | | | | | | This function allows getting arbitrary sized block of random bytes. Primary motivation is support for --build-id=uuid in lld. Differential revision: https://reviews.llvm.org/D23671 llvm-svn: 279807
* [X86][SSE] Add CMPSS/CMPSD intrinsic scalar load folding support.Craig Topper2016-08-261-0/+4
| | | | llvm-svn: 279806
* Replace subregister uses when processing tied operandsMatt Arsenault2016-08-261-2/+2
| | | | | | | | | | | | | | | | | | | | | This was for some reason skipping operands that are subregisters instead of keeping the same subregister index. v_movreld_b32 expects src0 to be the subregister of the tied super register use/def. e.g. v_movreld_b32 v0, v9, <imp-def, tied3> v[0:3], <imp-use, tied2> v[0:3] was being replaced with v[4:7] = copy v[0:3] v_movreld_b32 v0, v9, <imp-def, tied3> v[4:7], <imp-use, tied2> v[4:7], which really writes to v[0:3] llvm-svn: 279804
* [libFuzzer] simplify a test to make it pass on the botKostya Serebryany2016-08-261-1/+1
| | | | llvm-svn: 279796
* [libFuzzer] make sure we have symbols on fuzzer testsKostya Serebryany2016-08-251-1/+1
| | | | llvm-svn: 279792
* Revert r274613 because it breaks the test suite with AVX512Michael Kuperstein2016-08-252-89/+49
| | | | | | | | | | | | This reverts most of r274613 (AKA r274626) and its follow-ups (r276347, r277289), due to miscompiles in the test suite. The FastISel change was left in, because it apparently fixes an unrelated issue. (Recommit of r279782 which was broken due to a bad merge.) This fixes 4 out of the 5 test failures in PR29112. llvm-svn: 279788
* [libFizzer] rename -print_new_cov_pcs=1 into -print_pcs=1 and make it more ↵Kostya Serebryany2016-08-256-12/+28
| | | | | | useful: print PCs only after the initial corpus has been read and symbolize them llvm-svn: 279787
* Revert r279782 due to debug buildbot breakage.Michael Kuperstein2016-08-252-53/+88
| | | | llvm-svn: 279785
* Revert r274613 because it breaks the test suite with AVX512Michael Kuperstein2016-08-252-88/+53
| | | | | | | | | | This reverts most of r274613 and its follow-ups (r276347, r277289), due to miscompiles in the test suite. The FastISel change was left in, because it apparently fixes an unrelated issue. This fixes 4 out of the 5 test failures in PR29112. llvm-svn: 279782
* [MemCpy] Add comments for r279769Tim Shen2016-08-251-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D23846 llvm-svn: 279778
* ARM: by default don't set the Thumb bit on MachO relocated values.Tim Northover2016-08-251-10/+11
| | | | | | | | | | | | | Its existence is largely historical, apparently we tried to make ARM object files look maybe-almost-possibly runnable by putting our best guess at the actual value into relocated locations. Of course, the real linker then comes along and can completely change things. But it should only be there for word-sized and movw/movt relocations. It can't be encoded in branch relocations, and I've seen it mess up validity calculations twice in the last couple of weeks so the default is clearly problematic. llvm-svn: 279773
* [MemCpy] Check for alias in performMemCpyToMemSetOptzn, instead of the ↵Tim Shen2016-08-251-1/+3
| | | | | | | | | | | | | | | identity of two operands Summary: This fixes pr29105. The reason is that lifetime marks creates new aliasing pointers the original ones, but before this patch aliases were not checked in performMemCpyToMemSetOptzn. Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23846 llvm-svn: 279769
* Reuse an SDLoc throughout a function. NFC.Michael Kuperstein2016-08-251-18/+12
| | | | llvm-svn: 279767
* GlobalISel: add missing type to G_UADDE instructionsTim Northover2016-08-251-5/+4
| | | | llvm-svn: 279762
* GlobalISel: mark overflow bit of overflow ops legal.Tim Northover2016-08-251-1/+4
| | | | | | It's expected this will map to NZCV register class and be properly selectable. llvm-svn: 279761
* GlobalISel: mark simple ops legal even on types < 32-bit.Tim Northover2016-08-251-4/+3
| | | | | | | | The 32-bit variants of these operations don't depend on the bits not being operated on, so they also naturally model operations narrower than the actual register width. llvm-svn: 279760
* GlobalISel: mark pointer constants as legal on AArch64.Tim Northover2016-08-251-0/+2
| | | | llvm-svn: 279759
* GlobalISel: perform multi-step legalizationTim Northover2016-08-253-2/+59
| | | | llvm-svn: 279758
* GlobalISel: mark small extends as legal on AArch64Tim Northover2016-08-251-0/+13
| | | | llvm-svn: 279757
* [X86] 512-bit VPAVG requires AVX512BWMichael Kuperstein2016-08-251-4/+4
| | | | | | | | | Fix VPAVG detection to require AVX512BW, not AVX512F for 512-bit widths, and change associated asserts to assert in the right direction... This fixes PR29111. llvm-svn: 279755
* [X86][SSE] INSERTPS is only combined on v4f32 types. NFCI.Simon Pilgrim2016-08-251-2/+1
| | | | llvm-svn: 279751
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