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* Teach two-address pass to update the "source" map so it doesn't perform aEvan Cheng2012-05-181-1/+7
| | | | | | | | | non-profitable commute using outdated info. The test case would still fail because of poor pre-RA schedule. That will be fixed by MI scheduler. rdar://11472010 llvm-svn: 157038
* Clarify comment.Eric Christopher2012-05-181-1/+1
| | | | llvm-svn: 157033
* fix corner case in ConstantRange::intersectWith().Nuno Lopes2012-05-181-1/+1
| | | | | | this fixes the missed optimization I was seeing in the CorrelatedValuePropagation pass llvm-svn: 157032
* minor simplification in the call to ConstantRange constructorNuno Lopes2012-05-171-1/+1
| | | | llvm-svn: 157024
* commentsAndrew Trick2012-05-171-2/+3
| | | | llvm-svn: 157020
* Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missingKevin Enderby2012-05-173-11/+54
| | | | | | | | | | the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in the code for better error checking when versions shouldn't be used. rdar://11457025 llvm-svn: 157019
* Remove extraneous ';'.Bill Wendling2012-05-171-1/+1
| | | | llvm-svn: 157011
* misched: trace ReadyQ.Andrew Trick2012-05-171-0/+8
| | | | llvm-svn: 157007
* misched: Added 3-level regpressure back-off.Andrew Trick2012-05-173-75/+288
| | | | | | | | | | | | | | | | | | Introduce the basic strategy for register pressure scheduling. 1) Respect target limits at all times. 2) Indentify critical register classes (pressure sets). Track pressure within the scheduled region. Avoid increasing scheduled pressure for critical registers. 3) Avoid exceeding the max pressure of the region prior to scheduling. Added logic for picking between the top and bottom ready Q's based on regpressure heuristics. Status: functional but needs to be asjusted to achieve good results. llvm-svn: 157006
* commentAndrew Trick2012-05-172-3/+1
| | | | llvm-svn: 157005
* regpressure: Fix getMaxUpwardPressureDelta.Andrew Trick2012-05-171-2/+6
| | | | llvm-svn: 157004
* misched: fix liveness iteratorsAndrew Trick2012-05-171-10/+16
| | | | llvm-svn: 157003
* whitespaceAndrew Trick2012-05-172-2/+3
| | | | llvm-svn: 157002
* Never clear <undef> flags on already joined copies.Jakob Stoklund Olesen2012-05-171-4/+6
| | | | | | | | | | | | | | | | | | | | | RegisterCoalescer set <undef> flags on all operands of copy instructions that are scheduled to be removed. This is so they won't affect shrinkToUses() by introducing false register reads. Make sure those <undef> flags are never cleared, or shrinkToUses() could cause live intervals to end at instructions about to be deleted. This would be a lot simpler if RegisterCoalescer could just erase joined copies immediately instead of keeping all the to-be-deleted instructions around. This fixes PR12862. Unfortunately, bugpoint can't create a sane test case for this. Like many other coalescer problems, this failure depends of a very fragile series of events. <rdar://problem/11474428> llvm-svn: 157001
* Fix a verifier bug.Jakob Stoklund Olesen2012-05-171-1/+1
| | | | | | Make sure useless (def-only) intervals also get verified. llvm-svn: 157000
* Relax the requirement that the exception object must be an instruction. DuringBill Wendling2012-05-171-6/+6
| | | | | | bugpoint-ing, it may turn into something else. llvm-svn: 156998
* enhance the intrinsic info stuff to emit encodings that don't fit in 32-bits ↵Chris Lattner2012-05-171-17/+20
| | | | | | | | | into a separate side table, using the handy SequenceToOffsetTable class. This encodes all these weird things into another 256 bytes, allowing all intrinsics to be encoded this way. llvm-svn: 156995
* Remove incorrect pattern for ARM SMML instruction.Tim Northover2012-05-171-2/+1
| | | | | | Patch by Meador Inge. llvm-svn: 156989
* Fix compile error.Manuel Klimek2012-05-171-1/+1
| | | | llvm-svn: 156986
* SelectionDAGBuilder: CaseBlock, CaseRanges and CaseCmp changed ↵Stepan Dyatkovskiy2012-05-172-10/+11
| | | | | | representation of Low and High from signed to unsigned. Since unsigned ints usually simpler, faster and allows to reduce some extra signed bit checks needed before <,>,<=,>= comparisons. llvm-svn: 156985
* Genericize the intrinsics descriptor decoding a bit to make room Chris Lattner2012-05-171-20/+25
| | | | | | for future expansion, no functionality change yet though. llvm-svn: 156979
* finish encoding all of the interesting details of intrinsics. Now intrinsicsChris Lattner2012-05-171-3/+25
| | | | | | | are only rejected because they can't be encoded into a 32-bit unit, not because they contain an unencodable feature. llvm-svn: 156978
* strengthen the intrinsic descriptor stuff to be able to handle sin, cos and ↵Chris Lattner2012-05-171-10/+21
| | | | | | | | other intrinsics that use passed-in arguments. llvm-svn: 156977
* This patch adds the register class for MIPS16 as well as the ability forAkira Hatanaka2012-05-165-11/+26
| | | | | | | | | | | | | | | llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the mips16 ASE for mips32 by default. As part of fixing of adding this we discovered some small changes that need to be made to MipsInstrInfo::storeRegToStackSLot and MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead, per suggestion of Jakob Stoklund Olesen. Patch by Reed Kotler. llvm-svn: 156958
* Set sub-register <undef> flags more accurately.Jakob Stoklund Olesen2012-05-161-7/+11
| | | | | | | | | | | | | | | When widening an existing <def,reads-undef> operand to a super-register, it may be necessary to clear the <undef> flag because the wider register is now read-modify-write through the instruction. Conversely, it may be necessary to add an <undef> flag when the coalescer turns a full-register def into a sub-register def, but the larger register wasn't live before the instruction. This happens in test/CodeGen/ARM/coalesce-subregs.ll, but the test is too small for the <undef> flags to affect the generated code. llvm-svn: 156951
* Added LLIMCJITMemoryManager to the lli. This manager will be used for MCJIT ↵Danil Malyshev2012-05-161-2/+2
| | | | | | | | instead of DefaultJIMMemoryManager. It's more flexible for MCJIT tasks, in addition it's provides a invalidation instruction cache for code sections which will be used before JIT code will be executed. llvm-svn: 156933
* Hexagon: Remove unused command line option.Benjamin Kramer2012-05-161-2/+0
| | | | llvm-svn: 156917
* Fix a thinko in DisintegrateMERGE_VALUES. Patch by Xiaoyi Guo.Duncan Sands2012-05-162-2/+2
| | | | llvm-svn: 156909
* Significantly reduce the compiled size of Functions.cpp by turning a big ↵Chris Lattner2012-05-161-6/+44
| | | | | | | | | | blob of tblgen generated code (for Intrinsic::getType) into a table. This handles common cases right now, but I plan to extend it to handle all cases and merge in type verification logic as well in follow-on patches. llvm-svn: 156905
* Avoid creating a cycle when folding load / op with flag / store. PR11451474. ↵Evan Cheng2012-05-161-0/+14
| | | | | | rdar://11451474 llvm-svn: 156896
* Enable sub-sub-register copy coalescing.Jakob Stoklund Olesen2012-05-151-9/+0
| | | | | | | | | | | | | | | | It is now possible to coalesce weird skewed sub-register copies by picking a super-register class larger than both original registers. The included test case produces code like this: vld2.32 {d16, d17, d18, d19}, [r0]! vst2.32 {d18, d19, d20, d21}, [r0] We still perform interference checking as if it were a normal full copy join, so this is still quite conservative. In particular, the f1 and f2 functions in the included test case still have remaining copies because of false interference. llvm-svn: 156878
* Teach RegisterCoalescer to handle symmetric sub-register copies.Jakob Stoklund Olesen2012-05-151-14/+28
| | | | | | | | | | | | | It is possible to coalesce two overlapping registers to a common super-register that it larger than both of the original registers. The important difference is that it may be necessary to rewrite DstReg operands as well as SrcReg operands because the sub-register index has changed. This behavior is still disabled by CoalescerPair. llvm-svn: 156869
* Handle NewReg==OldReg in renameRegister().Jakob Stoklund Olesen2012-05-151-1/+2
| | | | | | | This can happen when widening a virtual register to a super-register class. llvm-svn: 156867
* We never call adjustCopiesBackFrom() for partial copies.Jakob Stoklund Olesen2012-05-151-1/+3
| | | | | | There is no need to look at an always null SrcIdx. llvm-svn: 156866
* reuse the result of some expensive computations in getSignExtendExpr() and ↵Nuno Lopes2012-05-151-18/+20
| | | | | | | | getZeroExtendExpr() this gives a speedup of > 80 in a debug build in the test case of PR12825 (php_sha512_crypt_r) llvm-svn: 156849
* Extend the CoalescerPair interface to handle symmetric sub-register copies.Jakob Stoklund Olesen2012-05-152-44/+51
| | | | | | | | | | Now both SrcReg and DstReg can be sub-registers of the final coalesced register. CoalescerPair::setRegisters still rejects such copies because RegisterCoalescer doesn't yet handle them. llvm-svn: 156848
* Add -enable-aa-sched-mi, off by default, for AliasAnalysis inside ↵Andrew Trick2012-05-151-22/+243
| | | | | | | | | | | | | | | MachineScheduler. This feature avoids creating edges in the scheduler's dependence graph for non-aliasing memory operations according to whichever alias analysis is available. It has been fully tested in Hexagon. Before making this default, it needs to be extended to handle multiple MachineMemOperands, compile time needs more evaluation, and benchmarking on X86 and ARM is needed. Patch by Sergei Larin! llvm-svn: 156842
* Allow MCCodeEmitter access to the target MCRegisterInfo.Jim Grosbach2012-05-1511-5/+24
| | | | | | | | Add the MCRegisterInfo to the factories and constructors. Patch by Tom Stellard <Tom.Stellard@amd.com>. llvm-svn: 156828
* minor simplification to code: Ty is already a SCEV type; don't need to run ↵Nuno Lopes2012-05-151-6/+3
| | | | | | getEffectiveSCEVType() twice llvm-svn: 156823
* Teach SimplifyLibCalls about stpcpy.David Majnemer2012-05-151-7/+54
| | | | llvm-svn: 156815
* Rejected r156804 due to buildbots failures.Stepan Dyatkovskiy2012-05-151-35/+46
| | | | llvm-svn: 156808
* SelectionDAGBuilder::Clusterify : main functinality was replaced with ↵Stepan Dyatkovskiy2012-05-151-46/+35
| | | | | | CRSBuilder::optimize, so big part of Clusterify's code was reduced. llvm-svn: 156804
* Temporarily disable anti-dependence breaking for Mips until bug 12829 isAkira Hatanaka2012-05-151-1/+1
| | | | | | resolved. llvm-svn: 156801
* Remove extraneous ';'.Bill Wendling2012-05-151-1/+1
| | | | llvm-svn: 156791
* Add a command line option to skip the delay slot filler pass entirely for Mips.Akira Hatanaka2012-05-141-0/+10
| | | | | | | | | | The purpose of this option is to silence error messages issued by machine verifier passes and enable them to run to the end. If this option is not provided, -verify-machineinstrs complains when it discovers there is a non-terminator instruction (an instruction that is in a delay slot) after the first terminator in a basic block. llvm-svn: 156790
* [Support/YAMLParser] Use rtrim on plain scalars.Michael J. Spencer2012-05-141-3/+1
| | | | llvm-svn: 156787
* Fix use of uninitialized variable.David Blaikie2012-05-141-1/+1
| | | | | | Found by GCC's maybe-uninitialized. llvm-svn: 156780
* Don't access MO reference after invalidating operand list.Jakob Stoklund Olesen2012-05-141-2/+3
| | | | | | This should unbreak llvm-x86_64-linux. llvm-svn: 156778
* Fix PR12821.Jakob Stoklund Olesen2012-05-141-0/+6
| | | | | | | RAFast must add an <imp-def> operand when it is rewriting a sub-register def that isn't a read-modify-write. llvm-svn: 156777
* Move the capture analysis from MemoryDependencyAnalysis to a more general placeChad Rosier2012-05-143-86/+93
| | | | | | | | | so that it can be reused in MemCpyOptimizer. This analysis is needed to remove an unnecessary memcpy when returning a struct into a local variable. rdar://11341081 PR12686 llvm-svn: 156776
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