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* AMDGPU: Expand setcc for v2f32 and v4f32Konstantin Zhuravlyov2017-10-031-0/+1
| | | | llvm-svn: 314853
* AMDGPU: Expand setcc for v2i32 and v4i32Konstantin Zhuravlyov2017-10-031-0/+1
| | | | llvm-svn: 314852
* AMDGPU: Add ELFOSABI_AMDGPU_MESA3DKonstantin Zhuravlyov2017-10-031-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D38387 llvm-svn: 314846
* [X86] Remove dead declaration convertArgMovsToPushes, NFCReid Kleckner2017-10-031-9/+0
| | | | | | | | This was dead when it landed in r252578. We have this functionality, if not for stack probe calls, but for regular calls in X86CallFrameOptimization.cpp. llvm-svn: 314845
* Pre-compute the tail of the archiveRafael Espindola2017-10-031-177/+184
| | | | | | | | | | | | | | | | | | | | | | | | An archive looks like <header> <symbol table> <tail> The symbol table refers to offsets in the tail. A complication is that we would like to support symbol tables that use 64 bit offsets if it turns out that any of the offsets is too big. This patch changes the archive writer to first compute the tail. We cannot just compute one big StringRef since that would require reading every member upfront, but we can represent it as a series of StringRefs. Having done that it is much easier to compute the symbol table and all offsets are computed before it is written. With this if there is an accounting problem it will show up with a regular symbol table, not just when a 64 bit one is needed. llvm-svn: 314844
* AMDGPU: Add ELFOSABI_AMDGPU_PALKonstantin Zhuravlyov2017-10-031-2/+3
| | | | llvm-svn: 314843
* Refactor DIBuilder dbg intrinsic insertion, NFCReid Kleckner2017-10-031-58/+57
| | | | | | | Both dbg.declare and dbg.value insertion had duplicate code for the two overloads with different insertion point conventions. llvm-svn: 314839
* [MachineOutliner] Fix off-by-one in cost modelJessica Paquette2017-10-031-35/+36
| | | | | | | | | | This commit does two things. Firstly, it cleans up some of the benefit calculation wrt outlined functions and candidates. Secondly, it fixes an off-by-one bug in the cost model which was caused by the benefit value of an OutlinedFunction and Candidate differing by 1. It updates the remarks test to reflect this change. llvm-svn: 314836
* [PowerPC] Revert P9 scheduling model to incompleteStefan Pintilie2017-10-031-1/+1
| | | | | | | Partially revert a previous change from commit: https://llvm.org/svn/llvm-project/llvm/trunk@314026 The previous change caused regressions on Power 9. llvm-svn: 314835
* [InstCombine] Use isSignBitCheck to simplify an if statement. Directly ↵Craig Topper2017-10-031-12/+8
| | | | | | | | create new sign bit compares instead of manipulating the constant. NFCI Since we no longer had the direct constant compares, manipulating the constant seemeded less clear. llvm-svn: 314830
* [AMDGPU] implemented pal metadataTim Renouf2017-10-036-3/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: For the amdpal OS type: We write an AMDGPU_PAL_METADATA record in the .note section in the ELF (or as an assembler directive). It contains key=value pairs of 32 bit ints. It is a merge of metadata from codegen of the shaders, and metadata provided by the frontend as _amdgpu_pal_metadata IR metadata. Where both sources have a key=value with the same key, the two values are ORed together. This .note record is part of the amdpal ABI and will be documented in docs/AMDGPUUsage.rst in a future commit. Eventually the amdpal OS type will stop generating the .AMDGPU.config section once the frontend has safely moved over to using the .note records above instead of .AMDGPU.config. Reviewers: arsenm, nhaehnle, dstuttard Subscribers: kzhuravl, wdng, yaxunl, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D37753 llvm-svn: 314829
* [AMDGPU] Avoid predicated execution of the basic blocks containing scalarAlexander Timofeev2017-10-031-0/+10
| | | | | | | | instructions. Differential revision: https://reviews.llvm.org/D38293 llvm-svn: 314828
* Fix -Wcovered-switch-default warnings from r314821Hans Wennborg2017-10-031-3/+2
| | | | llvm-svn: 314826
* Revert r314817 "[dwarfdump] Add -lookup option"Hans Wennborg2017-10-032-30/+2
| | | | | | | | | | | | | | | | | The test fails on Linux; see follow-up email on the llvm-commits list. > Add the option to lookup an address in the debug information and print > out the file, function, block and line table details. > > Differential revision: https://reviews.llvm.org/D38409 This also reverts the follow-up r314818: > [test] Fix llvm-dwarfdump/cmdline.test > > Fixes test/tools/llvm-dwarfdump/cmdline.test llvm-svn: 314825
* Revert r314806 "[SLP] Vectorize jumbled memory loads."Hans Wennborg2017-10-032-256/+84
| | | | | | | | | | | | | | | | | | | | | | | | | All the buildbots are red, e.g. http://lab.llvm.org:8011/builders/clang-cmake-aarch64-lld/builds/2436/ > Summary: > This patch tries to vectorize loads of consecutive memory accesses, accessed > in non-consecutive or jumbled way. An earlier attempt was made with patch D26905 > which was reverted back due to some basic issue with representing the 'use mask' of > jumbled accesses. > > This patch fixes the mask representation by recording the 'use mask' in the usertree entry. > > Change-Id: I9fe7f5045f065d84c126fa307ef6ebe0787296df > > Reviewers: mkuper, loladiro, Ayal, zvi, danielcdh > > Reviewed By: Ayal > > Subscribers: hans, mzolotukhin > > Differential Revision: https://reviews.llvm.org/D36130 llvm-svn: 314824
* Implement David Blaikie's suggestion for comparison operatorsReid Kleckner2017-10-031-3/+8
| | | | llvm-svn: 314822
* CodeView: Provide a .def file with the register idsHans Wennborg2017-10-033-143/+130
| | | | | | | | | | | | | | The list of register ids was previously written out in a couple of dirrent places. This puts it in a .def file and also adds a few more registers (e.g. the x87 regs) which should lead to more readable dumps, but I didn't include the whole list since that seems unnecessary. X86_MC::initLLVMToSEHAndCVRegMapping is pretty ugly, but at least it's not relying on magic constants anymore. The TODO of using tablegen still stands. Differential revision: https://reviews.llvm.org/D38480 llvm-svn: 314821
* [DebugInfo] Correctly coalesce DBG_VALUEs that mix direct and indirect valuesReid Kleckner2017-10-031-83/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This should fix a regression introduced by r313786, which switched from MachineInstr::isIndirectDebugValue() to checking if operand 1 is an immediate. I didn't have a test case for it until now. A single UserValue, which approximates a user variable, may have many DBG_VALUE instructions that disagree about whether the variable is in memory or in a virtual register. This will become much more common once we have llvm.dbg.addr, but you can construct such a test case manually today with llvm.dbg.value. Before this change, we would get two UserValues: one for direct and one for indirect DBG_VALUE instructions describing the same variable. If we build separate interval maps for direct and indirect locations, we will end up accidentally coalescing identical DBG_VALUE intervals that need to remain separate because they are broken up by intervals of the opposite direct-ness. Reviewers: aprantl Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D37932 llvm-svn: 314819
* [dwarfdump] Add -lookup optionJonas Devlieghere2017-10-032-2/+30
| | | | | | | | | Add the option to lookup an address in the debug information and print out the file, function, block and line table details. Differential revision: https://reviews.llvm.org/D38409 llvm-svn: 314817
* Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source ↵Geoff Berry2017-10-033-636/+23
| | | | | | | | | | forwarding"" This reverts commit r314729. Another bug has been encountered in an out-of-tree target reported by Quentin. llvm-svn: 314814
* Use sched_getaffinity instead of std::thread::hardware_concurrency.Rafael Espindola2017-10-034-13/+20
| | | | | | | | | | | | | | The issue with std::thread::hardware_concurrency is that it forwards to libc and some implementations (like glibc) don't take thread affinity into consideration. With this change a llvm program that can execute in only 2 cores will use 2 threads, even if the machine has 32 cores. This makes benchmarking a lot easier, but should also help if someone doesn't want to use all cores for compilation for example. llvm-svn: 314809
* Revert the change that accidentally went in r314806.Dehao Chen2017-10-031-4/+0
| | | | llvm-svn: 314807
* [SLP] Vectorize jumbled memory loads.Mohammad Shahid2017-10-032-84/+256
| | | | | | | | | | | | | | | | | | | | | | Summary: This patch tries to vectorize loads of consecutive memory accesses, accessed in non-consecutive or jumbled way. An earlier attempt was made with patch D26905 which was reverted back due to some basic issue with representing the 'use mask' of jumbled accesses. This patch fixes the mask representation by recording the 'use mask' in the usertree entry. Change-Id: I9fe7f5045f065d84c126fa307ef6ebe0787296df Reviewers: mkuper, loladiro, Ayal, zvi, danielcdh Reviewed By: Ayal Subscribers: hans, mzolotukhin Differential Revision: https://reviews.llvm.org/D36130 llvm-svn: 314806
* [ARM] Use table-gen'd assembly operand diags in ARM asm parserOliver Stannard2017-10-033-95/+22
| | | | | | | | | | | | This switches the ARM AsmParser to use assembly operand diagnostics from tablegen, rather than a switch statement on the ARMMatchResultTy. It moves the existing diagnostic strings to tablegen, but adds no new ones, so this is NFC except for one diagnostic string that had an off-by-1 error in the hand-written switch statement. Differential revision: https://reviews.llvm.org/D31607 llvm-svn: 314804
* [ARM, Asm] Use correct source location for register tokensOliver Stannard2017-10-031-3/+3
| | | | | | | | | | | | tryParseRegister advances the lexer, so we need to take copies of the start and end locations of the register operand before calling it. Previously, the caret in the diagnostic pointer to the comma after the r0 operand in the test, rather than the start of the operand. Differential revision: https://reviews.llvm.org/D31537 llvm-svn: 314799
* [mips] Enable spilling and reloading of the dsp register set.Simon Dardis2017-10-033-0/+17
| | | | | | | | | | | The dsp register class is an alias of the gpr register class, so we have to define instructions for spilling and reloading. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D38038 llvm-svn: 314798
* [CGP] Make optimizeMemoryInst capable of handling multiple AddrModesJohn Brawn2017-10-031-20/+154
| | | | | | | | | | | | | Currently optimizeMemoryInst requires that all of the AddrModes it sees are identical. This patch makes it capable of tracking multiple AddrModes, so long as they differ in at most one field. This patch does nothing by itself, but later patches will make use of it to insert or reuse phi or select instructions for the differing fields. Differential Revision: https://reviews.llvm.org/D38278 llvm-svn: 314795
* [CGP] In optimizeMemoryInst handle select similarly to phiJohn Brawn2017-10-031-7/+16
| | | | | | | | | | This lets us optimize away selects that perform the same address computation in two different ways and is also the first step towards being able to handle selects between two different, but compatible, address computations. Differential Revision: https://reviews.llvm.org/D38242 llvm-svn: 314794
* [ARM, Asm] Fix ubsan failure caused by out-of-range enum valueOliver Stannard2017-10-031-2/+2
| | | | | | | | In this code, we use ~0U as a sentinel value for any operand class that doesn't have a user-friendly error message, but this value isn't in range of the MatchClassKind enum, so we need to ensure it does not get passed to isSubclass. llvm-svn: 314793
* [X86][SSE] Add support for decoding PACKSS/PACKUS shuffles masks with UNDEFSimon Pilgrim2017-10-031-4/+12
| | | | llvm-svn: 314792
* [ARM, Asm] Remove dead code causing MSan failure.Oliver Stannard2017-10-031-7/+0
| | | | | | | r314779 caused ErrorInfo to be red uninitialised, but also made this code dead, so it can just be removed. llvm-svn: 314791
* [X86][SSE] Add support for lowering shuffles to PACKSS/PACKUSSimon Pilgrim2017-10-031-0/+53
| | | | | | | | | | If the upper bits of a truncation shuffle patterns have at least the minimum number of sign/zero bits on their inputs then we can safely use PACKSS/PACKUS as shuffles. Partial fix for https://bugs.llvm.org/show_bug.cgi?id=34773 Differential Revision: https://reviews.llvm.org/D38472 llvm-svn: 314788
* [InlineCost, NFC] Extract code dealing with inbounds GEPs from ↵Evgeny Astigeevich2017-10-031-29/+24
| | | | | | | | | | | | | visitGetElementPtr into a function The code responsible for analysis of inbounds GEPs is extracted into a separate function: CallAnalyzer::canFoldInboundsGEP. With the patch SROA enabling/disabling code is localized at one place instead of spreading across the code of CallAnalyzer::visitGetElementPtr. Differential Revision: https://reviews.llvm.org/D38233 llvm-svn: 314787
* [WebAssembly] MC: Support for init_array and fini_arraySam Clegg2017-10-031-3/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D37757 llvm-svn: 314783
* [DebugInfo] Handle endianness when moving debug info for split integer ↵Bjorn Pettersson2017-10-031-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | values (reapplied) Summary: Take the target's endianness into account when splitting the debug information in DAGTypeLegalizer::SetExpandedInteger. This patch fixes so that, for big-endian targets, the fragment expression corresponding to the high part of a split integer value is placed at offset 0, in order to correctly represent the memory address order. I have attached a PPC32 reproducer where the resulting DWARF pieces for a 64-bit integer were incorrectly reversed. Original patch was reverted due to using -stop-after=isel in the test case (but that is only working when AMDGPU target is included in the llc build). The test case has now been updated to use -stop-before=expand-isel-pseudos instead. Patch by: dstenb Reviewers: JDevlieghere, aprantl, dblaikie Reviewed By: JDevlieghere, aprantl, dblaikie Subscribers: nemanjai Differential Revision: https://reviews.llvm.org/D38172 llvm-svn: 314781
* [ARM] Use new assembler diags for ARMOliver Stannard2017-10-032-133/+289
| | | | | | | | | | | | | | | This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 llvm-svn: 314779
* Remove unused variable. NFCI.Simon Pilgrim2017-10-031-1/+0
| | | | llvm-svn: 314778
* [X86][SSE] Add support for shuffle combining from PACKSS/PACKUSSimon Pilgrim2017-10-031-0/+4
| | | | | | Mentioned in D38472 llvm-svn: 314777
* [X86][SSE] Add support for PACKSS/PACKUS constant foldingSimon Pilgrim2017-10-031-0/+85
| | | | | | Pulled out of D38472 llvm-svn: 314776
* [MiSched] - Simplify ProcResEntry accessJaved Absar2017-10-031-6/+8
| | | | | | | Reviewed by: @MatzeB Differential Revision: https://reviews.llvm.org/D38447 llvm-svn: 314775
* ISel type legalization: add debug messages. NFCI.Sjoerd Meijer2017-10-032-168/+197
| | | | | | | | | | This adds some more debug messages to the type legalizer and functions like PromoteNode, ExpandNode, ExpandLibCall in an attempt to make the debug messages a little bit more informative and useful. Differential Revision: https://reviews.llvm.org/D38450 llvm-svn: 314773
* [RISCV] Parse RISC-V eflags in ObjectYAMLAlex Bradbury2017-10-031-0/+8
| | | | | | | Differential Revision: https://reviews.llvm.org/D38311 Patch by Chih-Mao Chen. llvm-svn: 314770
* [trivial] fix format, NFCHiroshi Inoue2017-10-031-1/+1
| | | | llvm-svn: 314769
* [ObjectYAML] Handle SHF_COMPRESSEDShoaib Meenai2017-10-031-0/+1
| | | | | | | | | This was previously being silently dropped by obj2yaml and caused parsing errors with yaml2obj. Differential Revision: https://reviews.llvm.org/D38490 llvm-svn: 314768
* [X86] Provide the LSDA pointer with RIP relative addressing if necessaryMartin Storsjo2017-10-032-5/+7
| | | | | | | | | | | | | This makes sure the LSDA pointer isn't truncated to 32 bit. Make LowerINTRINSIC_WO_CHAIN a member function instead of a static function, so that it can use the getGlobalWrapperKind method. This solves the second half of the issues mentioned in PR34720. Differential Revision: https://reviews.llvm.org/D38343 llvm-svn: 314767
* [Lint] Avoid failed assertion by fetching the proper pointer typeMikael Holmen2017-10-032-11/+19
| | | | | | | | | | | | | | | | | | | | | Summary: When checking if a constant expression is a noop cast we fetched the IntPtrType by doing DL->getIntPtrType(V->getType())). However, there can be cases where V doesn't return a pointer, and then getIntPtrType() triggers an assertion. Now we pass DataLayout to isNoopCast so the method itself can determine what the IntPtrType is. Reviewers: arsenm Reviewed By: arsenm Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D37894 llvm-svn: 314763
* [InstCombine] Change a bunch of methods to take APInts by reference instead ↵Craig Topper2017-10-032-134/+134
| | | | | | | | of pointer. This allows us to remove a bunch of dereferences and only have a few dereferences at the call sites. llvm-svn: 314762
* [InstCombine] Replace an equality compare of two APInt pointers with a ↵Craig Topper2017-10-031-1/+1
| | | | | | | | compare of the APInts themselves. Apparently this works by virtue of the fact that the pointers are pointers to the APInts stored inside of the ConstantInt objects. But I really don't think we should be relying on that. llvm-svn: 314761
* [Legalizer] Add support for G_OR NarrowScalar.Quentin Colombet2017-10-032-0/+45
| | | | | | | | | | | | | | Legalize bitwise OR: A = BinOp<Ty> B, C into: B1, ..., BN = G_UNMERGE_VALUES B C1, ..., CN = G_UNMERGE_VALUES C A1 = BinOp<Ty/N> B1, C2 ... AN = BinOp<Ty/N> BN, CN A = G_MERGE_VALUES A1, ..., AN llvm-svn: 314760
* Rewrite a function so that it doesn't use pointers to pointers. NFC.Rui Ueyama2017-10-031-12/+13
| | | | | | | | Previous code was a bit puzzling because of its use of pointers. In this patch, we pass a vector and its offsets, instead of pointers to vector elements. llvm-svn: 314756
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