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* LTO: Improve error reporting when adding a cache entry.Peter Collingbourne2017-10-031-4/+6
| | | | | | | | Move error handling code next to the code that returns the error, and change the error message in order to distinguish it from a similar error message elsewhere in this file. llvm-svn: 314745
* SparseSolver: Rename getOrInitValueState to getValueState, matching what ↵Daniel Berlin2017-10-031-6/+6
| | | | | | SCCP calls it llvm-svn: 314744
* AMDGPU: Remove global isGCN predicatesMatt Arsenault2017-10-0319-442/+466
| | | | | | | | | | | | | | These are problematic because they apply to everything, and can easily clobber whatever more specific predicate you are trying to add to a function. Currently instructions use SubtargetPredicate/PredicateControl to apply this to patterns applied to an instruction definition, but not to free standing Pats. Add a wrapper around Pat so the special PredicateControls requirements can be appended to the final predicate list like how Mips does it. llvm-svn: 314742
* [InstSimplify] teach SimplifySelectInst() to fold more vector selectsHaicheng Wu2017-10-021-0/+3
| | | | | | | | | | | | Call ConstantFoldSelectInstruction() to fold cases like below select <2 x i1><i1 true, i1 false>, <2 x i8> <i8 0, i8 1>, <2 x i8> <i8 2, i8 3> All operands are constants and the condition has mixed true and false conditions. Differential Revision: https://reviews.llvm.org/D38369 llvm-svn: 314741
* [PassManager] Retire cl::opt that have been set for a while. NFCI.Davide Italiano2017-10-021-33/+21
| | | | llvm-svn: 314740
* [PowerPC] Revert r314666.Tim Shen2017-10-021-7/+2
| | | | | | | | | See https://reviews.llvm.org/D38172. I tried to XFAIL it, but sometimes XPASS triggers the bot. Simply revert it. llvm-svn: 314739
* Template the sparse propagation solver instead of using void pointersDaniel Berlin2017-10-021-18/+31
| | | | | | | | | | | | | | Summary: This avoids using void * as the type of the lattice value and ugly casts needed to make that happen. (If folks want to use references, etc, they can use a reference_wrapper). Reviewers: davide, mssimpso Subscribers: sanjoy, llvm-commits Differential Revision: https://reviews.llvm.org/D38476 llvm-svn: 314734
* Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"Geoff Berry2017-10-023-23/+636
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issues addressed since original review: - Avoid bug in regalloc greedy/machine verifier when forwarding to use in an instruction that re-defines the same virtual register. - Fixed bug when forwarding to use in EarlyClobber instruction slot. - Fixed incorrect forwarding to register definitions that showed up in explicit_uses() iterator (e.g. in INLINEASM). - Moved removal of dead instructions found by LiveIntervals::shrinkToUses() outside of loop iterating over instructions to avoid instructions being deleted while pointed to by iterator. - Fixed ARMLoadStoreOptimizer bug exposed by this change in r311907. - The pass no longer forwards COPYs to physical register uses, since doing so can break code that implicitly relies on the physical register number of the use. - The pass no longer forwards COPYs to undef uses, since doing so can break the machine verifier by creating LiveRanges that don't end on a use (since the undef operand is not considered a use). [MachineCopyPropagation] Extend pass to do COPY source forwarding This change extends MachineCopyPropagation to do COPY source forwarding. This change also extends the MachineCopyPropagation pass to be able to be run during register allocation, after physical registers have been assigned, but before the virtual registers have been re-written, which allows it to remove virtual register COPY LiveIntervals that become dead through the forwarding of all of their uses. llvm-svn: 314729
* Remove trailing whitespace to trigger re-cmakingMichael Liao2017-10-021-1/+1
| | | | llvm-svn: 314728
* [X86][NFC] Add X86CmovConverterPass to the pass registry.Amjad Aboud2017-10-022-5/+20
| | | | | | Differential Revision: https://reviews.llvm.org/D38355 llvm-svn: 314726
* Remove dead file.Michael Liao2017-10-021-1479/+0
| | | | llvm-svn: 314720
* AMDGPU: Fix typosMatt Arsenault2017-10-021-2/+2
| | | | llvm-svn: 314715
* Add support for Myriad ma2x8x series of CPUsWalter Lee2017-10-021-0/+9
| | | | | | | | | | | | Summary: Also add support for some older Myriad CPUs that were missing. Reviewers: jyknight Subscribers: fedor.sergeev Differential Revision: https://reviews.llvm.org/D37552 llvm-svn: 314705
* Move the stripping of invalid debug info from the Verifier to AutoUpgrade.Adrian Prantl2017-10-0210-66/+54
| | | | | | | | | | | | | | | | | | | | | | | | This came out of a recent discussion on llvm-dev (https://reviews.llvm.org/D38042). Currently the Verifier will strip the debug info metadata from a module if it finds the dbeug info to be malformed. This feature is very valuable since it allows us to improve the Verifier by making it stricter without breaking bcompatibility, but arguable the Verifier pass should not be modifying the IR. This patch moves the stripping of broken debug info into AutoUpgrade (UpgradeDebugInfo to be precise), which is a much better location for this since the stripping of malformed (i.e., produced by older, buggy versions of Clang) is a (harsh) form of AutoUpgrade. This change is mostly NFC in nature, the one big difference is the behavior when LLVM module passes are introducing malformed debug info. Prior to this patch, a NoAsserts build would have printed a warning and stripped the debug info, after this patch the Verifier will report a fatal error. I believe this behavior is actually more desirable anyway. Differential Revision: https://reviews.llvm.org/D38184 llvm-svn: 314699
* [InstCombine] remove one-use restriction for icmp (shr exact X, C1), C2 --> ↵Sanjay Patel2017-10-021-6/+6
| | | | | | icmp X, (C2<<C1) llvm-svn: 314698
* Update getMergedLocation to check the instruction type and merge properly.Dehao Chen2017-10-026-30/+54
| | | | | | | | | | | | | | Summary: If the merged instruction is call instruction, we need to set the scope to the closes common scope between 2 locations, otherwise it will cause trouble when the call is getting inlined. Reviewers: dblaikie, aprantl Reviewed By: dblaikie, aprantl Subscribers: llvm-commits, sanjoy Differential Revision: https://reviews.llvm.org/D37877 llvm-svn: 314694
* CodeView symbol dumper: use symbolic names for registersHans Wennborg2017-10-021-4/+7
| | | | | | https://reviews.llvm.org/D38469 llvm-svn: 314690
* Eliminate ftrunc if source is know to be roundedStanislav Mekhanoshin2017-10-021-0/+13
| | | | | | Differential Revision: https://reviews.llvm.org/D38421 llvm-svn: 314688
* [dwarfdump] Add -show-formJonas Devlieghere2017-10-021-1/+1
| | | | | | | | | This enables printing of DWARF form types after the DWARF attribute types. Differential revision: https://reviews.llvm.org/D38459 llvm-svn: 314685
* use range-for-loops; NFCISanjay Patel2017-10-021-9/+8
| | | | llvm-svn: 314676
* [AsmParser] Support GAS's .print directiveCoby Tayree2017-10-021-0/+18
| | | | | | Differential Revision: https://reviews.llvm.org/D38448 llvm-svn: 314674
* remove duplicate comments, reposition related functions; NFCSanjay Patel2017-10-021-56/+49
| | | | llvm-svn: 314669
* [X86][SSE] Fix -Wsign-compare problems introduced in r314658Bjorn Pettersson2017-10-021-4/+4
| | | | | | | | | | | The refactoring in "[X86][SSE] Add createPackShuffleMask helper function. NFCI." resulted in warning when compiling the code (seen in build bots). This patch restores some types from int to unsigned to avoid those warnings. llvm-svn: 314667
* [Debug info] Handle endianness when moving debug info for split integer valuesBjorn Pettersson2017-10-021-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Take the target's endianness into account when splitting the debug information in DAGTypeLegalizer::SetExpandedInteger. This patch fixes so that, for big-endian targets, the fragment expression corresponding to the high part of a split integer value is placed at offset 0, in order to correctly represent the memory address order. I have attached a PPC32 reproducer where the resulting DWARF pieces for a 64-bit integer were incorrectly reversed. Patch by: dstenb Reviewers: JDevlieghere, aprantl, dblaikie Reviewed By: JDevlieghere, aprantl, dblaikie Subscribers: nemanjai Differential Revision: https://reviews.llvm.org/D38172 llvm-svn: 314666
* [X86][SSE] Add createPackShuffleMask helper function. NFCI.Simon Pilgrim2017-10-021-10/+19
| | | | llvm-svn: 314658
* [X86][SSE] matchBinaryVectorShuffle - add support for different src/dst ↵Simon Pilgrim2017-10-021-12/+12
| | | | | | | | value shuffle types Preparation for support for combining to PACKSS/PACKUS llvm-svn: 314656
* [PowerPC] support ZERO_EXTEND in tryBitPermutationHiroshi Inoue2017-10-021-17/+64
| | | | | | | | | | | | | | | | | | | This patch add a support of ISD::ZERO_EXTEND in PPCDAGToDAGISel::tryBitPermutation to increase the opportunity to use rotate-and-mask by reordering ZEXT and ANDI. Since tryBitPermutation stops analyzing nodes if it hits a ZEXT node while traversing SDNodes, we want to avoid ZEXT between two nodes that can be folded into a rotate-and-mask instruction. For example, we allow these nodes t9: i32 = add t7, Constant:i32<1> t11: i32 = and t9, Constant:i32<255> t12: i64 = zero_extend t11 t14: i64 = shl t12, Constant:i64<2> to be folded into a rotate-and-mask instruction. Such case often happens in array accesses with logical AND operation in the index, e.g. array[i & 0xFF]; Differential Revision: https://reviews.llvm.org/D37514 llvm-svn: 314655
* Fix typo in comment. NFCI.Simon Pilgrim2017-10-021-1/+1
| | | | llvm-svn: 314653
* [X86] Cleanup uses of computeKnownBits by using MaskedValueIsZero helper ↵Simon Pilgrim2017-10-021-6/+3
| | | | | | instead. NFCI. llvm-svn: 314652
* [X86][LLVM]Expanding Supports lowerInterleaved{store|load}() in ↵Michael Zuckerman2017-10-021-109/+169
| | | | | | | | | | | | | | | | | | | X86InterleavedAccess (VF64 stride 3-4) I continue to support different VF interleaved and in this pass for this patch, I added the vf64 stride3 support for both load and store. I also added support fot the stride4 store. Reviewers: 1. zvi 2. dorit 3. igorb 4. guyblank Differential Revision: https://reviews.llvm.org/D37687 Change-Id: I3d238efedf217d1768b348d710de1efa2f19d27b llvm-svn: 314651
* [X86] Fix copy pasto in X86FastISel::fastEmitInst_rrrr.Craig Topper2017-10-021-1/+1
| | | | | | The 4th operand was not being constrained and the third operand was being constrained twice. llvm-svn: 314648
* [X86] Use a bool flag instead of assigning an unsigned to two different ↵Craig Topper2017-10-021-9/+8
| | | | | | values that we only use in an equality comparison. llvm-svn: 314647
* [X86] Use _NOREX MOVZX instructions for some patterns even in 32-bit mode.Craig Topper2017-10-021-32/+6
| | | | | | This unifies the patterns between both modes. This should be effectively NFC since all the available registers in 32-bit mode statisfy this constraint. llvm-svn: 314643
* [Hexagon] Check vector elements for equivalence in the ↵Ron Lieberman2017-10-021-1/+16
| | | | | | | | | | | | | HexagonVectorLoopCarriedReuse pass If the two instructions being compared for equivalence have corresponding operands that are integer constants, then check their values to determine equivalence. Patch by Suyog Sarda! llvm-svn: 314642
* [Hexagon] Patch to Extract i1 element from vector of i1Ron Lieberman2017-10-021-1/+7
| | | | | | | This patch extracts 1 element from vector consisting of elements of size 1 bit at given index. llvm-svn: 314641
* [InstCombine] Use APInt for all the math in foldICmpDivConstantCraig Topper2017-10-011-95/+46
| | | | | | | | | | | | | | Summary: This currently uses ConstantExpr to do its math, but as noted in a TODO it can all be done directly on APInt. Reviewers: spatel, majnemer Reviewed By: majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38440 llvm-svn: 314640
* [X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMemCraig Topper2017-10-018-34/+33
| | | | | | | | | | | | | | | | | | | Summary: Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable. For the register&register form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register&register form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem. I believe this supercedes D38025 which was trying to switch the register&register form back to pre-PR22995. Reviewers: aymanmus, RKSimon, zvi Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38120 llvm-svn: 314639
* [X86] Remove a couple unnecessary COPY_TO_REGCLASS from some output patterns ↵Craig Topper2017-10-011-9/+7
| | | | | | where the instruction already produces the correct register class. llvm-svn: 314638
* [X86][SSE] Add faux shuffle combining support for PACKUSSimon Pilgrim2017-10-011-4/+15
| | | | llvm-svn: 314631
* [X86][SSE] Improve shuffle combining of PACKSS instructions.Simon Pilgrim2017-10-011-6/+24
| | | | | | Support unary packing and fix the faux shuffle mask for vectors larger than 128 bits. llvm-svn: 314629
* [x86] formatting; NFCSanjay Patel2017-10-011-4/+2
| | | | llvm-svn: 314627
* Revert r314579: "Recommi r314561 after fixing over-debug assertion".Daniel Jasper2017-10-012-225/+0
| | | | | | | | | | | | And follow-up r314585. Leads to segfaults. I'll forward reproduction instructions to the patch author. Also, for a recommit, still add the original patch description. Otherwise, it becomes really tedious to find out what a patch actually does. The fact that it is a recommit with a fix is somewhat secondary. llvm-svn: 314622
* Separate the logic when handling indirect calls in SamplePGO ThinLTO compile ↵Dehao Chen2017-10-012-13/+28
| | | | | | | | | | | | | | | | phase and other phases. Summary: In SamplePGO ThinLTO compile phase, we will not invoke ICP as it may introduce confusion to the 2nd annotation. This patch extracted that logic and makes it clearer before profile annotation. In the mean time, we need to make function importing process both inlined callsites as well as not promoted indirect callsites. Reviewers: tejohnson Reviewed By: tejohnson Subscribers: sanjoy, mehdi_amini, llvm-commits, inglorion Differential Revision: https://reviews.llvm.org/D38094 llvm-svn: 314619
* Revert "Fix typo [NFC]"Xin Tong2017-10-011-6/+3
| | | | | | | | This reverts commit e60b5028619be1c81bd039d63a0627dac32d38f9. Incorrectly include changes that are not typo fix. llvm-svn: 314614
* Fix typo [NFC]Xin Tong2017-10-011-3/+6
| | | | llvm-svn: 314613
* NewGVN: Fix PR 34473, by not using ExactlyEqualsExpression for findingDaniel Berlin2017-09-301-6/+6
| | | | | | phi of ops users. llvm-svn: 314612
* NewGVN: Evaluate phi of ops expressions before creating phi nodeDaniel Berlin2017-09-301-48/+72
| | | | llvm-svn: 314611
* NewGVN: Allow dependent PHI of opsDaniel Berlin2017-09-301-57/+100
| | | | llvm-svn: 314610
* NewGVN: Make OpIsSafeForPhiOfOps non-recursiveDaniel Berlin2017-09-301-7/+38
| | | | llvm-svn: 314609
* Refactor the SamplePGO profile annotation logic to extract ↵Dehao Chen2017-09-301-58/+65
| | | | | | inlineCallInstruction. (NFC) llvm-svn: 314601
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