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* Mark the methods in the Mangler const.Rafael Espindola2014-02-101-5/+6
| | | | | | | | | A const ObjectFile needs to be able to provide its name. For an IRObjectFile, that means being able to call the mangler. Since each IRObjectFile can have a different mangling, it is natural for them to contain a Mangler which is therefore also const. llvm-svn: 201113
* Change the begin and end methods in ObjectFile to match the style guide.Rafael Espindola2014-02-109-59/+59
| | | | llvm-svn: 201108
* R600: Implement isTruncateFreeMatt Arsenault2014-02-102-0/+6
| | | | | | | Truncation is just accessing a subregister for any multiple of the register size, so it's free. llvm-svn: 201107
* [LPM] A terribly simple fix to a terribly complex bug: PR18773.Chandler Carruth2014-02-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The crux of the issue is that LCSSA doesn't preserve stateful alias analyses. Before r200067, LICM didn't cause LCSSA to run in the LTO pass manager, where LICM runs essentially without any of the other loop passes. As a consequence the globalmodref-aa pass run before that loop pass manager was able to survive the loop pass manager and be used by DSE to eliminate stores in the function called from the loop body in Adobe-C++/loop_unroll (and similar patterns in other benchmarks). When LICM was taught to preserve LCSSA it had to require it as well. This caused it to be run in the loop pass manager and because it did not preserve AA, the stateful AA was lost. Most of LLVM's AA isn't stateful and so this didn't manifest in most cases. Also, in most cases LCSSA was already running, and so there was no interesting change. The real kicker is that LCSSA by its definition (injecting PHI nodes only) trivially preserves AA! All we need to do is mark it, and then everything goes back to working as intended. It probably was blocking some other weird cases of stateful AA but the only one I have is a 1000-line IR test case from loop_unroll, so I don't really have a good test case here. Hopefully this fixes the regressions on performance that have been seen since that revision. llvm-svn: 201104
* Copy the ThreadLocalMode in GlobalVariable::copyAttributesFromHans Wennborg2014-02-101-1/+1
| | | | | | This fixes the oversight from r159077. llvm-svn: 201098
* R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are usedTom Stellard2014-02-104-10/+28
| | | | | | | | | | | DS instructions that access local memory can only uses addresses that are less than or equal to the value of M0. When M0 is uninitialized, then we experience undefined behavior. This patch also changes the behavior to emit S_WQM_B64 on pixel shaders no matter what kind of DS instruction is used. llvm-svn: 201097
* R600/SI: Only use S_WQM_B64 in pixel shadersTom Stellard2014-02-101-1/+1
| | | | | | | | This doesn't change any functionality, since we only have two shader types (compute and pixel) that use local memory. We're just changing the logic to match the documentation. llvm-svn: 201096
* Remove some prototype code accidentally committed in r201043David Blaikie2014-02-102-14/+0
| | | | | | Thanks to Chandler for the catch. llvm-svn: 201095
* ARM: use natural LLVM IR for vshll instructionsTim Northover2014-02-103-36/+27
| | | | | | | | Similarly to the vshrn instructions, these are simple zext/sext + trunc operations. Using normal LLVM IR should allow for better code, and more sharing with the AArch64 backend. llvm-svn: 201093
* [AArch64] Handle aliases of conditional branches without b.pred form.Chad Rosier2014-02-101-4/+25
| | | | llvm-svn: 201091
* ARM: r12 is callee-saved for interrupt handlersOliver Stannard2014-02-101-2/+2
| | | | | | | For A- and R-class processors, r12 is not normally callee-saved, but is for interrupt handlers. See AAPCS, 5.3.1.1, "Use of IP by the linker". llvm-svn: 201089
* Make succ_iterator a real random access iterator and clean up a couple of users.Benjamin Kramer2014-02-103-12/+4
| | | | llvm-svn: 201088
* GlobalsModRef: Unify and clean up duplicated pointer analysis code.Benjamin Kramer2014-02-101-21/+12
| | | | llvm-svn: 201087
* ARM: use LLVM IR to represent the vshrn operationTim Northover2014-02-104-14/+17
| | | | | | | | | | vshrn is just the combination of a right shift and a truncate (and the limits on the immediate value actually mean the signedness of the shift doesn't matter). Using that representation allows us to get rid of an ARM-specific intrinsic, share more code with AArch64 and hopefully get better code out of the mid-end optimisers. llvm-svn: 201085
* [mips][msa] Add DLSA instruction.Matheus Almeida2014-02-103-1/+23
| | | | llvm-svn: 201081
* [mips][msa] Make LSA_DESC a parameterizable class.Matheus Almeida2014-02-101-7/+11
| | | | | | | | | This way it's possible to share the instruction's description for LSA and DLSA (to be added). No functional changes. llvm-svn: 201078
* [CMake] LLVMSupport should be responsible to provide system_libs.NAKAMURA Takumi2014-02-101-0/+2
| | | | llvm-svn: 201077
* [asan] support for FreeBSD, LLVM part. patch by Viktor KutuzovKostya Serebryany2014-02-101-2/+7
| | | | llvm-svn: 201067
* AVX-512: Fixed extract_vector_elt for v16i1 and v8i1 vectors.Elena Demikhovsky2014-02-104-10/+12
| | | | llvm-svn: 201066
* Recommit r201059 and r201060 with hopefully a fix for its original failure.Craig Topper2014-02-107-11/+31
| | | | | | | | | | Original commits messages: Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. llvm-svn: 201065
* Revert r201059 and r201060.Bob Wilson2014-02-107-29/+11
| | | | | | | | r201059 appears to cause a crash in a bootstrapped build of clang. Craig isn't available to look at it right now, so I'm reverting it while he investigates. llvm-svn: 201064
* [AArch64]Implement the copy of two FPR8 registers by using FMOVss of two ↵Hao Liu2014-02-101-0/+10
| | | | | | FPR32 registers in copyPhysReg. llvm-svn: 201061
* Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' ↵Craig Topper2014-02-107-11/+29
| | | | | | field of modrm byte as a don't care value. Will allow for simplification of disassembler code. llvm-svn: 201059
* MCParser: add a single token lookaheadSaleem Abdulrasool2014-02-091-0/+22
| | | | | | | Some of the more complex directive and macro handling for GAS compatibility requires lookahead. Add a single token lookahead in the MCAsmLexer. llvm-svn: 201058
* AsmParser: Simplify code with ArrayRef.Benjamin Kramer2014-02-091-32/+12
| | | | | | No functionality change. llvm-svn: 201055
* AsmParser: Parse (and ignore) nested .macro definitions.Benjamin Kramer2014-02-091-9/+20
| | | | | | | | | This enables a slightly odd feature of gas. The macro is defined when the outermost macro is instantiated. PR18599 llvm-svn: 201045
* Use a consistent argument order in TargetLoweringObjectFile.Rafael Espindola2014-02-0910-64/+57
| | | | | | | | | These methods normally call each other and it is really annoying if the arguments are in different order. The more common rule was that the arguments specific to call are first (GV, Encoding, Suffix) and the auxiliary objects (Mang, TM) come after. This patch changes the exceptions. llvm-svn: 201044
* Fix formatting introduced in r200941David Blaikie2014-02-093-2/+15
| | | | llvm-svn: 201043
* LoopVectorizer: Keep track of conditional store basic blocksArnold Schwaighofer2014-02-081-0/+4
| | | | | | | | | | | | | Before conditional store vectorization/unrolling we had only one vectorized/unrolled basic block. After adding support for conditional store vectorization this will not only be one block but multiple basic blocks. The last block would have the back-edge. I updated the code to use a vector of basic blocks instead of a single basic block and fixed the users to use the last entry in this vector. But, I forgot to add the basic blocks to this vector! Fixes PR18724. llvm-svn: 201028
* Pass the Mangler by reference.Rafael Espindola2014-02-0823-75/+78
| | | | | | | It is never null and it is not used in casts, so there is no reason to use a pointer. This matches how we pass TM. llvm-svn: 201025
* Add LLVM_OVERRIDE to a few declarations.Rafael Espindola2014-02-088-49/+61
| | | | llvm-svn: 201022
* [Constant Hoisting] Fix insertion point for constant materialization.Juergen Ributzka2014-02-081-18/+21
| | | | | | | | | | The bitcast instruction during constant materialization was not placed correcly in the presence of phi nodes. This commit fixes the insertion point to be in the idom instead. This fixes PR18768 llvm-svn: 201009
* [Constant Hoisting] Don't update the use list while traversing it - DOH!Juergen Ributzka2014-02-081-5/+16
| | | | | | | | This fix first traverses the whole use list of the constant expression and keeps track of the instructions that need to be updated. Then perform the fixup afterwards. llvm-svn: 201008
* Remove dead code.Rafael Espindola2014-02-071-4/+0
| | | | llvm-svn: 201006
* Always create a temporary symbol to use with the cfi frame.Rafael Espindola2014-02-071-9/+3
| | | | | | | This is a small simplification and a small step in fixing pr18743 since private functions on MachO should be using a 'l' prefix. llvm-svn: 200994
* Remove -arm-disable-ehabi optionRenato Golin2014-02-072-13/+2
| | | | llvm-svn: 200988
* Don't internalize linkonce_odr non constant variables.Rafael Espindola2014-02-071-0/+8
| | | | llvm-svn: 200983
* Fix an invalid check for duplicate option categories.Alexander Kornienko2014-02-071-4/+10
| | | | | | | An intermediate solution until the problems with analyzer plugins linking with llvm/Support and causing assertions due to duplicate GeneralCategory are solved. llvm-svn: 200981
* [mips] Forbid the use of registers t6, t7 and t8 if the target is NaCl.Sasa Stankovic2014-02-073-2/+17
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D2694 llvm-svn: 200978
* Fix a bug with .weak_def_can_be_hidden: Mutable variables cannot use it.Rafael Espindola2014-02-071-0/+12
| | | | | | Thanks to John McCall for noticing it. llvm-svn: 200977
* Refactor logic into a function predicate.Rafael Espindola2014-02-071-14/+19
| | | | | | No functionality change. llvm-svn: 200976
* Try to unbreak the mingw32 build.Benjamin Kramer2014-02-071-1/+1
| | | | llvm-svn: 200973
* LLVM-1163: AAPCS-VFP violation when CPRC allocated to stackOliver Stannard2014-02-071-4/+5
| | | | | | | | | | | | According to the AAPCS, when a CPRC is allocated to the stack, all other VFP registers should be marked as unavailable. I have also modified the rules for allocating non-CPRCs to the stack, to make it more explicit that all GPRs must be made unavailable. I cannot think of a case where the old version would produce incorrect answers, so there is no test for this. llvm-svn: 200970
* [Sparc] Add support for parsing synthetic instruction 'mov'. Venkatraman Govindaraju2014-02-071-0/+6
| | | | llvm-svn: 200965
* [Sparc] Emit correct encoding for atomic instructions. Also, add support for ↵Venkatraman Govindaraju2014-02-074-12/+32
| | | | | | parsing CAS instructions to test the CAS encoding. llvm-svn: 200963
* [Sparc] Emit relocations for Thread Local Storage (TLS) when integrated ↵Venkatraman Govindaraju2014-02-075-4/+187
| | | | | | assembler is used. llvm-svn: 200962
* [Sparc] Emit correct relocations for PIC code when integrated assembler is used.Venkatraman Govindaraju2014-02-078-43/+139
| | | | llvm-svn: 200961
* [Sparc] Use SparcMCExpr::VariantKind itself as MachineOperand's target flags.Venkatraman Govindaraju2014-02-078-211/+92
| | | | llvm-svn: 200960
* PGO branch weight: fix PR18752.Manman Ren2014-02-071-5/+4
| | | | | | | Fix a bug triggered in IfConverterTriangle when CvtBB has multiple predecessors by getting the weights before removing a successor. llvm-svn: 200958
* X86: Resolve a long standing FIXME and properly isel pextr[bw].Jim Grosbach2014-02-073-18/+4
| | | | | | | | | | | | | | | | | Generalize the AArch64 .td nodes for AssertZext and AssertSext. Use them to match the relevant pextr store instructions. The test widen_load-2.ll requires a slight change because with the stores gone, the remaining instructions are scheduled in a different order. Add test cases for SSE4 and AVX variants. Resolves rdar://13414672. Patch by Adam Nemet <anemet@apple.com>. llvm-svn: 200957
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