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* cleanup: scc_iterator consumers should use isAtEndDuncan P. N. Exon Smith2014-02-044-9/+6
| | | | | | | | | | | | | | No functional change. Updated loops from: for (I = scc_begin(), E = scc_end(); I != E; ++I) to: for (I = scc_begin(); !I.isAtEnd(); ++I) for teh win. llvm-svn: 200789
* [mips] Implement %hi(sym1 - sym2) and %lo(sym1 - sym2) expressionsPetar Jovanovic2014-02-046-4/+184
| | | | | | | | | | | Patch implements %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions for MIPS by creating target expression class MipsMCExpr. Patch by Sasa Stankovic. Differential Revision: http://llvm-reviews.chandlerc.com/D2592 llvm-svn: 200783
* Every target uses .align. Simplify.Rafael Espindola2014-02-043-8/+13
| | | | llvm-svn: 200782
* Use the default values.Rafael Espindola2014-02-046-11/+11
| | | | llvm-svn: 200781
* Fix PR18345: ldr= pseudo instruction produces incorrect code when using in ↵David Peixotto2014-02-046-111/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | inline assembly This patch fixes the ldr-pseudo implementation to work when used in inline assembly. The fix is to move arm assembler constant pools from the ARMAsmParser class to the ARMTargetStreamer class. Previously we kept the assembler generated constant pools in the ARMAsmParser object. This does not work for inline assembly because a new parser object is created for each blob of inline assembly. This patch moves the constant pools to the ARMTargetStreamer class so that the constant pool will remain alive for the entire code generation process. An ARMTargetStreamer class is now required for the arm backend. There was no existing implementation for MachO, only Asm and ELF. Instead of creating an empty MachO subclass, we decided to make the ARMTargetStreamer a non-abstract class and provide default (llvm_unreachable) implementations for the non constant-pool related methods. Differential Revision: http://llvm-reviews.chandlerc.com/D2638 llvm-svn: 200777
* R600/SI: Expand i1 BR_CCTom Stellard2014-02-041-0/+2
| | | | | | | | | | | This fixes a crashes in the OpenCV test suite and also the scrypt kernel in bfgminer. I was unable to come up with a reduced test case for this. https://bugs.freedesktop.org/show_bug.cgi?id=72785 llvm-svn: 200776
* R600/SI: Don't assume copies will be coalesced in SIFixSGPRCopiesTom Stellard2014-02-041-1/+1
| | | | | | | There is no lit test for this, because it would be too big and complicated, but it does fix a crash in the Arithm/Absdiff.* OpenCV test. llvm-svn: 200775
* R600/SI: Custom lower i64 ISD::SELECTTom Stellard2014-02-042-0/+28
| | | | llvm-svn: 200774
* R600: Enable vector fpow.Tom Stellard2014-02-041-0/+1
| | | | | | | | | | | The OpenCL specs say: "The vector versions of the math functions operate component-wise. The description is per-component." Patch by: Jan Vesely Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 200773
* OS X: the correct function is __sincospif_stret, not __sincospi_stretfTim Northover2014-02-042-4/+4
| | | | | | rdar://problem/13729466 llvm-svn: 200771
* ARM & AArch64: merge NEON absolute compare intrinsicsTim Northover2014-02-042-45/+20
| | | | | | | | There was an extremely confusing proliferation of LLVM intrinsics to implement the vacge & vacgt instructions. This combines them all into two polymorphic intrinsics, shared across both backends. llvm-svn: 200768
* Implemented support for Process::GetRandomNumber on Windows.Aaron Ballman2014-02-042-0/+12
| | | | | | Patch thanks to Stephan Tolksdorf! llvm-svn: 200767
* llvm-cov: Implement the preserve-paths flagJustin Bogner2014-02-041-10/+49
| | | | | | | | | | | | | | | | Until now, when a path in a gcno file included a directory, we would emit our .gcov file in that directory, whereas gcov always emits the file in the current directory. In doing so, this implements gcov's strange name-mangling -p flag, which is needed to avoid clobbering files when two with the same name exist in different directories. The path mangling is a bit ugly and only handles unix-like paths, but it's simple, and it doesn't make any guesses as to how it should behave outside of what gcov documents. If we decide this should be cross platform later, we can consider the compatibility implications then. llvm-svn: 200754
* ARM: fix fast-isel assertion failureTim Northover2014-02-041-1/+2
| | | | | | | | | Missing braces on if meant we inserted both ARM and Thumb load for a litpool entry. This didn't end well. rdar://problem/15959157 llvm-svn: 200752
* R600/SI: Fix fneg for 0.0Michel Danzer2014-02-041-4/+18
| | | | | | | | | | | | V_ADD_F32 with source modifier does not produce -0.0 for this. Just manipulate the sign bit directly instead. Also add a pattern for (fneg (fabs ...)). Fixes a bunch of bit encoding piglit tests with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 200743
* RegAllocGreedy.cpp: Use more simple value as Hysteresis, to suppress ↵NAKAMURA Takumi2014-02-041-1/+1
| | | | | | -mfpmath-dependent behavior. llvm-svn: 200738
* Revert: ARM: Enable use of relocation type tlsldo in debug info for tls data.Kai Nacke2014-02-042-9/+0
| | | | | | | There seems to be a new problem with the debug info in the test case. I'll have to investigate this. llvm-svn: 200737
* Add strchr(p, 0) -> p + strlen(p) to SimplifyLibCallsKai Nacke2014-02-041-3/+4
| | | | | | | | Add the missing transformation strchr(p, 0) -> p + strlen(p) to SimplifyLibCalls and remove the ToDo comment. Reviewer: Duncan P.N. Exan Smith llvm-svn: 200736
* ARM: Enable use of relocation type tlsldo in debug info for tls data.Kai Nacke2014-02-042-0/+9
| | | | | | | This fixes PR18554. Reviewers: Renato Golin, Keith Walker llvm-svn: 200735
* DebugInfo: Remove some unneeded conditionals now that DIBuilder no longer ↵David Blaikie2014-02-042-6/+3
| | | | | | | | | | | emits zero-length arrays as {i32 0} A bunch of test cases needed to be cleaned up for this, many my fault - when implementid imported modules I updated test cases by simply duplicating the prior metadata field - which wasn't always the empty metadata entry. llvm-svn: 200731
* Self-memcpy-elision and memcpy of constant byte to memset transforms don't ↵Nick Lewycky2014-02-041-4/+7
| | | | | | care how many bytes you were trying to transfer. Sink that safety test after those transforms. Noticed by inspection. llvm-svn: 200726
* DIBuilder: simplify array generation to produce true zero-length arraysDavid Blaikie2014-02-031-4/+0
| | | | | | | | | | | | For some anachronistic reason we were producing {i32 0} for zero-length debug info arrays. (this change is paired with a Clang change and may cause temporary buildbot noise) Let's not. llvm-svn: 200721
* Add DEBUG_TYPE to SIAnnotateControlFlowMatt Arsenault2014-02-031-0/+2
| | | | llvm-svn: 200720
* inalloca: Don't remove dead arguments in the presence of inalloca argsReid Kleckner2014-02-031-0/+7
| | | | | | | | | | | | It disturbs the layout of the parameters in memory and registers, leading to problems in the backend. The plan for optimizing internal inalloca functions going forward is to essentially SROA the argument memory and demote any captured arguments (things that aren't trivially written by a load or store) to an indirect pointer to a static alloca. llvm-svn: 200717
* AArch64 & ARM: refactor crypto intrinsics to take scalarsTim Northover2014-02-032-18/+54
| | | | | | | | | | | | Some of the SHA instructions take a scalar i32 as one argument (largely because they work on 160-bit hash fragments). This wasn't reflected in the IR previously, with ARM and AArch64 choosing different types (<4 x i32> and <1 x i32> respectively) which was ugly. This makes all the affected intrinsics take a uniform "i32", allowing them to become non-polymorphic at the same time. llvm-svn: 200706
* Expand vector bswap in LegalizeVectorOpsHal Finkel2014-02-031-0/+1
| | | | | | | ISD::BSWAP was missing from the list of node types that should be expanded element-wise. llvm-svn: 200705
* Undef'ing _WIN32_IE to silence an MSVC warning about redefining a macro value.Aaron Ballman2014-02-031-0/+1
| | | | | | No functional change intended. llvm-svn: 200704
* Rename the non-templated base class of SmallPtrSet toChandler Carruth2014-02-031-13/+15
| | | | | | | | | | | 'SmallPtrSetImplBase'. This more closely matches the organization of SmallVector and should allow introducing a SmallPtrSetImpl which serves the same purpose as SmallVectorImpl: isolating the element type from the particular small size chosen. This in turn allows a lot of simplification of APIs by not coding them against a specific small size which is rarely needed. llvm-svn: 200687
* Remove unnecessary include of AArch64GenInstrInfo.inc from ↵Craig Topper2014-02-031-1/+0
| | | | | | AArch64Disassembler.cpp. None of the GET_ defines were set that would make the include do anything. llvm-svn: 200677
* Lower llvm.expect intrinsic correctly for i1Duncan P. N. Exon Smith2014-02-021-5/+18
| | | | | | | | | | LowerExpectIntrinsic previously only understood the idiom of an expect intrinsic followed by a comparison with zero. For llvm.expect.i1, the comparison would be stripped by the early-cse pass. Patch by Daniel Micay. llvm-svn: 200664
* Unaligned access is supported on ARMv6 and ARMv7 for the NetBSD target.Joerg Sonnenberger2014-02-022-3/+7
| | | | | | Patch from Matt Thomas. llvm-svn: 200654
* Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ↵Craig Topper2014-02-0213-499/+498
| | | | | | meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
* Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field ↵Craig Topper2014-02-026-143/+171
| | | | | | in TSFlags. llvm-svn: 200624
* Replace PPC instruction-size code with MCInstrDesc getSizeHal Finkel2014-02-022-20/+11
| | | | | | | | | | As part of the cleanup done to enable the disassembler, the PPC instructions now have a valid Size description field. This can now be used to replace some custom logic in a few places to compute instruction sizes. Patch by David Wiberg! llvm-svn: 200623
* LoopVectorizer: Enable unrolling of conditional stores and the load/storeArnold Schwaighofer2014-02-021-3/+3
| | | | | | | | | unrolling heuristic per default Benchmarking on x86_64 (thanks Chandler!) and ARM has shown those options speed up some benchmarks while not causing any interesting regressions. llvm-svn: 200621
* R600/SI: Fix insertelement with dynamic indices.Matt Arsenault2014-02-021-7/+17
| | | | | | | | This didn't work for any integer vectors, and didn't work with some sizes of float vectors. This should now work with all sizes of float and i32 vectors. llvm-svn: 200619
* [Sparc] Set %o7 as the return address register instead of %i7 in ↵Venkatraman Govindaraju2014-02-012-4/+23
| | | | | | MCRegisterInfo. Also, add CFI instructions to initialize the frame correctly. llvm-svn: 200617
* ARMTTI: We don't have 16 allocatable scalar registersArnold Schwaighofer2014-02-011-1/+1
| | | | | | | This caused an regression on libquantum after enabling the new loop vectorizer unroll heuristics. llvm-svn: 200616
* MC: Fix .octa output for APInts with BitWidth > 128David Woodhouse2014-02-011-1/+2
| | | | llvm-svn: 200615
* MC: Add support for .octaDavid Woodhouse2014-02-011-2/+55
| | | | | | | | | | This is a minimal implementation which accepts only constants rather than full expressions, but that should be perfectly sufficient for all known users for now. Patch from PaX Team <pageexec@freemail.hu> llvm-svn: 200614
* MC: Add AsmLexer::BigNum token for integers greater than 64 bitsDavid Woodhouse2014-02-012-17/+19
| | | | | | | | | | | | | | | | | | | | This will be needed for .octa support, but we don't want to just use the existing AsmLexer::Integer for it and then have to litter all its users with explicit checks for the size, and make them use the new get APIntVal() method. So let the lexer produce an AsmLexer::Integer as before for numbers which are small enough — which appears to cover what was previously a nasty special case handling of numbers which don't fit in int64_t but *do* fit in uint64_t. Where the number is too large even for that, produce an AsmLexer::BigNum instead. We do nothing with these except complain about them for now, but that will be changed shortly... Based on a patch from PaX Team <pageexec@freemail.hu> llvm-svn: 200613
* [LPM] Apply a really big hammer to fix PR18688 by recursively reformingChandler Carruth2014-02-011-5/+18
| | | | | | | | | | | | | | | | | | | | LCSSA when we promote to SSA registers inside of LICM. Currently, this is actually necessary. The promotion logic in LICM uses SSAUpdater which doesn't understand how to place LCSSA PHI nodes. Teaching it to do so would be a very significant undertaking. It may be worthwhile and I've left a FIXME about this in the code as well as starting a thread on llvmdev to try to figure out the right long-term solution. For now, the PR needs to be fixed. Short of using the promition SSAUpdater to place both the LCSSA PHI nodes and the promoted PHI nodes, I don't see a cleaner or cheaper way of achieving this. Fortunately, LCSSA is relatively lazy and sparse -- it should only update instructions which need it. We can also skip the recursive variant when we don't promote to SSA values. llvm-svn: 200612
* Remove some unused #includesEli Bendersky2014-02-012-3/+0
| | | | llvm-svn: 200611
* Silence GCC warnings.Benjamin Kramer2014-02-011-4/+3
| | | | llvm-svn: 200610
* [inliner] Skip debug intrinsics even earlier in computing the inlineChandler Carruth2014-02-011-0/+10
| | | | | | | | | | | | | | | | | | | | | | | cost so that they don't impact the vector bonus. Fundamentally, counting unsimplified instructions is just *wrong*; it will continue to introduce instability as things which do not generate code bizarrely impact inlining. For example, sufficiently nested inlined functions could turn off the vector bonus with lifetime markers just like the debug intrinsics do. =/ This is a short-term tactical fix. Long term, I think we need to remove the vector bonus entirely. That's a separate patch and discussion though. The patch to fix this provided by Dario Domizioli. I've added some comments about the planned direction and used a heavily pruned form of debug info intrinsics for the test case. While this debug info doesn't work or "do" anything useful, it lets us easily test all manner of interference easily, and I suspect this will not be the last time we want to craft a pattern where debug info interferes with the inliner in a problematic way. llvm-svn: 200609
* Simplify some x86 format classes and remove some ambiguities in their ↵Craig Topper2014-02-013-43/+46
| | | | | | application. llvm-svn: 200608
* MC: Improve the .fill directive's compatibility with GASDavid Majnemer2014-02-012-14/+57
| | | | | | | | | Per the GAS documentation, .fill should permit pattern widths that aren't a power of two. While I was in the neighborhood, I added some sanity checking. This change was motivated by a use of this construct in the Linux Kernel. llvm-svn: 200606
* Hopefully fix mingw32 bots.Peter Collingbourne2014-02-011-1/+1
| | | | | | For some reason this symbolic constant isn't defined in some versions of mingw32. llvm-svn: 200605
* Revert "[SLPV] Recognize vectorizable intrinsics during SLP vectorization ..."Reid Kleckner2014-02-011-86/+3
| | | | | | | This reverts commit r200576. It broke 32-bit self-host builds by vectorizing two calls to @llvm.bswap.i64, which we then fail to expand. llvm-svn: 200602
* [stackprotector] Implement the sspstrong rules for stack layout.Josh Magee2014-02-012-0/+22
| | | | | | | | | | | | | | | | | | This changes the PrologueEpilogInserter and LocalStackSlotAllocation passes to follow the extended stack layout rules for sspstrong and sspreq. The sspstrong layout rules are: 1. Large arrays and structures containing large arrays (>= ssp-buffer-size) are closest to the stack protector. 2. Small arrays and structures containing small arrays (< ssp-buffer-size) are 2nd closest to the protector. 3. Variables that have had their address taken are 3rd closest to the protector. Differential Revision: http://llvm-reviews.chandlerc.com/D2546 llvm-svn: 200601
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