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* test commit / whitespaceWill Schmidt2012-10-041-1/+1
| | | | llvm-svn: 165233
* SimplifyCFG: Enhance the "remove CFG edge that leads to null pointer ↵Benjamin Kramer2012-10-041-2/+3
| | | | | | | | | | dereference" optimization to also handle instructions with multiple uses. We conservatively only check the first use to avoid walking long use chains. This catches the common case of having both a load and a store to a pointer supplied by a PHI node. llvm-svn: 165232
* In my recent change to avoid use of underaligned memory I didn't notice thatDuncan Sands2012-10-041-7/+7
| | | | | | | | cpyDest can be mutated in some cases, which would then cause a crash later if indeed the memory was underaligned. This brought down several buildbots, so I guess the underaligned case is much more common than I thought! llvm-svn: 165228
* The alignment of an sret parameter is known: it must be at least theDuncan Sands2012-10-041-5/+14
| | | | | | alignment of the return type. Teach the optimizers this. llvm-svn: 165226
* Hoist some grossly duplicated code from the COFF/ELF/MachO streamers into ↵Benjamin Kramer2012-10-044-126/+25
| | | | | | MCObjectStreamer. llvm-svn: 165225
* Fix PR13969, a mini-phase-ordering issue with the new SROA pass.Chandler Carruth2012-10-041-23/+50
| | | | | | | | | | | | | | | | | | | | | Currently, we re-visit allocas when something changes about the way they might be *split* to allow better scalarization to take place. However, we weren't handling the case when the *promotion* is what would change the behavior of SROA. When an address derived from an alloca is stored into another alloca, we consider the first to have escaped. If the second is ever promoted to an SSA value, we will suddenly be able to run the SROA pass on the first alloca. This patch adds explicit support for this form if iteration. When we detect a store of a pointer derived from an alloca, we flag the underlying alloca for reprocessing after promotion. The logic works hard to only do this when there is definitely going to be promotion and it might remove impediments to the analysis of the alloca. Thanks to Nick for the great test case and Benjamin for some sanity check review. llvm-svn: 165223
* The memcpy optimizer was happily doing call slot forwarding when the new memoryDuncan Sands2012-10-041-4/+30
| | | | | | | | | | was less aligned than the old. In the testcase this results in an overaligned memset: the memset alignment was correct for the original memory but is too much for the new memory. Fix this by either increasing the alignment of the new memory or bailing out if that isn't possible. Should fix the gcc-4.7 self-host buildbot failure. llvm-svn: 165220
* Teach the integer-promotion rewrite strategy to be endianness aware.Chandler Carruth2012-10-041-9/+29
| | | | | | | | | | | | | | | | | | | | | | | Sorry for this being broken so long. =/ As part of this, switch all of the existing tests to be Little Endian, which is the behavior I was asserting in them anyways! Add in a new big-endian test that checks the interesting behavior there. Another part of this is to tighten the rules abotu when we perform the full-integer promotion. This logic now rejects cases where there fully promoted integer is a non-multiple-of-8 bitwidth or cases where the loads or stores touch bits which are in the allocated space of the alloca but are not loaded or stored when accessing the integer. Sadly, these aren't really observable today as the rest of the pass will already ensure the invariants hold. However, the latter situation is likely to become a potential concern in the future. Thanks to Benjamin and Duncan for early review of this patch. I'm still looking into whether there are further endianness issues, please let me know if anyone sees BE failures persisting past this. llvm-svn: 165219
* Use method to query if there are attributes.Bill Wendling2012-10-041-1/+1
| | | | llvm-svn: 165213
* Add method to query for NoCapture attribute.Bill Wendling2012-10-041-0/+16
| | | | llvm-svn: 165212
* Use method to query for NoAlias attribute.Bill Wendling2012-10-041-1/+1
| | | | llvm-svn: 165211
* Use method to query for attributes.Bill Wendling2012-10-043-11/+11
| | | | llvm-svn: 165209
* Add method to query for 'NoAlias' attribute on call/invoke instructions.Bill Wendling2012-10-042-1/+17
| | | | llvm-svn: 165208
* Use method to query for attributes.Bill Wendling2012-10-041-1/+1
| | | | llvm-svn: 165207
* Query for attributes via the correct method call.Bill Wendling2012-10-041-2/+2
| | | | llvm-svn: 165206
* Use new accessor methods to query for attributes.Bill Wendling2012-10-044-4/+4
| | | | llvm-svn: 165205
* [tsan] add 3 internal flags for fine-grain control of what is instrumented ↵Kostya Serebryany2012-10-041-7/+18
| | | | | | and what is not. llvm-svn: 165204
* Remove template from function that is only used with one type after r165092.Craig Topper2012-10-041-4/+5
| | | | llvm-svn: 165203
* Fix reg mask slot test, and preserve LiveIntervals and VirtRegMap in the PBQPLang Hames2012-10-041-1/+3
| | | | | | allocator. Fixes PR13945. llvm-svn: 165201
* Implement methods that enable expansion of load immediate Jack Carter2012-10-043-28/+115
| | | | | | | | | | | | | | | | | | | | | | | | macro instruction (li) in the assembler. We have identified three possible expansions depending on the size of immediate operand: 1) for 0 ≤ j ≤ 65535. li d,j => ori d,$zero,j 2) for −32768 ≤ j < 0. li d,j => addiu d,$zero,j 3) for any other value of j that is representable as a 32-bit integer. li d,j => lui d,hi16(j) ori d,d,lo16(j) All of the above have been implemented in ths patch. Contributer: Vladimir Medic llvm-svn: 165199
* This patch is a partial implementation of mips .set assembler directive. ↵Jack Carter2012-10-041-43/+238
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Directive is defined as follows: .set option The patch implements following options at - lets the assembler use the $at register for macros, but generates warnings if the source program uses $at noat - let source programs use $at without issuingwarnings. noreorder - prevents the assembler from reordering machine language instructions. nomacro - causes the assembler to print a warning whenever an assembler operation generates more than one machine language instruction. macro - lets the assembler generate multiple machine instructions from a single assembler instruction reorder - lets the assembler reorder machine language instructions to improve performance The above variants are parsed and their boolean values set or unset. The code to actually use them will come later. Following options are not implemented yet: nomips16 nomicromips move nomove Contributer: Vladimir Medic llvm-svn: 165194
* tblgen: Whitespace and 80-col cleanup.Sean Silva2012-10-041-11/+12
| | | | llvm-svn: 165190
* Enable -schedmodel, but prefer itineraries until we have more benchmark data.Andrew Trick2012-10-041-52/+51
| | | | llvm-svn: 165188
* Fix PR13967.Jakub Staszak2012-10-031-1/+4
| | | | llvm-svn: 165187
* Clean up tailing whitespacesMichael Liao2012-10-031-2/+2
| | | | llvm-svn: 165182
* [ms-inline asm] Add support in the X86AsmPrinter for printing memory referencesChad Rosier2012-10-032-0/+56
| | | | | | | | | | | in the Intel syntax. The MC layer supports emitting in the Intel syntax, but this would require the inline assembly MachineInstr to be lowered to an MCInst before emission. This is potential future work, but for now emitting directly from the MachineInstr suffices. llvm-svn: 165173
* This patch moves from using a hard coded number (4) Jack Carter2012-10-031-2/+4
| | | | | | | | | | | | | for the number of bytes in a particular instruction to using const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode()); Desc.getSize() This is necessary with the advent of 16 bit instructions with mips16 and micromips. It is also puts Mips in compliance with the other targets for getting instruction size. llvm-svn: 165171
* tblgen: Remove last traces of old TableGenMain API.Sean Silva2012-10-033-36/+1
| | | | llvm-svn: 165168
* tblgen: Put new TableGenMain API in place.Sean Silva2012-10-031-0/+19
| | | | | | | | In order to avoid rev-lock with Clang when moving to the new API, also preserve the current API temporarily and insert a shim to implement the new API in terms of the old. llvm-svn: 165165
* Update to use the predicate methods to query if an attribute exists.Bill Wendling2012-10-031-17/+17
| | | | llvm-svn: 165163
* Fix a cycle in the DAG. In this code we replace multiple loads with a single ↵Nadav Rotem2012-10-031-7/+19
| | | | | | | | | | | load and multiple stores with a single load. We create the wide loads and stores (and their chains) before we remove the scalar loads and stores and fix the DAG chain. We attempted to merge loads with a different chain. When that happened, the assumption that it is safe to RAUW broke and a cycle was introduced. llvm-svn: 165148
* Typos.Chad Rosier2012-10-032-5/+4
| | | | llvm-svn: 165141
* Add methods which query for the specific attribute instead of using theBill Wendling2012-10-033-16/+112
| | | | | | enums. This allows for better encapsulation of the Attributes class. llvm-svn: 165132
* Implement .rel relocation for R_ARM_ABS32 in MCJIT.Tim Northover2012-10-031-2/+10
| | | | | | Patch by Amara Emerson. llvm-svn: 165128
* This Patch corrects a problem whereby the optimization to use a faster dividePreston Gurd2012-10-031-5/+15
| | | | | | | | | | | | | | instruction (for Intel Atom) was not being done by Clang, because the type context used by Clang is not the default context. It fixes the problem by getting the global context types for each div/rem instruction in order to compare them against the types in the BypassTypeMap. Tests for this will be done as a separate patch to Clang. Patch by Tyler Nowicki. llvm-svn: 165126
* A DAGCombine optimization for mergeing consecutive stores to memory. The ↵Nadav Rotem2012-10-031-0/+395
| | | | | | | | | | | | | | | | | | | | | optimization is not profitable in many cases because modern processors perform multiple stores in parallel and merging stores prior to merging requires extra work. We handle two main cases: 1. Store of multiple consecutive constants: q->a = 3; q->4 = 5; In this case we store a single legal wide integer. 2. Store of multiple consecutive loads: int a = p->a; int b = p->b; q->a = a; q->b = b; In this case we load/store either ilegal vector registers or legal wide integer registers. llvm-svn: 165125
* Set up MCSchedModel after detecting the CPU type in X86SubTarget.Preston Gurd2012-10-031-0/+4
| | | | | | | | | Corrects a problem whereby MCSchedModel was not being set up when the CPU type was auto-detected. Patch by Andy Zhang. llvm-svn: 165122
* tsan: prepare for migration to new memory_order enum values (ABI compatible)Dmitry Vyukov2012-10-031-1/+2
| | | | llvm-svn: 165107
* Fixed a bug in the ExecutionDependencyFix pass that caused dependencies to ↵Silviu Baranga2012-10-031-3/+6
| | | | | | not propagate through implicit defs. llvm-svn: 165102
* Fix an issue where we failed to adjust the alignment constraint onChandler Carruth2012-10-031-0/+6
| | | | | | | | a memcpy to reflect that '0' has a different meaning when applied to a load or store. Now we correctly use underaligned loads and stores for the test case added. llvm-svn: 165101
* Try to use a better set of abstractions for computing the alignmentChandler Carruth2012-10-031-16/+28
| | | | | | | | | | | | | | | | | | | | necessary during rewriting. As part of this, fix a real think-o here where we might have left off an alignment specification when the address is in fact underaligned. I haven't come up with any way to trigger this, as there is always some other factor that reduces the alignment, but it certainly might have been an observable bug in some way I can't think of. This also slightly changes the strategy for placing explicit alignments on loads and stores to only do so when the alignment does not match that required by the ABI. This causes a few redundant alignments to go away from test cases. I've also added a couple of tests that really push on the alignment that we end up with on loads and stores. More to come here as I try to fix an underlying bug I have conjectured and produced test cases for, although it's not clear if this bug is the one currently hitting dragonegg's gcc47 bootstrap. llvm-svn: 165100
* Revert 165051-165049 while looking into the foreach.m failure inEric Christopher2012-10-033-28/+20
| | | | | | more detail. llvm-svn: 165099
* Fix doxygen comment to match function name.Craig Topper2012-10-031-1/+1
| | | | llvm-svn: 165094
* Remove unused function that used to get itineraries from SubTargetFeatures. ↵Craig Topper2012-10-031-24/+0
| | | | | | This is done from MCSubTargetInfo these days. llvm-svn: 165092
* Fix 80-column violationCraig Topper2012-10-031-2/+2
| | | | llvm-svn: 165089
* The early if conversion pass is ready to be used as an opt-in.Jakob Stoklund Olesen2012-10-032-4/+10
| | | | | | | | | | | Enable the pass by default for targets that request it, and change the -enable-early-ifcvt to the opposite -disable-early-ifcvt. There are still some x86 regressions when enabling early if-conversion because of the missing machine models. Disable the pass for x86 until machine models are added. llvm-svn: 165075
* Switch the SetVector::remove_if implementation to use partition whichChandler Carruth2012-10-031-1/+3
| | | | | | | | | | | | | | preserves the values of the relocated entries, unlikely remove_if. This allows walking them and erasing them. Also flesh out the predicate we are using for this to support the various constraints actually imposed on a UnaryPredicate -- without this we can't compose it with std::not1. Thanks to Sean Silva for the review here and noticing the issue with std::remove_if. llvm-svn: 165073
* Fix a serious X86 instruction selection bug. InEvan Cheng2012-10-021-3/+14
| | | | | | | | | | | | | X86DAGToDAGISel::PreprocessISelDAG(), isel is moving load inside callseq_start / callseq_end so it can be folded into a call. This can create a cycle in the DAG when the call is glued to a copytoreg. We have been lucky this hasn't caused too many issues because the pre-ra scheduler has special handling of call sequences. However, it has caused a crash in a specific tailcall case. rdar://12393897 llvm-svn: 165072
* Revert "Don't use a debug location for frame setup instructions in the"Eric Christopher2012-10-022-4/+5
| | | | | | | This reverts 165055 and 165052 temporarily while I look at debugger failures. llvm-svn: 165071
* Revert 165057, per Jim's request. This requires further discussion.Chad Rosier2012-10-021-26/+8
| | | | llvm-svn: 165069
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