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* [RISCV] Constant materialisation for RV64IAlex Bradbury2018-11-161-1/+28
| | | | | | | | | | | | | | | | | | | | | | | This commit introduces support for materialising 64-bit constants for RV64I, making use of the RISCVMatInt::generateInstSeq helper in order to share logic for immediate materialisation with the MC layer (where it's used for the li pseudoinstruction). test/CodeGen/RISCV/imm.ll is updated to test RV64, and gains new 64-bit constant tests. It would be preferable if anyext constant returns were sign rather than zero extended (see PR39092). This patch simply adds an explicit signext to the returns in imm.ll. Further optimisations for constant materialisation are possible, most notably for mask-like values which can be generated my loading -1 and shifting right. A future patch will standardise on the C++ codepath for immediate selection on RV32 as well as RV64, and then add further such optimisations to RISCVMatInt::generateInstSeq in order to benefit both RV32 and RV64 for codegen and li expansion. Differential Revision: https://reviews.llvm.org/D52962 llvm-svn: 347042
* [MSP430] Add support for .refsym directiveAnton Korobeynikov2018-11-161-0/+13
| | | | | | | | | | | | | | | Introduces support for '.refsym' assembler directive. From GCC docs (for MSP430): '.refsym' - This directive instructs assembler to add an undefined reference to the symbol following the directive. No relocation is created for this symbol; it will exist purely for pulling in object files from archives. Patch by Kristina Bessonova! Differential Revision: https://reviews.llvm.org/D54618 llvm-svn: 347041
* [DAGCombine] Fix non-deterministic debug outputSam Parker2018-11-161-4/+4
| | | | | | | | | | | PR37970 reported non-deterministic debug output, this was caused by iterating through a set and not a a vector. bugzilla: https://bugs.llvm.org/show_bug.cgi?id=37970 Differential Revision: https://reviews.llvm.org/D54570 llvm-svn: 347037
* [LegalizeVectorTypes] Teach WidenVecRes_Convert to turn ANY_EXTEND into ↵Craig Topper2018-11-161-0/+2
| | | | | | | | ANY_EXTEND_VECTOR_INREG when the input and output types need to be widened to the same width. If we don't do it here, DAGCombine will just end up creating it from the scalar any_extend+build_vector so might as well save a step. llvm-svn: 347034
* [ThinLTO] Internalize readonly globalsEugene Leviant2018-11-1610-51/+296
| | | | | | | | An attempt to recommit r346584 after failure on OSX build bot. Fixed cache key computation in ThinLTOCodeGenerator and added test case llvm-svn: 347033
* [X86] Add custom type legalization for v2i8/v4i8/v8i8 mul under ↵Craig Topper2018-11-161-2/+20
| | | | | | | | -x86-experimental-vector-widening. By early promoting the multiply to use an i16 element type we can avoid op legalization emit a second multiply for the 8 upper elements of the v16i8 type we would otherwise get. llvm-svn: 347032
* AMDGPU: Fix analyzeBranch failing with pseudoterminatorsMatt Arsenault2018-11-163-3/+31
| | | | | | | | | If a block had one of the _term instructions used for gluing exec modifying instructions to the end of the block, analyzeBranch would fail, preventing the verifier from catching a broken successor list. llvm-svn: 347027
* [X86] Use ANY_EXTEND instead of SIGN_EXTEND in the AVX2 and later path for ↵Craig Topper2018-11-161-2/+2
| | | | | | | | | | legalizing vXi8 multiply. We aren't going to use the upper bits of the multiply result that the extend would effect. So we don't need a specific type of extend. This makes some reduction test cases shorter because we were previously trying to sign_extend a truncate which we can't eliminate. llvm-svn: 347011
* [X86] Update a couple comments to remove a mention of a sign extending that ↵Craig Topper2018-11-161-3/+3
| | | | | | no longer happens. NFC llvm-svn: 347010
* [VFS] Implement `RedirectingFileSystem::getRealPath`.Volodymyr Sapsai2018-11-161-4/+29
| | | | | | | | | | | | | | | | | | | | | | | | | It fixes the case when Objective-C framework is added as a subframework through a symlink. When parent framework infers a module map and fails to detect a symlink, it would add a subframework as a submodule. And when we parse module map for the subframework, we would encounter an error like > error: umbrella for module 'WithSubframework.Foo' already covers this directory By implementing `getRealPath` "an egregious but useful hack" in `ModuleMap::inferFrameworkModule` works as expected. rdar://problem/45821279 Reviewers: bruno, benlangmuir, erik.pilkington Reviewed By: bruno Subscribers: hiraditya, dexonsmith, JDevlieghere, cfe-commits, llvm-commits Differential Revision: https://reviews.llvm.org/D54245 llvm-svn: 347009
* [AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/STRon Lieberman2018-11-168-4/+263
| | | | | | | | | Add a pass to fixup various vector ISel issues. Currently we handle converting GLOBAL_{LOAD|STORE}_* and GLOBAL_Atomic_* instructions into their _SADDR variants. This involves feeding the sreg into the saddr field of the new instruction. llvm-svn: 347008
* [WebAssembly] Split BBs after throw instructionsHeejin Ahn2018-11-162-17/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: `throw` instruction is a terminator in wasm, but BBs were not splitted after `throw` instructions, causing machine instruction verifier to fail. This patch - Splits BBs after `throw` instructions in WasmEHPrepare and adding an unreachable instruction after `throw`, which will be deleted in LateEHPrepare pass - Refactors WasmEHPrepare into two member functions - Changes the semantics of `eraseBBsAndChildren` in LateEHPrepare pass to match that of WasmEHPrepare pass, which is newly added. Now `eraseBBsAndChildren` does not delete BBs with remaining predecessors. - Fixes style nits, making static function names conform to clang-tidy - Re-enables the test temporarily disabled by rL346840 && rL346845 Reviewers: dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D54571 llvm-svn: 347003
* [AMDGPU] NFC Test commitRon Lieberman2018-11-161-1/+1
| | | | llvm-svn: 347002
* AMDHSA: More code object v3 fixes:Konstantin Zhuravlyov2018-11-151-1/+2
| | | | | | | | - Make sure IsaInfo::hasCodeObjectV3 returns true only for AMDHSA - Update assembler metadata tests to use v2 by default llvm-svn: 347001
* [X86] Remove ANY_EXTEND special case from canReduceVMulWidthCraig Topper2018-11-151-18/+2
| | | | | | | | | | Removing this code doesn't affect any lit tests so it doesn't appear to be tested anymore. I assume it was when it was added, but I guess something else changed? Code coverage report also says its unused. I mostly didn't like that it seemed to count the sign bits as if it was a sign_extend, but then set isPositive as if it was a zero_extend. It feels like we should have picked one interpretation? Differential Revision: https://reviews.llvm.org/D54596 llvm-svn: 346995
* [X86] Minor cleanup to getExtendInVec. NFCICraig Topper2018-11-151-4/+7
| | | | | | | | | | Use unsigned to calculate the subvector index to avoid a cast. Remove an unnecessary condition and replace it with a stronger assert. Use the InVT variable we updated when we extracted instead of grabbing it from the In SDValue. llvm-svn: 346983
* [X86] Add -x86-experimental-vector-widening support to reduceVMULWidth and ↵Craig Topper2018-11-151-14/+22
| | | | | | | | | | | | combineMulToPMADDWD In reduceVMULWidth, we no longer need to worry about extending the vector to 128 bits first. Regular widening of extends, muls and shuffles will take care of that for us. In combineMulToPMADDWD, we can handle v2i32 multiplies and allow the VPMADDWD to be widened to v4i32 during type legalization by adding custom widening like we do have for AVG/ADDUS/SUBUS. I had to modify that code a little to allow different and output VTs. Differential Revision: https://reviews.llvm.org/D54512 llvm-svn: 346980
* [WebAssembly] Fix return type of nextByteThomas Lively2018-11-151-2/+2
| | | | | | | | | | | | | | Summary: The old return type did not allow for correct error reporting and was causing a compiler warning. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D54586 llvm-svn: 346979
* [BinaryFormat] Add MsgPackTypesScott Linder2018-11-152-0/+304
| | | | | | | | | Add data structure to represent MessagePack "documents" and convert to/from both MessagePack and YAML encodings. Differential Revision: https://reviews.llvm.org/D48175 llvm-svn: 346978
* [X86] Guess that a CPU is Icelake it if reports support for AVX512VBMI2.Craig Topper2018-11-151-0/+6
| | | | llvm-svn: 346973
* [LTO] Load sample profile in LTO link step.Xin Tong2018-11-152-0/+13
| | | | | | | | | | | | | | Summary: Load sample profile in LTO link step. ThinLTO calls populateModulePassManager to load the profile Reviewers: tejohnson, davidxl, danielcdh Subscribers: mehdi_amini, inglorion, steven_wu, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D54564 llvm-svn: 346971
* [InstCombine] fix rotate narrowing bug for non-pow-2 typesSanjay Patel2018-11-151-2/+7
| | | | llvm-svn: 346968
* [X86] Fix MCNullStreamer support for modules with a CodeView flag Simon Pilgrim2018-11-151-8/+8
| | | | | | | | | | | | This fixes -filetype=null support when compiling for a Win32 target and the module has a CodeView flag. The only places changed are the uses of getTargetStreamer function - this patch guards both of them with null checks. Committed on behalf of @eush (Eugene Sharygin) Differential Revision: https://reviews.llvm.org/D54008 llvm-svn: 346962
* [InstSimplify] delete shift-of-zero guard ops around funnel shiftsSanjay Patel2018-11-151-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | This is a problem seen in common rotate idioms as noted in: https://bugs.llvm.org/show_bug.cgi?id=34924 Note that we are not canonicalizing standard IR (shifts and logic) to the intrinsics yet. (Although I've written this before...) I think this is the last step before we enable that transform. Ie, we could regress code by doing that transform without this simplification in place. In PR34924, I questioned whether this is a valid transform for target-independent IR, but I convinced myself this is ok. If we're speculating a funnel shift by turning cmp+br into select, then SimplifyCFG has already determined that the transform is justified. It's possible that SimplifyCFG is not taking into account profile or other metadata, but if that's true, then it's a bug independent of funnel shifts. Also, we do have CGP code to restore a guard like this around an intrinsic if it can't be lowered cheaply. But that isn't necessary for funnel shift because the default expansion in SelectionDAGBuilder includes this same cmp+select. Differential Revision: https://reviews.llvm.org/D54552 llvm-svn: 346960
* [RISCV] Mark C.EBREAK instruction as having side effectsAlex Bradbury2018-11-151-1/+1
| | | | | | | | | | | | | | | C.EBREAK was defined with hasSideEffects = 0, which is incorrect and inconsistent with the non-compressed instruction form. This patch corrects this oversight. This wouldn't cause codegen issues, as compressed instructions are only ever generated by converting the non-compressed form as an MCInst. But having correct flags is still worthwhile. Differential Revision: https://reviews.llvm.org/D54256 Patch by Luís Marques. llvm-svn: 346959
* [RISCV] Mark FREM as ExpandAlex Bradbury2018-11-151-1/+1
| | | | | | | | | | | | Mark the FREM SelectionDAG node as Expand, which is necessary in order to support the frem IR instruction on RISC-V. This is expanded into a library call. Adds the corresponding test. Previously, this would have triggered an assertion at instruction selection time. Differential Revision: https://reviews.llvm.org/D54159 Patch by Luís Marques. llvm-svn: 346958
* Add missed files from prev. commitAnton Korobeynikov2018-11-1511-0/+1572
| | | | llvm-svn: 346949
* [MSP430] Add MC layerAnton Korobeynikov2018-11-1519-1092/+1120
| | | | | | | | | | | | | | Reapply r346374 with the fixes for modules build. Original summary: This change implements assembler parser, code emitter, ELF object writer and disassembler for the MSP430 ISA. Also, more instruction forms are added to the target description. Patch by Michael Skvortsov! llvm-svn: 346948
* [RISCV] Introduce the RISCVMatInt::generateInstSeq helperAlex Bradbury2018-11-154-72/+132
| | | | | | | | | | | | | | | | | | | | | Logic to load 32-bit and 64-bit immediates is currently present in RISCVAsmParser::emitLoadImm in order to support the li pseudoinstruction. With the introduction of RV64 codegen, there is a greater benefit of sharing immediate materialisation logic between the MC layer and codegen. The generateInstSeq helper allows this by producing a vector of simple structs representing the chosen instructions. This can then be consumed in the MC layer to produce MCInsts or at instruction selection time to produce appropriate SelectionDAG node. Sharing this logic means that both the li pseudoinstruction and codegen can benefit from future optimisations, and that this logic can be used for materialising constants during RV64 codegen. This patch does contain a behaviour change: addi will now be produced on RV64 when no lui is necessary to materialise the constant. In that case addiw takes x0 as the source register, so is semantically identical to addi. Differential Revision: https://reviews.llvm.org/D52961 llvm-svn: 346937
* [X86] Add some custom type legalization rules for truncate with ↵Craig Topper2018-11-151-0/+64
| | | | | | | | -x86-experimental-vector-widening-legalization. This avoids some nasty shuffles when we have avx512. It will also prevent using zmm truncate instructions when a ymm instruction that zeroes part of an xmm register will do. Also avoid using avx512 truncate instructions when the input is 128 bits or less. These instructions are 2 uops on skx so we can probably find a better single uop shuffle like pshufb. llvm-svn: 346936
* [WebAssembly] Renumber SIMD bitwise instructionsThomas Lively2018-11-151-7/+7
| | | | | | | | | | | | Summary: Changed to match https://github.com/WebAssembly/simd/pull/54. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D54561 llvm-svn: 346931
* AMDGPU: Enable code object v3 for AMDHSA onlyKonstantin Zhuravlyov2018-11-152-17/+34
| | | | | | Differential Revision: https://reviews.llvm.org/D54186 llvm-svn: 346923
* [X86] Don't mark SEXTLOADS with narrow types as Custom with ↵Craig Topper2018-11-151-8/+27
| | | | | | | | -x86-experimental-vector-widening-legalization. The narrow types end up requesting widening, but generic legalization will end up scalaring and using a build_vector to do the widening. llvm-svn: 346916
* [MachineOutliner][NFC] Check if CandidatesForRepeatedSeq < 2Jessica Paquette2018-11-151-1/+1
| | | | | | There's no reason to call getOutliningCandidateInfo with a single candidate. llvm-svn: 346913
* [X86] Remove unused variableBenjamin Kramer2018-11-141-1/+0
| | | | llvm-svn: 346909
* [X86] Support v2i32/v4i16/v8i8 load/store using f64 on 32-bit targets under ↵Craig Topper2018-11-141-15/+38
| | | | | | | | | | -x86-experimental-vector-widening-legalization. On 64-bit targets the type legalizer will use i64 to legalize these. But when i64 isn't legal, the type legalizer won't try an FP type. So do it manually instead. There are a few regressions in here due to some v2i32 operations like mul and div now being reassembled into a full vector just to store instead of storing the pieces. But this was already occuring in 64-bit mode so its not a new issue. llvm-svn: 346908
* [MachineOutliner][NFC] Don't compute liveness if X16/X17/NZCV are unusedJessica Paquette2018-11-141-16/+32
| | | | | | | | | | | Using the MBB flags, we can tell if X16/X17/NZCV are unused in a block, and also not live out. If this holds for all MBBs, then we can avoid checking for liveness on that candidate. Furthermore, if it holds for an individual candidate's MBB, then we can avoid checking for liveness on that candidate. llvm-svn: 346901
* Remove unused getMDNodeFwdRefOrNull interfaces (NFC)Teresa Johnson2018-11-142-13/+3
| | | | | | | | | | | | | | | Summary: Followup from D53596/r346891. Remove the getMDNodeFwdRefOrNull interface to the MDLoader since it is no longer used. Also improve error messages when the internal implementation is used within the MDLoader. Reviewers: steven_wu Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54542 llvm-svn: 346899
* Bias physical register immediate assignmentsNirav Dave2018-11-143-29/+46
| | | | | | | | | | | | | | | | | | | | | | | The machine scheduler currently biases register copies to/from physical registers to be closer to their point of use / def to minimize their live ranges. This change extends this to also physical register assignments from immediate values. This causes a reduction in reduction in overall register pressure and minor reduction in spills and indirectly fixes an out-of-registers assertion (PR39391). Most test changes are from minor instruction reorderings and register name selection changes and direct consequences of that. Reviewers: MatzeB, qcolombet, myatsina, pcc Subscribers: nemanjai, jvesely, nhaehnle, eraman, hiraditya, javed.absar, arphaman, jfb, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D54218 llvm-svn: 346894
* [ThinLTO] Fix a crash in lazy loading of MetadataTeresa Johnson2018-11-141-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a revised version of D41474. When the debug location is parsed in BitcodeReader::parseFunction, the scope and inlinedAt MDNodes are obtained via MDLoader->getMDNodeFwdRefOrNull(), which will create a forward ref if they were not yet loaded. Specifically, if one of these MDNodes is in the module level metadata block, and this is during ThinLTO importing, that metadata block is lazily loaded. Most places in that invoke getMDNodeFwdRefOrNull have a corresponding call to resolveForwardRefsAndPlaceholders which will take care of resolving them. E.g. places that call getMetadataFwdRefOrLoad, or at the end of parsing a function-level metadata block, or at the end of the initial lazy load of module level metadata in order to handle invocations of getMDNodeFwdRefOrNull for named metadata and global object attachments. However, the calls for the scope/inlinedAt of debug locations are not backed by any such call to resolveForwardRefsAndPlaceholders. To fix this, change the scope and inlinedAt parsing to instead use getMetadataFwdRefOrLoad, which will ensure the forward refs to lazily loaded metadata are resolved. Fixes PR35472. llvm-svn: 346891
* AMDGPU: Additional pattern for i16 median3 matchingAakanksha Patil2018-11-141-4/+17
| | | | | | | | min(max(a, b), max(min(a, b), c)) Differential Revision: https://reviews.llvm.org/D54494 llvm-svn: 346886
* [Support] Teach YAMLIO about polymorphic typesScott Linder2018-11-141-15/+73
| | | | | | | | | | | | | | | | | | | | | Add support for "polymorphic" types to YAMLIO. PolymorphicTraits can dynamically switch between other traits (Scalar, Map, or Sequence). When inputting, the PolymorphicTraits type is told which type to become, and when outputting the PolymorphicTraits type is asked which type it currently is. Also add support for TaggedScalarTraits to allow dynamically differentiating between multiple scalar types using YAML tags. Serialize empty maps as "{}" and empty sequences as "[]", so that types are preserved when round-tripping PolymorphicTraits. This change has equivalent semantics, but may break e.g. tests which compare output verbatim. Differential Revision: https://reviews.llvm.org/D48144 llvm-svn: 346884
* [ThinLTO] Update handling of vararg functions to match inlinerTeresa Johnson2018-11-141-2/+7
| | | | | | | | | | | | | | | | | Summary: Previously we marked all vararg functions as non-inlinable in the function summary, which prevented their importing. However, the corresponding inliner restriction was loosened in r321940/r342675 to only apply to functions calling va_start. Adjust the summary flag computation to match. Reviewers: davidxl Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D54270 llvm-svn: 346883
* [WebAssembly] Add support for dylink section in object formatSam Clegg2018-11-142-2/+30
| | | | | | | | See https://github.com/WebAssembly/tool-conventions/blob/master/DynamicLinking.md. Differential Revision: https://reviews.llvm.org/D54490 llvm-svn: 346880
* [X86] Allow pmulh to be formed from narrow vXi16 vectors under ↵Craig Topper2018-11-141-2/+4
| | | | | | | | | | -x86-experimental-vector-widening-legalization Narrower vectors will be widened to 128 bits without changing the element size. And generic type legalization can already handle widening mulhu/mulhs. Differential Revision: https://reviews.llvm.org/D54513 llvm-svn: 346879
* [InstCombine] Remove a couple of asserts based on incorrect assumptionsMandeep Singh Grang2018-11-141-11/+4
| | | | | | | | | | | | | | | | Summary: These asserts are based on the assumption that the order of true/false operands in a select and those in the compare would always be the same. This fixes PR39595. Reviewers: craig.topper, spatel, dmgreen Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54359 llvm-svn: 346874
* [InstCombine] fix formatting for matchBSwap(); NFCSanjay Patel2018-11-142-7/+9
| | | | | | | We should have a similar function for matching rotate and/or funnel shift, so tidy up the related existing call. llvm-svn: 346871
* [VPlan, SLP] Use SmallPtrSet for Candidates.Florian Hahn2018-11-142-27/+26
| | | | | | This slightly improves the candidate handling in getBest(). llvm-svn: 346870
* [TTI] getOperandInfo - a broadcast shuffle means the result is OK_UniformValue Simon Pilgrim2018-11-141-0/+7
| | | | llvm-svn: 346868
* [VPlan] Remove LLVM_DEBUG from VPlanSlp::dumpBundle.Florian Hahn2018-11-141-4/+4
| | | | | | The caller should take care of only calling it with debug enabled. llvm-svn: 346860
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