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* Added 32-bit Thumb instructions t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV, and t2DBGJohnny Chen2010-03-031-0/+28
| | | | | | for disassembly only. llvm-svn: 97632
* Use APInt instead of zext value.Bill Wendling2010-03-031-1/+1
| | | | llvm-svn: 97631
* factor the 'in the default address space' check out to a singleChris Lattner2010-03-031-51/+30
| | | | | | | 'dsload' pattern. tblgen doesn't check patterns to see if they're textually identical. This allows better factoring. llvm-svn: 97630
* factor the 'sign extended from 8 bit' patterns better so Chris Lattner2010-03-033-20/+11
| | | | | | | | that they are not destination type specific. This allows tblgen to factor them and the type check is redundant with what the isel does anyway. llvm-svn: 97629
* - Change MachineInstr::isIdenticalTo to take a new option that determines ↵Evan Cheng2010-03-035-38/+34
| | | | | | | | whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality. - Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools). llvm-svn: 97628
* Add an option to enable machine cse (it's not doing anything yet.Evan Cheng2010-03-031-0/+5
| | | | llvm-svn: 97627
* Eliminate unused instruction classes.Evan Cheng2010-03-031-13/+0
| | | | llvm-svn: 97617
* This test case:Bill Wendling2010-03-032-7/+11
| | | | | | | | | | | | | | | | | | | | | long test(long x) { return (x & 123124) | 3; } Currently compiles to: _test: orl $3, %edi movq %rdi, %rax andq $123127, %rax ret This is because instruction and DAG combiners canonicalize (or (and x, C), D) -> (and (or, D), (C | D)) However, this is only profitable if (C & D) != 0. It gets in the way of the 3-addressification because the input bits are known to be zero. llvm-svn: 97616
* Added 32-bit Thumb instructions t2DMB variants, t2DSB variants, and t2ISBsy forJohnny Chen2010-03-031-0/+60
| | | | | | disassembly only. llvm-svn: 97614
* Add Module functions in place of module providers.Erick Tryzelaar2010-03-023-33/+97
| | | | llvm-svn: 97608
* merge two loops over all nodes in the graph into one.Chris Lattner2010-03-021-57/+41
| | | | llvm-svn: 97606
* eliminate PreprocessForRMW now that isel handles it.Chris Lattner2010-03-021-136/+27
| | | | | | We still preprocess calls and fp return stuff. llvm-svn: 97598
* remove 300 lines of code that is now dead in the MSP430 backendChris Lattner2010-03-021-293/+1
| | | | | | | now that isel handles chains more aggressively. This also allows us to make isLegalToFold non-virtual. llvm-svn: 97597
* Fix some issues in WalkChainUsers dealing with Chris Lattner2010-03-023-56/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | CopyToReg/CopyFromReg/INLINEASM. These are annoying because they have the same opcode before an after isel. Fix this by setting their NodeID to -1 to indicate that they are selected, just like what automatically happens when selecting things that end up being machine nodes. With that done, give IsLegalToFold a new flag that causes it to ignore chains. This lets the HandleMergeInputChains routine be the one place that validates chains after a match is successful, enabling the new hotness in chain processing. This smarter chain processing eliminates the need for "PreprocessRMW" in the X86 and MSP430 backends and enables MSP to start matching it's multiple mem operand instructions more aggressively. I currently #if out the dead code in the X86 backend and MSP backend, I'll remove it for real in a follow-on patch. The testcase changes are: test/CodeGen/X86/sse3.ll: we generate better code test/CodeGen/X86/store_op_load_fold2.ll: PreprocessRMW was miscompiling this before, we now generate correct code Convert it to filecheck while I'm at it. test/CodeGen/MSP430/Inst16mm.ll: Add a testcase for mem/mem folding to make anton happy. :) llvm-svn: 97596
* Added 32-bit Thumb instruction CLREX (Clear-Exclusive) for disassembly only.Johnny Chen2010-03-021-0/+10
| | | | llvm-svn: 97595
* Okay. One last attempt:Bill Wendling2010-03-021-3/+3
| | | | | | Place the LSDA into the TEXT section on Mach-O. This saves space. llvm-svn: 97592
* Rename LLVMUseIteratorRef to LLVMUseRef since we don't refer to iterators in ↵Erick Tryzelaar2010-03-021-7/+10
| | | | | | llvm-c. llvm-svn: 97585
* Removed the extra S from the multiclass def T2I_adde_sube_s_irs as well as fromJohnny Chen2010-03-021-14/+14
| | | | | | | the opc string passed in, since it's a given from the class inheritance of T2sI. The fixed the extra 's' in adcss & sbcss when disassembly printing. llvm-svn: 97582
* run HandleMergeInputChains even if we only have one input chain.Chris Lattner2010-03-021-29/+3
| | | | llvm-svn: 97581
* When expanding an expression such as (A + B + C + D), sort the operandsDan Gohman2010-03-021-31/+121
| | | | | | | by loop depth and emit loop-invariant subexpressions outside of loops. This speeds up MultiSource/Applications/viterbi and others. llvm-svn: 97580
* Swap parameters of isSafeToMove and isSafeToReMat for consistency.Evan Cheng2010-03-025-10/+10
| | | | llvm-svn: 97578
* Fix typo.Evan Cheng2010-03-021-1/+1
| | | | llvm-svn: 97577
* Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL,Johnny Chen2010-03-022-7/+164
| | | | | | | SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for disassembly only. llvm-svn: 97573
* Fix grammar.Devang Patel2010-03-021-1/+1
| | | | | | Thanks Duncan! llvm-svn: 97572
* AL is an optional mnemonic extension for always, except in IT instructions.Johnny Chen2010-03-024-1/+15
| | | | | | | Add printMandatoryPredicateOperand() PrintMethod for IT predicate printing. Ref: A8.3 Conditional execution llvm-svn: 97571
* Change some asm shift opcode strings to lowercase.Johnny Chen2010-03-021-6/+6
| | | | llvm-svn: 97567
* fix typo add missing (Xerxes Ranby2010-03-021-2/+2
| | | | llvm-svn: 97565
* Unbreak llvm-arm-linux buildbot and fix PR5309.Xerxes Ranby2010-03-021-2/+2
| | | | llvm-svn: 97564
* Rather than passing "false" for InsertBefore, AddressSpace for ThreadLocal,Duncan Sands2010-03-021-2/+2
| | | | | | | and nothing for AddressSpace, pass 0 for InsertBefore, "false" for ThreadLocal and AddressSpace for AddressSpace. Spotted by gcc-4.5. llvm-svn: 97563
* Fix the xfail I added a couple of patches back. The issueChris Lattner2010-03-021-12/+40
| | | | | | | | | was that we weren't properly handling the case when interior nodes of a matched pattern become dead after updating chain and flag uses. Now we handle this explicitly in UpdateChainsAndFlags. llvm-svn: 97561
* I was confused about this, it turns out that MorphNodeToChris Lattner2010-03-021-3/+2
| | | | | | *does* delete ex-operands that become dead. llvm-svn: 97559
* factor node morphing out to its own helper method.Chris Lattner2010-03-021-54/+62
| | | | llvm-svn: 97558
* Sink InstructionSelect() out of each target into SDISel, and rename itChris Lattner2010-03-0215-334/+101
| | | | | | | | | | | | DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader. Sink some other stuff out of DAGISelHeader into SDISel. Eliminate the various 'Indent' stuff from various targets, which dates to when isel was recursive. 17 files changed, 114 insertions(+), 430 deletions(-) llvm-svn: 97555
* Only save vector registers if we've defined for the vector registers.Eric Christopher2010-03-021-2/+2
| | | | | | Fixes PR5309. llvm-svn: 97554
* Fix looking up MD names to not need a module.Erick Tryzelaar2010-03-021-10/+12
| | | | llvm-svn: 97550
* Add file to CMakeLists.txtEric Christopher2010-03-021-0/+1
| | | | llvm-svn: 97545
* Add skeleton of a machine level cse pass.Evan Cheng2010-03-021-0/+124
| | | | llvm-svn: 97543
* Use the right induction variable.Chris Lattner2010-03-021-2/+2
| | | | llvm-svn: 97541
* Rewrite chain handling validation and input TokenFactor handlingChris Lattner2010-03-021-54/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | stuff now that we don't care about emulating the old broken behavior of the old isel. This eliminates the 'CheckChainCompatible' check (along with IsChainCompatible) which did an incorrect and inefficient scan *up* the chain nodes which happened as the pattern was being formed and does the validation at the end in HandleMergeInputChains when it forms a structural pattern. This scans "down" the graph, which means that it is quickly bounded by nodes already selected. This also handles token factors that get "trapped" in the dag. Removing the CheckChainCompatible nodes also shrinks the generated tables by about 6K for X86 (down to 83K). There are two pieces remaining before I can nuke PreprocessRMW: 1. I xfailed a test because we're now producing worse code in a case that has nothing to do with the change: it turns out that our use of MorphNodeTo will leave dead nodes in the graph which (depending on how the graph is walked) end up causing bogus uses of chains and blocking matches. This is really bad for other reasons, so I'll fix this in a follow-up patch. 2. CheckFoldableChainNode needs to be improved to handle the TF. llvm-svn: 97539
* Fix several places to handle vector operands properly.Dan Gohman2010-03-023-6/+6
| | | | | | Based on a patch by Micah Villmow for PR6438. llvm-svn: 97538
* Non-affine post-inc SCEV expansions have more code which must beDan Gohman2010-03-022-3/+7
| | | | | | | emitted after the increment. Make sure the insert position reflects this. This fixes PR6453. llvm-svn: 97537
* Remove dead parameter passing.Bill Wendling2010-03-0210-69/+58
| | | | llvm-svn: 97536
* Constructors and operators for anonymous aggregates does not names. Do not ↵Devang Patel2010-03-021-1/+3
| | | | | | force empty AT_name attribute in such cases. llvm-svn: 97533
* Floating-point add, sub, and mul are now spelled fadd, fsub, and fmul,Dan Gohman2010-03-024-9/+9
| | | | | | respectively. llvm-svn: 97531
* remove dead code.Chris Lattner2010-03-021-31/+0
| | | | llvm-svn: 97529
* Don't attempt load PRE when there is no real redundancy (i.e., the load is inBob Wilson2010-03-021-4/+6
| | | | | | a loop and is itself the only dependency). llvm-svn: 97526
* refactor some code out of OPC_EmitMergeInputChains into aChris Lattner2010-03-021-21/+37
| | | | | | new helper function. llvm-svn: 97525
* When GVN needs to split critical edges for load PRE, check all of theBob Wilson2010-03-011-1/+4
| | | | | | | | predecessors before returning. Otherwise, if multiple predecessor edges need splitting, we only get one of them per iteration. This makes a small but measurable compile time improvement with -enable-full-load-pre. llvm-svn: 97521
* remove a little hack I did for the old isel, not neededChris Lattner2010-03-011-16/+2
| | | | | | now that it is gone. llvm-svn: 97516
* MemoryDepAnalysis is not used if redundant load processing is disabled.Evan Cheng2010-03-011-1/+1
| | | | llvm-svn: 97512
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