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* [PM/AA] Put the 'final' keyword in the correct place. And actuallyChandler Carruth2015-07-221-1/+1
| | | | | | succeed at compiling my change before committing it too! llvm-svn: 242879
* [PM/AA] Replace the only use of the AliasAnalysis::deleteValue API (inChandler Carruth2015-07-221-35/+58
| | | | | | | | | | | | | | | | | | | | | | GlobalsModRef) with CallbackVHs that trigger the same behavior. This is technically more expensive, but in benchmarking some LTO runs, it seems unlikely to even be above the noise floor. The only way I was able to measure the performance of GMR at all was to run nothing else but this one analysis on a linked clang bitcode file. The call graph analysis still took 5x more time than GMR, and this change at most made GMR 2% slower (this is well within the noise, so its hard for me to be sure that this is an actual change). However, in a real LTO run over the same bitcode, the GMR run takes so little time that the pass timers don't measure it. With this, I can remove the last update API from the AliasAnalysis interface, but I'll actually remove the interface hook point in a follow-up commit. Differential Revision: http://reviews.llvm.org/D11324 llvm-svn: 242878
* AVX-512: Added intrinsics for VCVT* instructions.Elena Demikhovsky2015-07-222-7/+181
| | | | | | | | All SKX forms. All VCVT instructions for float/double/int/long types. Differential Revision: http://reviews.llvm.org/D11343 llvm-svn: 242877
* [LoopUnswitch] Code refactoring to separate trivial loop unswitch and ↵Chen Li2015-07-221-96/+112
| | | | | | | | | | | | | | non-trivial loop unswitch in processCurrentLoop() Summary: The current code in LoopUnswtich::processCurrentLoop() mixes trivial loop unswitch and non-trivial loop unswitch together. It goes over all basic blocks in the loop and checks if a condition is trivial or non-trivial unswitch condition. However, trivial unswitch condition can only occur in the loop header basic block (where it controls whether or not the loop does something at all). This refactoring separate trivial loop unswitch and non-trivial loop unswitch. Before going over all basic blocks in the loop, it checks if the loop header contains a trivial unswitch condition. If so, unswitch it. Otherwise, go over all blocks like before but don't check trivial condition any more since they are not possible to be in the other blocks. This code has no functionality change. Reviewers: meheff, reames, broune Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11276 llvm-svn: 242873
* [BranchFolding] do not iterate the aliases of virtual registersJingyue Wu2015-07-222-16/+28
| | | | | | | | | | | | | | | | | Summary: MCRegAliasIterator only works for physical registers. So, do not run it on virtual registers. With this issue fixed, we can resurrect the BranchFolding pass in NVPTX backend. Reviewers: jholewinski, bkramer Subscribers: henryhu, meheff, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11174 llvm-svn: 242871
* [SROA] Fix a nasty pile of bugs to do with big-endian, different allocaChandler Carruth2015-07-221-11/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | types and loads, loads or stores widened past the size of an alloca, etc. This started off with a bug report about big-endian behavior with bitfields and loads and stores to a { i32, i24 } struct. An initial attempt to fix this was sent for review in D10357, but that didn't really get to the root of the problem. The core issue was that canConvertValue and convertValue in SROA were handling different bitwidth integers by doing a zext of the integer. It wouldn't do a trunc though, only a zext! This would in turn lead SROA to form an i24 load from an i24 alloca, zext it to i32, and then use it. This would at least produce the wrong value for big-endian systems. One of my many false starts here was to correct the computation for big-endian systems by shifting. But this doesn't actually work because the original code has a 64-bit store to the entire 8 bytes, and a 32-bit load of the last 4 bytes, and because the alloc size is 8 bytes, we can't lose that last (least significant if bigendian) byte! The real problem here is that we're forming an i24 load in SROA which is actually not sufficiently wide to load all of the necessary bits here. The source has an i32 load, and SROA needs to form that as well. The straightforward way to do this is to disable the zext logic in canConvertValue and convertValue, forcing us to actually load all 32-bits. This seems like a really good change, but it in turn breaks several other parts of SROA. First in the chain of knock-on failures, we had places where we were doing integer-widening promotion even though some of the integer loads or stores extended *past the end* of the alloca's memory! There was even a comment about preventing this, but it only prevented the case where the type had a different bit size from its store size. So I added checks to handle the cases where we actually have a widened load or store and to avoid trying to special integer widening promotion in those cases. Second, we actually rely on the ability to promote in the face of loads past the end of an alloca! This is important so that we can (for example) speculate loads around PHI nodes to do more promotion. The bits loaded are garbage, but as long as they aren't used and the alignment is suitable high (which it wasn't in the test case!) this is "fine". And we can't stop promoting here, lots of things stop working well if we do. So we need to add specific logic to handle the extension (and truncation) case, but *only* where that extension or truncation are over bytes that *are outside the alloca's allocated storage* and thus totally bogus to load or store. And of course, once we add back this correct handling of extension or truncation, we need to correctly handle bigendian systems to avoid re-introducing the exact bug that started us off on this chain of misery in the first place, but this time even more subtle as it only happens along speculated loads atop a PHI node. I've ported an existing test for PHI speculation to the big-endian test file and checked that we get that part correct, and I've added several more interesting big-endian test cases that should help check that we're getting this correct. Fun times. llvm-svn: 242869
* [Fuzzer] Rely on $PATH expansion instead of hardcoding paths in tests. NFC.Alexey Samsonov2015-07-213-14/+15
| | | | llvm-svn: 242851
* [Fuzzer] Clearly separate regular and DFSan tests. NFC.Alexey Samsonov2015-07-215-7/+10
| | | | llvm-svn: 242850
* MIR Serialization: Start serializing the CFI operands with .cfi_def_cfa_offset.Alex Lorenz2015-07-214-1/+56
| | | | | | | | This commit begins serialization of the CFI index machine operands by serializing one kind of CFI instruction - the .cfi_def_cfa_offset instruction. Reviewers: Duncan P. N. Exon Smith llvm-svn: 242845
* Fix a performance problem in memcpyopt by removing a linear scan over ranges ↵Nick Lewycky2015-07-211-16/+9
| | | | | | when inserting a new range. No functionality change intended. Patch by Anthony Pesch! llvm-svn: 242843
* [MDA] change BlockScanLimit into a command line option.Jingyue Wu2015-07-211-1/+5
| | | | | | | | | | | | | | | | | | | | Summary: In the benchmark (https://github.com/vetter/shoc) we are researching, the duplicated load is not eliminated because MemoryDependenceAnalysis hit the BlockScanLimit. This patch change it into a command line option instead of a hardcoded value. Patched by Xuetian Weng. Test Plan: test/Analysis/MemoryDependenceAnalysis/memdep-block-scan-limit.ll Reviewers: jingyue, reames Subscribers: reames, llvm-commits Differential Revision: http://reviews.llvm.org/D11366 llvm-svn: 242842
* [AsmPrinter] Check for valid constants in handleIndirectSymViaGOTPCRelBruno Cardoso Lopes2015-07-211-1/+1
| | | | | | | | | Check whether BaseCst is valid before extracting a GlobalValue. This fixes PR24163. Patch by David Majnemer. llvm-svn: 242840
* [PPC64LE] More vector swap optimization TLCBill Schmidt2015-07-211-21/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes one substantive change and a few stylistic changes to the VSX swap optimization pass. The substantive change is to permit LXSDX and LXSSPX instructions to participate in swap optimization computations. The previous change to insert a swap following a SUBREG_TO_REG widening operation makes this almost trivial. I experimented with also permitting STXSDX and STXSSPX instructions. This can be done using similar techniques: we could insert a swap prior to a narrowing COPY operation, and then permit these stores to participate. I prototyped this, but discovered that the pattern of a narrowing COPY followed by an STXSDX does not occur in any of our test-suite code. So instead, I added commentary indicating that this could be done. Other TLC: - I changed SH_COPYSCALAR to SH_COPYWIDEN to more clearly indicate the direction of the copy. - I factored the insertion of swap instructions into a separate function. Finally, I added a new test case to check that the scalar-to-vector loads are working properly with swap optimization. llvm-svn: 242838
* MIR Parser: Reuse the function 'lexName' when lexing global value tokens. NFC.Alex Lorenz2015-07-211-31/+19
| | | | | | | This commit refactors the function 'maybeLexGlobalValue' so that now it reuses the function 'lexName' when lexing a named global value token. llvm-svn: 242837
* [SCEV][NFC] Fix a typo in a comment.Sanjoy Das2015-07-211-6/+6
| | | | llvm-svn: 242834
* [RewriteStatepointsForGC] minor style cleanupPhilip Reames2015-07-211-26/+25
| | | | | | Use a named lambda for readability, common some code, remove a stale comments, and use llvm style variable names. llvm-svn: 242827
* Follow up to r242810. NFC.Chad Rosier2015-07-211-1/+1
| | | | llvm-svn: 242812
* [AArch64] Simplify the passing of arguments. NFC.Chad Rosier2015-07-211-23/+37
| | | | | | This is setup for future work planned for the AArch64 Load/Store Opt pass. llvm-svn: 242810
* Re-land 242726 to use RAII to do cleanupReid Kleckner2015-07-211-0/+50
| | | | | | | The LooksLikeCodeInBug11395() codepath was returning without clearing the ProcessedAllocas cache. llvm-svn: 242809
* [RewriteStatepointsForGC] Hoist some code out of a loopPhilip Reames2015-07-211-12/+13
| | | | llvm-svn: 242808
* MergeFunc: Transfer the callee's attributes when replacing a direct callerArnold Schwaighofer2015-07-211-0/+19
| | | | | | | | | | We insert a bitcast which obfuscates the getCalledFunction for the utility function which looks up attributes from the called function. Loosing ABI changing parameter attributes is a bad thing. rdar://21516488 llvm-svn: 242807
* MIR Serialization: Serialize the external symbol machine operands.Alex Lorenz2015-07-215-1/+65
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 242806
* [RewriteStatepointsForGC] Delete trivial codePhilip Reames2015-07-211-13/+5
| | | | | | A bit more code cleanup: delete some a trivial true assertion and supporting code, remove a redundant cast, and use count in assertions where feasible. llvm-svn: 242805
* IR: Extract a function 'printLLVMNameWithoutPrefix' from 'PrintLLVMName'. NFC.Alex Lorenz2015-07-211-14/+26
| | | | | | | | | | | | | This commit extracts the code that prints out a name of an LLVM value without a prefix from a function 'PrintLLVMName' into a publicly accessible function named 'printLLVMNameWithoutPrefix'. This change would be useful for MIR serialization, as it would allow the MIR printer to reuse this function to print out the names of the external symbol machine operands. Reviewers: Duncan P. N. Exon Smith llvm-svn: 242803
* fix formatting; NFCSanjay Patel2015-07-211-2/+2
| | | | llvm-svn: 242796
* Revert 242726, it broke ASan on OS X.Nico Weber2015-07-211-40/+0
| | | | llvm-svn: 242792
* Constfold trunc,rint,nearbyint,ceil and floor using APFloatKarthik Bhat2015-07-211-4/+33
| | | | | | | | A patch by Chakshu Grover! This patch allows constfolding of trunc,rint,nearbyint,ceil and floor intrinsics using APFloat class. Differential Revision: http://reviews.llvm.org/D11144 llvm-svn: 242763
* AVX512 : Implemented VPMADDUBSW and VPMADDWD instruction , Igor Breger2015-07-215-1/+38
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D11351 llvm-svn: 242761
* [ARM] Define subtarget feature "reserve-r9", which is used to decideAkira Hatanaka2015-07-213-13/+12
| | | | | | | | | | | | | | | | | | | | whether register r9 should be reserved. This recommits r242737, which broke bots because the number of subtarget features went over the limit of 64. This change is needed because we cannot use a backend option to set cl::opt "arm-reserve-r9" when doing LTO. Out-of-tree projects currently using cl::opt option "-arm-reserve-r9" to reserve r9 should make changes to add subtarget feature "reserve-r9" to the IR. rdar://problem/21529937 Differential Revision: http://reviews.llvm.org/D11320 llvm-svn: 242756
* [RewriteStatepointsForGC] Minor code cleanup [NFC]Philip Reames2015-07-211-21/+5
| | | | | | We can use builders to simplify part of the code and we only check for the existance of the metadata value; this enables us to delete some redundant code. llvm-svn: 242751
* AMDGPU: Set isMoveImm on s_movk_i32Matt Arsenault2015-07-211-1/+1
| | | | llvm-svn: 242747
* ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common codeMatthias Braun2015-07-211-166/+186
| | | | | | | | | | | | | | | Re-apply of r241928 which had to be reverted because of the r241926 revert. This commit factors out common code from MergeBaseUpdateLoadStore() and MergeBaseUpdateLSMultiple() and introduces a new function MergeBaseUpdateLSDouble() which merges adds/subs preceding/following a strd/ldrd instruction into an strd/ldrd instruction with writeback where possible. Differential Revision: http://reviews.llvm.org/D10676 llvm-svn: 242743
* ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2Matthias Braun2015-07-211-31/+102
| | | | | | | | | | Re-apply r241926 with an additional check that r13 and r15 are not used for LDRD/STRD. See http://llvm.org/PR24190. This also already includes the fix from r241951. Differential Revision: http://reviews.llvm.org/D10623 llvm-svn: 242742
* Revert r242737.Akira Hatanaka2015-07-203-12/+13
| | | | | | | | This caused builds to fail with the following error message: error:Too many subtarget features! Bump MAX_SUBTARGET_FEATURES. llvm-svn: 242740
* [ARM] Define subtarget feature "reserve-r9", which is used to decideAkira Hatanaka2015-07-203-13/+12
| | | | | | | | | | | | | | | | | whether register r9 should be reserved. This change is needed because we cannot use a backend option to set cl::opt "arm-reserve-r9" when doing LTO. Out-of-tree projects currently using cl::opt option "-arm-reserve-r9" to reserve r9 should make changes to add subtarget feature "reserve-r9" to the IR. rdar://problem/21529937 Differential Revision: http://reviews.llvm.org/D11320 llvm-svn: 242737
* Revert "ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2"Matthias Braun2015-07-201-96/+29
| | | | | | This reverts commit r241926. This caused http://llvm.org/PR24190 llvm-svn: 242735
* Revert "ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common code"Matthias Braun2015-07-201-186/+166
| | | | | | This reverts commit r241928. This caused http://llvm.org/PR24190 llvm-svn: 242734
* Revert "ARM: Use SpecificBumpPtrAllocator to fix leak introduced in r241920"Matthias Braun2015-07-201-3/+3
| | | | | | This reverts commit r241951. It caused http://llvm.org/PR24190 llvm-svn: 242733
* AArch64: Restrict macroop fusion heuristics to cyclone.Matthias Braun2015-07-201-31/+33
| | | | | | | Even though this is just some hinting for the scheduler it doesn't make sense to do that unless you know the target can perform the fusion. llvm-svn: 242732
* Targets: commonize some stack realignment codeJF Bastien2015-07-2016-165/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following: * Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`. * Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute. Multiple targets duplicated the same `needsStackRealignment` code: - Aarch64. - ARM. - Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has. - PowerPC. - WebAssembly. - x86 almost: has an extra `-force-align-stack` option, which the default implementation now has. The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects: - AMDGPU - BPF - CppBackend - MSP430 - NVPTX - Sparc - SystemZ - XCore - Out-of-tree targets This is a breaking change! `make check` passes. The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation. `needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11160 llvm-svn: 242727
* Don't try to instrument allocas used by outlined SEH funcletsReid Kleckner2015-07-201-0/+40
| | | | | | | | | | | | | | | | | | | Summary: Arguments to llvm.localescape must be static allocas. They must be at some statically known offset from the frame or stack pointer so that other functions can access them with localrecover. If we ever want to instrument these, we can use more indirection to recover the addresses of these local variables. We can do it during clang irgen or with the asan module pass. Reviewers: eugenis Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11307 llvm-svn: 242726
* AArch64: Add aditional Cyclone macroop fusion opportunitiesMatthias Braun2015-07-201-16/+34
| | | | | | | | Related to rdar://19205407 Differential Revision: http://reviews.llvm.org/D10746 llvm-svn: 242724
* MachineScheduler: Restrict macroop fusion to data-dependent instructions.Matthias Braun2015-07-201-9/+33
| | | | | | | | | | | | | | Before creating a schedule edge to encourage MacroOpFusion check that: - The predecessor actually writes a register that the branch reads. - The predecessor has no successors in the ScheduleDAG so we can schedule it in front of the branch. This avoids skewing the scheduling heuristic in cases where macroop fusion cannot happen. Differential Revision: http://reviews.llvm.org/D10745 llvm-svn: 242723
* Fix comment typo (test commit). NFCGeoff Berry2015-07-201-1/+1
| | | | llvm-svn: 242719
* [ARM] Refactor the prologue/epilogue emission to be more robust.Quentin Colombet2015-07-204-118/+219
| | | | | | | | | | | | | | | | This is the first step toward supporting shrink-wrapping for this target. The changes could be summarized by these items: - Expand the tail-call return as part of the expand pseudo pass. - Get rid of the assumptions that the epilogue is the exit block: * Do not assume which registers are free in the epilogue. (This indirectly improve the lowering of the code for the segmented stacks, see the test cases.) * Take into account that the basic block can be empty. Related to <rdar://problem/20821730> llvm-svn: 242714
* [NVPTX] make load on global readonly memory to use ldgJingyue Wu2015-07-201-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: [NVPTX] make load on global readonly memory to use ldg Summary: As describe in [1], ld.global.nc may be used to load memory by nvcc when __restrict__ is used and compiler can detect whether read-only data cache is safe to use. This patch will try to check whether ldg is safe to use and use them to replace ld.global when possible. This change can improve the performance by 18~29% on affected kernels (ratt*_kernel and rwdot*_kernel) in S3D benchmark of shoc [2]. Patched by Xuetian Weng. [1] http://docs.nvidia.com/cuda/kepler-tuning-guide/#read-only-data-cache [2] https://github.com/vetter/shoc Test Plan: test/CodeGen/NVPTX/load-with-non-coherent-cache.ll Reviewers: jholewinski, jingyue Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D11314 llvm-svn: 242713
* [Hexagon] Generate MUX from conditional transfers when dot-new not possibleKrzysztof Parzyszek2015-07-203-0/+328
| | | | llvm-svn: 242711
* MIR Serialization: Initial serialization of machine constant pools.Alex Lorenz2015-07-206-1/+89
| | | | | | | | | | This commit implements the initial serialization of machine constant pools and the constant pool index machine operands. The constant pool is serialized using a YAML sequence of YAML mappings that represent the constant values. The target-specific constant pool items aren't serialized by this commit. Reviewers: Duncan P. N. Exon Smith llvm-svn: 242707
* [ImplicitNullChecks] Work with implicit defs.Sanjoy Das2015-07-202-7/+15
| | | | | | | | | | | | | | | Summary: This change generalizes the implicit null checks pass to work with instructions that don't have any explicit register defs. This lets us use X86's `cmp` against memory as faulting load instructions. Reviewers: reames, JosephTremoulet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11286 llvm-svn: 242703
* MIR Parser: Add support for quoted named global value operands.Alex Lorenz2015-07-203-7/+102
| | | | | | | | | | This commit extends the machine instruction lexer and implements support for the quoted global value tokens. With this change the syntax for the global value identifier tokens becomes identical to the syntax for the global identifier tokens from the LLVM's assembly language. Reviewers: Duncan P. N. Exon Smith llvm-svn: 242702
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