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* use bool operator shortcut; NFCSanjay Patel2015-03-031-2/+1
| | | | llvm-svn: 231123
* Fixing problem with field initialization orderAndrew Kaylor2015-03-031-2/+2
| | | | llvm-svn: 231122
* Fix PR22762. When emitting a DWARF expression check whether this is theAdrian Prantl2015-03-031-6/+7
| | | | | | | | frame register before checking if there is a DWARF register number for it. Thanks to H.J. Lu for diagnosing this and providing the testcase! llvm-svn: 231121
* Outline cleanup handlers for native Windows C++ exception handlingAndrew Kaylor2015-03-031-97/+251
| | | | | | Differential Revision: http://reviews.llvm.org/D7865 llvm-svn: 231117
* Add the following 64-bit vector integer arithmetic instructions added in POWER8:Kit Barton2015-03-035-10/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | vaddudm vsubudm vmulesw vmulosw vmuleuw vmulouw vmuluwm vmaxsd vmaxud vminsd vminud vcmpequd vcmpequd. vcmpgtsd vcmpgtsd. vcmpgtud vcmpgtud. vrld vsld vsrd vsrad Phabricator review: http://reviews.llvm.org/D7959 llvm-svn: 231115
* Remove explicit no-op dtor in favor of the implicit dtor so as not to ↵David Blaikie2015-03-031-3/+0
| | | | | | disable/deprecate the copy operations. llvm-svn: 231113
* Add a comment above findRepresentativeClass explaining why it'sEric Christopher2015-03-031-0/+4
| | | | | | where it is so that future generations can understand. llvm-svn: 231111
* unique_ptrify FullDependenceAnalysis::DVDavid Blaikie2015-03-031-9/+5
| | | | | | | Making this type a little harder to abuse (see workaround relating to use of the implicit copy ctor in the prior commit) llvm-svn: 231104
* FullDependenceAnalysis: Avoid using the (deprecated in C++11) copy ctorDavid Blaikie2015-03-031-23/+22
| | | | llvm-svn: 231103
* Fix PR22750: non-determinism causes assertion failure in DWARF generationDario Domizioli2015-03-031-2/+5
| | | | | | | | | | | | | | | | | | | | | | | The cause of the issue is the interaction of two factors: 1) When generating a DW_TAG_imported_declaration DIE which imports another imported declaration, the code in AsmPrinter/DwarfCompileUnit.cpp asserts that the second imported declaration must already have a DIE. 2) There is a non-determinism in the order in which imported declarations within the same scope are processed. Because of the non-determinism (2), it is possible that an imported declaration is processed before another one it depends on, breaking the assumption in (1). The source of the non-determinism is that the imported declaration DIDescriptors are sorted by scope in DwarfDebug::beginModule(); however that sort is not a stable_sort, therefore the order of the declarations within the same scope is not preserved. The attached patch changes the std::sort to a std::stable_sort and it fixes the problem. Test omitted due to it being non-deterministic and depending on the implementation of std::sort. llvm-svn: 231100
* Make Triple::getOSVersion make sense for Android.Dan Albert2015-03-031-0/+8
| | | | | | | | | | | | Reviewers: srhines Reviewed By: srhines Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7928 llvm-svn: 231090
* 80-column fixup.Eric Christopher2015-03-031-1/+2
| | | | llvm-svn: 231088
* [AArch64] When combining constant mul of -3, prefer (sub x, (shl x, N)).Chad Rosier2015-03-031-9/+9
| | | | | | This change only effects codegen when the constant is -3. llvm-svn: 231085
* DebugInfo: Move new hierarchy into placeDuncan P. N. Exon Smith2015-03-034-1272/+297
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the specialized metadata nodes for the new debug info hierarchy into place, finishing off PR22464. I've done bootstraps (and all that) and I'm confident this commit is NFC as far as DWARF output is concerned. Let me know if I'm wrong :). The code changes are fairly mechanical: - Bumped the "Debug Info Version". - `DIBuilder` now creates the appropriate subclass of `MDNode`. - Subclasses of DIDescriptor now expect to hold their "MD" counterparts (e.g., `DIBasicType` expects `MDBasicType`). - Deleted a ton of dead code in `AsmWriter.cpp` and `DebugInfo.cpp` for printing comments. - Big update to LangRef to describe the nodes in the new hierarchy. Feel free to make it better. Testcase changes are enormous. There's an accompanying clang commit on its way. If you have out-of-tree debug info testcases, I just broke your build. - `upgrade-specialized-nodes.sh` is attached to PR22564. I used it to update all the IR testcases. - Unfortunately I failed to find way to script the updates to CHECK lines, so I updated all of these by hand. This was fairly painful, since the old CHECKs are difficult to reason about. That's one of the benefits of the new hierarchy. This work isn't quite finished, BTW. The `DIDescriptor` subclasses are almost empty wrappers, but not quite: they still have loose casting checks (see the `RETURN_FROM_RAW()` macro). Once they're completely gutted, I'll rename the "MD" classes to "DI" and kill the wrappers. I also expect to make a few schema changes now that it's easier to reason about everything. llvm-svn: 231082
* [X86][Haswell][SchedModel] Fix patterns for scalar FMA3 variants.Michael Kuperstein2015-03-031-2/+2
| | | | llvm-svn: 231073
* AVX-512: Moved patterns for masked load/store under avx_store, avx_load classes.Elena Demikhovsky2015-03-032-74/+94
| | | | | | No functional changes. llvm-svn: 231069
* During PHI elimination, split critical edges that move copies out of loops.Daniel Jasper2015-03-031-7/+13
| | | | | | | | | | | | | | | | | | | | This prevents the behavior observed in llvm.org/PR22369. I am not sure whether I am reading the code correctly, but the early exit based on isLiveOutPastPHIs() seems to make the wrong assumption that RegisterCoalescer won't be able to coalesce those copies later. This change hides the new behavior behind -no-phi-elim-live-out-early-exit as it currently breaks four tests: * Assertion in: CodeGen/Hexagon/hwloop-cleanup.ll * Worse code in: CodeGen/X86/coalescer-commute4.ll CodeGen/X86/phys_subreg_coalesce-2.ll CodeGen/X86/zlib-longest-match.ll The root cause here seems to be that the heuristic that determines the visitation order in RegisterCoalescer gets less lucky. llvm-svn: 231064
* Cleanup after r230934 per Dave's suggestions.Owen Anderson2015-03-031-3/+4
| | | | llvm-svn: 231056
* [X86] Remove some unused code from disassembler.Craig Topper2015-03-031-12/+0
| | | | llvm-svn: 231055
* [X86] Special-case 2x CMOV when custom-inserting.Ahmed Bougacha2015-03-031-7/+125
| | | | | | | | | | | | | | | | | | This lets us avoid a few copies that are otherwise hard to get rid of. The way this is done is, the custom-inserter looks at the following instruction for another CMOV, and replaces both at the same time. A previous version used a new CMOV2 opcode, but the custom inserter is expected to be able to return a different basic block anyway, which means it's OK - though far from ideal - to alter that block's contents. Explicitly document that, in case it ever makes a difference. Alternatives welcome! Follow-up to r231045. rdar://19767934 Closes http://reviews.llvm.org/D8019 llvm-svn: 231046
* [X86] Combine (cmov (and/or (setcc) (setcc))) into (cmov (cmov)).Ahmed Bougacha2015-03-031-0/+81
| | | | | | | | | | | | | | | | | | | Fold and/or of setcc's to double CMOV: (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2) (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2) When we can't use the CMOV instruction, it might increase branch mispredicts. When we can, or when there is no mispredict, this improves throughput and reduces register pressure. These can't be catched by generic combines, because the pattern can appear when legalizing some instructions (such as fcmp une). rdar://19767934 http://reviews.llvm.org/D7634 llvm-svn: 231045
* LowerBitSets: Use byte arrays instead of bit sets to represent in-memory bit ↵Peter Collingbourne2015-03-031-64/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sets. By loading from indexed offsets into a byte array and applying a mask, a program can test bits from the bit set with a relatively short instruction sequence. For example, suppose we have 15 bit sets to lay out: A (16 bits), B (15 bits), C (14 bits), D (13 bits), E (12 bits), F (11 bits), G (10 bits), H (9 bits), I (7 bits), J (6 bits), K (5 bits), L (4 bits), M (3 bits), N (2 bits), O (1 bit) These bits can be laid out in a 16-byte array like this: Byte Offset 0123456789ABCDEF Bit 7 HHHHHHHHHIIIIIII 6 GGGGGGGGGGJJJJJJ 5 FFFFFFFFFFFKKKKK 4 EEEEEEEEEEEELLLL 3 DDDDDDDDDDDDDMMM 2 CCCCCCCCCCCCCCNN 1 BBBBBBBBBBBBBBBO 0 AAAAAAAAAAAAAAAA For example, to test bit X of A, we evaluate ((bits[X] & 1) != 0), or to test bit X of I, we evaluate ((bits[9 + X] & 0x80) != 0). This can be done in 1-2 machine instructions on x86, or 4-6 instructions on ARM. This uses the LPT multiprocessor scheduling algorithm to lay out the bits efficiently. Saves ~450KB of instructions in a recent build of Chromium. Differential Revision: http://reviews.llvm.org/D7954 llvm-svn: 231043
* Remap arguments and non-alloca values used by outlined C++ exception handlers.Andrew Kaylor2015-03-031-40/+76
| | | | | | Differential Revision: http://reviews.llvm.org/D7844 llvm-svn: 231042
* LoopIdiom: Give globals for memset_pattern16 private linkage.Benjamin Kramer2015-03-031-1/+1
| | | | | | | | There's really no reason to have them have entries in the symbol table anymore. Old versions of ld64 had some bugs in this area but those have been fixed long ago. llvm-svn: 231041
* TLI: Factor out sanitizeFunctionName. NFC.Michael Zolotukhin2015-03-021-6/+14
| | | | llvm-svn: 231034
* Revert "Revert "For the dwarf expression code get the subtarget off of the ↵Adrian Prantl2015-03-022-6/+8
| | | | | | | | current"" This reapplies r230990 without modifications. llvm-svn: 231024
* Refactor DebugLocDWARFExpression so it doesn't require access to theAdrian Prantl2015-03-028-137/+175
| | | | | | | | | | | | | | TargetRegisterInfo. DebugLocEntry now holds a buffer with the raw bytes of the pre-calculated DWARF expression. Ought to be NFC, but it does slightly alter the output format of the textual assembly. This reapplies 230930 without the assertion in DebugLocEntry::finalize() because not all Machine registers can be lowered into DWARF register numbers and floating point constants cannot be expressed. llvm-svn: 231023
* Revert some changes that were made to fix PR20680.Sanjoy Das2015-03-021-42/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | This re-lands change r230921. r230921 was reverted because it broke a clang test; a checkin fixing the clang test will be commited shortly. Summary: As far as I can tell, the real bug causing the issue was fixed in r230533. SCEVExpander should mark an increment operation as nuw or nsw only if it can *prove* that the operation does not overflow. There shouldn't be any situation where we have to do something different because of no-wrap flags generated by SCEVExpander. Revert "IndVarSimplify: Allow LFTR to fire more often" This reverts commit 1ade0f0faa98877b688e0b9da58e876052c1e04e (SVN: 222213). Revert "IndVarSimplify: Don't let LFTR compare against a poison value" This reverts commit c0f2b8b528d8a37b0a1522aae90af649d6357eb5 (SVN: 217102). Reviewers: majnemer, atrick, spatel Differential Revision: http://reviews.llvm.org/D7979 llvm-svn: 231018
* Use read{16,32,64}{le,be}() instead of ↵Rui Ueyama2015-03-024-44/+31
| | | | | | *reinterpret_cast<u{little,big}{16,32,64}_t>(). llvm-svn: 231016
* TLI: Use lambda. NFC.Michael Zolotukhin2015-03-021-20/+4
| | | | llvm-svn: 231011
* Make ToVectorTy static.Michael Zolotukhin2015-03-021-11/+9
| | | | llvm-svn: 231007
* Revert "Refactor DebugLocDWARFExpression so it doesn't require access to the"Adrian Prantl2015-03-028-165/+125
| | | | | | This reverts commit 230975 to investigate buildbot breakage. llvm-svn: 231004
* Revert "For the dwarf expression code get the subtarget off of the current"Adrian Prantl2015-03-022-8/+6
| | | | | | This reverts commit 230990 because also reverting 230975. llvm-svn: 231003
* Remove useless .debug_macinfo section setup.Paul Robinson2015-03-023-16/+0
| | | | llvm-svn: 231001
* For the dwarf expression code get the subtarget off of the currentEric Christopher2015-03-022-6/+8
| | | | | | MachineFunction. llvm-svn: 230990
* Restore LLVMLinkModules C API until it is properly deprecated.Juergen Ributzka2015-03-021-1/+1
| | | | | | | | | | | Add the enum "LLVMLinkerMode" back for backwards-compatibility and add the linker mode parameter back to the "LLVMLinkModules" function. The paramter is ignored and has no effect. Patch provided by: Filip Pizlo Reviewed by: Rafael and Sean llvm-svn: 230988
* R600: Use c++11 style for loopJan Vesely2015-03-021-6/+4
| | | | | | Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <tom@stellard.net> llvm-svn: 230987
* Revert r230979, should apply to all X86 ELF.Paul Robinson2015-03-023-13/+0
| | | | llvm-svn: 230985
* [PS4] Correct relocation for DWARF TLS references.Paul Robinson2015-03-023-0/+13
| | | | llvm-svn: 230979
* Detect malformed YAML sequence in yaml::Input::beginSequence()Justin Bogner2015-03-021-7/+10
| | | | | | | | | | | | | | | | | | | | | When reading a yaml::SequenceTraits object, YAMLIO does not report an error if the yaml item is not a sequence. Instead, YAMLIO reads an empty sequence. For example: --- seq: foo: 1 bar: 2 ... If `seq` is a SequenceTraits object, then reading the above yaml will yield `seq` as an empty sequence. Fix this to report an error for the above mapping ("not a sequence") Patch by William Fisher. Thanks! llvm-svn: 230976
* Refactor DebugLocDWARFExpression so it doesn't require access to theAdrian Prantl2015-03-028-125/+165
| | | | | | | | | | | | | TargetRegisterInfo. DebugLocEntry now holds a buffer with the raw bytes of the pre-calculated DWARF expression. Ought to be NFC, but it does slightly alter the output format of the textual assembly. This reapplies 230930 with a relaxed assertion in DebugLocEntry::finalize() that allows for empty DWARF expressions for constant FP values. llvm-svn: 230975
* Accidentaly inverted the condition again. Sorry.Benjamin Kramer2015-03-021-1/+1
| | | | llvm-svn: 230973
* Avoid assertion in MSVC 2013 debug builds.Benjamin Kramer2015-03-021-1/+1
| | | | llvm-svn: 230972
* AsmWriter: Only print one space after the load typeBenjamin Kramer2015-03-021-1/+1
| | | | | | | | | Before: %x = load i32, i32* %i After: %x = load i32, i32* %i Purely cosmetic, so no new test case. llvm-svn: 230966
* SLPVectorizer: Rewrite ArrayRef slice compare to be more idiomatic.Benjamin Kramer2015-03-021-9/+5
| | | | | | NFC intended. llvm-svn: 230965
* AVX-512: Add assembly parser support for Rounding modeElena Demikhovsky2015-03-023-2/+53
| | | | | | By Asaf Badouh <asaf.badouh@intel.com> llvm-svn: 230962
* NVPTX: Remove dead code.Benjamin Kramer2015-03-023-116/+0
| | | | | | | Fun fact: This file was never referenced since the initial checkin of the NVPTX backend. llvm-svn: 230957
* [mips] Optimize conditional moves where RHS is zero.Vasileios Kalintiris2015-03-021-0/+32
| | | | | | | | | | | | | Summary: When the RHS of a conditional move node is zero, we can utilize the $zero register by inverting the conditional move instruction and by swapping the order of its True/False operands. Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D7945 llvm-svn: 230956
* AVX-512: Simplified MOV patterns, no functional changes.Elena Demikhovsky2015-03-021-158/+142
| | | | llvm-svn: 230954
* Simplify code. NFC.Benjamin Kramer2015-03-022-15/+5
| | | | llvm-svn: 230948
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