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* DebugInfo: Do not delay attaching DW_AT_inline attribute to abstract ↵David Blaikie2014-05-142-18/+5
| | | | | | | | | | definitions. This is just unneccessary - we only create abstract definitions when we're inlining anyway, so there's no reason to delay this to see if we're going to inline anything. llvm-svn: 208798
* ARM-BE: test files for vector argument passingChristian Pirker2014-05-141-1/+2
| | | | | | Reviewed at http://reviews.llvm.org/D3766 llvm-svn: 208793
* [ARM64-BE] Fix byte order of CIE and FDE frames for exception handlingChristian Pirker2014-05-141-0/+17
| | | | | | Reviewed at http://reviews.llvm.org/D3741 llvm-svn: 208792
* Fix ARM EHABI when function has landingpad and nounwind.Logan Chien2014-05-141-8/+7
| | | | | | | | | | | | | | | | | | | | If the function has the landingpad instruction, then the handlerdata should be emitted even if the function has nouwnind attribute. Otherwise, following code will not work: void test1() noexcept { try { throw_exception(); } catch (...) { log_unexpected_exception(); } } Since the cantunwind was incorrectly emitted and the LSDA is not available. llvm-svn: 208791
* X86: If we have an instruction that sets a flag and a zero test on the input ↵Benjamin Kramer2014-05-141-3/+63
| | | | | | | | | | | | | | | | | | | | | of that instruction try to eliminate the test. For example tzcntl %edi, %ebx testl %edi, %edi je .label can be rewritten into tzcntl %edi, %ebx jb .label A minor complication is that tzcnt sets CF instead of ZF when the input is zero, we have to rewrite users of the flags from ZF to CF. Currently we recognize patterns using lzcnt, tzcnt and popcnt. Differential Revision: http://reviews.llvm.org/D3454 llvm-svn: 208788
* [mips][mips64r6] Add sel.s and sel.dDaniel Sanders2014-05-142-4/+52
| | | | | | | | | | | | | | | Summary: Also use named constants for common opcode fields. Depends on D3669 Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3670 llvm-svn: 208784
* ARM64: remove unneeded InstPrinter hacksTim Northover2014-05-141-32/+0
| | | | | | | Now that TableGen handles aliases, these are unneeded. Hopefully more will be able to go soon. llvm-svn: 208781
* [asan] Fix compiler warnings.Evgeniy Stepanov2014-05-141-5/+3
| | | | llvm-svn: 208769
* [asan] Set debug location in ASan function prologue.Evgeniy Stepanov2014-05-141-2/+14
| | | | | | | | | Most importantly, it gives debug location info to the coverage callback. This change also removes 2 cases of unnecessary setDebugLoc when IRBuilder is created with the same debug location. llvm-svn: 208767
* Fix the case when reordering shuffle and binop produces a constant.Serge Pavlov2014-05-141-13/+13
| | | | | | This resolves PR19737. llvm-svn: 208762
* Update the comments for ComputeMaskedBits, which lost its Mask parameterJay Foad2014-05-142-5/+4
| | | | | | in r154011. llvm-svn: 208757
* [obj2yaml] Support ELF input format in the obj2yaml tool.Simon Atanasyan2014-05-141-1/+2
| | | | | | | | | | The ELF header e_flags field in the MIPS related test cases handled incorrectly. The obj2yaml prints too many flags. I will fix that in the next patches. The patch reviewed by Michael Spencer and Sean Silva. llvm-svn: 208752
* ARM: implement support for the UDF mnemonicSaleem Abdulrasool2014-05-144-2/+37
| | | | | | | | | | | | | | The UDF instruction is a reserved undefined instruction space. The assembler mnemonic was introduced with ARM ARM rev C.a. The instruction is not predicated and the immediate constant is ignored by the CPU. Add support for the three encodings for this instruction. The changes to the invalid instruction test is due to the fact that the invalid instructions actually overlap with the undefined instruction. Introduction of the new instruction results in a partial decode as an undefined sequence. Drop the tests as they are invalid instruction patterns anyways. llvm-svn: 208751
* Optimize integral reciprocal (udiv 1, x and sdiv 1, x) to not use division. ↵Nick Lewycky2014-05-141-1/+20
| | | | | | This fires exactly once in a clang bootstrap, but covers a few different results from http://www.cs.utah.edu/~regehr/souper/ llvm-svn: 208750
* Recommit r208506: DebugInfo: Include lexical scopes in inlined subroutines.David Blaikie2014-05-142-17/+34
| | | | | | | | | | | | | | | | | | | | This was reverted in r208642 due to regressions surrounding file changes within lexical scopes causing inlining information to be lost. The issue was in LexicalScopes::getOrCreateInlinedScope, where I was previously testing "isLexicalBlock" which is false for "DILexicalBlockFile" (a scope used to represent changes in the current file name) and assuming it was then a function (breaking out of the inlined scope path and reaching for the parent non-inlined scopes). By inverting the condition and testing for "isSubprogram" the correct behavior is attained. (also found some weirdness in Clang, see r208742 when reducing this test case - the resulting test case doesn't apply with the Clang fix, but I've added a more realistic test case to inline-scopes.ll which does reproduce the issue and demonstrate the fix) llvm-svn: 208748
* Fix typo in function name.Eric Christopher2014-05-141-5/+5
| | | | llvm-svn: 208743
* R600/SI: Try to fix BFE operands when moving to VALUMatt Arsenault2014-05-131-1/+1
| | | | | | This was broken by r208479 llvm-svn: 208740
* [RuntimeDyld] Fix handling of i386 PC-rel external relocations. This fixesLang Hames2014-05-131-0/+11
| | | | | | | | several more i386 MCJIT regression test failures. <rdar://problem/16889891> llvm-svn: 208735
* Add missing line breaks to debug output in CodeGenPrepareLouis Gerbarg2014-05-131-3/+3
| | | | llvm-svn: 208731
* GVN: Fix non-determinism in map iteration.Benjamin Kramer2014-05-131-4/+7
| | | | | | | | | Iterating over a DenseMaop is non-deterministic and results to unpredictable IR output. Based on a patch by Daniel Reynaud! llvm-svn: 208728
* GVN: rangify a couple of loops.Benjamin Kramer2014-05-131-13/+9
| | | | | | No functionality change. llvm-svn: 208727
* Save the optimization level the subtarget was created with in aEric Christopher2014-05-132-15/+14
| | | | | | | | | | member variable and sink the initialization of crbits into the subtarget feature reset code. No functional change, but this refactor will be used in a future commit. llvm-svn: 208726
* Make the split function use StringRef::split.Eric Christopher2014-05-131-19/+3
| | | | llvm-svn: 208723
* Split GlobalValue into GlobalValue and GlobalObject.Rafael Espindola2014-05-136-42/+39
| | | | | | | | | This allows code to statically accept a Function or a GlobalVariable, but not an alias. This is already a cleanup by itself IMHO, but the main reason for it is that it gives a lot more confidence that the refactoring to fix the design of GlobalAlias is correct. That will be a followup patch. llvm-svn: 208716
* Check explicitly for EHABI and just use the default settings.Joerg Sonnenberger2014-05-131-0/+4
| | | | | | Code depends on the assembler and linker to fix things up... llvm-svn: 208715
* ARMEB: Fix byte order of EH frame unwinding instructions, with modified test ↵Christian Pirker2014-05-131-4/+14
| | | | | | | | | | | | file This commit was already commited as revision rL208689 and discussd in phabricator revision D3704. But the test file was crashing on OS X and windows. I fixed the test file in the same way as in rL208340. llvm-svn: 208711
* [CGP] r205941 changed the logic, so that a cast happens *before* 'Result' isJoey Gouly2014-05-131-1/+1
| | | | | | | | | | | compared to 'AddrMode.BaseReg'. In the case that 'AddrMode.BaseReg' is nullptr, 'Result' will also be nullptr, so the cast causes an assertion. We should use dyn_cast_or_null here to check 'Result' is not null and it is an instruction. Bug found by Mats Petersson, and I reduced his IR to get a test case. llvm-svn: 208705
* Revert "ARMEB: Fix byte order of EH frame unwinding instructions"Rafael Espindola2014-05-131-14/+4
| | | | | | | | This reverts commit r208689. The test was crashing on OS X and windows. llvm-svn: 208704
* [mips] Marked up instructions added in MIPS32r2 and tested that IAS for ↵Daniel Sanders2014-05-137-21/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | -mcpu=mips(2|32) does not accept them Summary: This required a new instruction group representing the 32-bit subset of MIPS-3 that was available in MIPS32R2. To limit the number of tests required, only one 32-bit and one 64-bit ISA prior to MIPS32/MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3696 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3697 llvm-svn: 208690
* ARMEB: Fix byte order of EH frame unwinding instructionsChristian Pirker2014-05-131-4/+14
| | | | llvm-svn: 208689
* [mips] Free up two values in SubtargetFeatureFlag by folding the redundant ↵Daniel Sanders2014-05-132-6/+5
| | | | | | | | | | | | | | | | | | | | | IsGP32/IsGP64 into IsGP32bit/IsGP64bit Summary: We are currently very close to the 32-bit limit of the current assembler implementation. This is because there is no way to represent an instruction that is available in, for example, Mips3 or Mips32. We have to define a feature bit that represents this. This patch cleans up a pair of redundant feature bits and slightly postpones the point we will reach the limit. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3703 llvm-svn: 208685
* [un]wrap extracted from lib/Target/Target[MachineC].cpp, ↵Artyom Skrobov2014-05-133-33/+0
| | | | | | lib/ExecutionEngine/ExecutionEngineBindings.cpp into include/llvm/IR/DataLayout.h llvm-svn: 208680
* [ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg ↵Kevin Qin2014-05-132-11/+8
| | | | | | | | | addressing mode. A vague diagnostic replaced the misleading one. This can fix bug 19502. llvm-svn: 208669
* Fix type of shuffle resulted from shuffle merge.Serge Pavlov2014-05-131-6/+4
| | | | | | This fix resolves PR19730. llvm-svn: 208666
* Assert that we don't RAUW a Constant with a ConstantExpr that contains it.Rafael Espindola2014-05-131-1/+36
| | | | | | | | We already had an assert for foo->RAUW(foo), but not for something like foo->RAUW(GEP(foo)) and would go in an infinite loop trying to apply the replacement. llvm-svn: 208663
* Folding into CSEL when there is ZEXT between SETCC and ADDWeiming Zhao2014-05-131-3/+11
| | | | | | | | | | | Normally, patterns like (add x, (setcc cc ...)) will be folded into (csel x, x+1, not cc). However, if there is a ZEXT after SETCC, they won't be folded. This patch recognizes the ZEXT and allows the generation of CSINC. This patch fixes bug 19680. llvm-svn: 208660
* Revert "DebugInfo: Include lexical scopes in inlined subroutines."David Blaikie2014-05-122-35/+17
| | | | | | | | | This reverts commit r208506. Some inlined subroutine scopes appear to be missing with this change. Reverting while I investigate. llvm-svn: 208642
* Use a logical not when inverting SetCC. This unfortunately doesn't fire on ↵Pete Cooper2014-05-122-3/+19
| | | | | | | | | | | | any targets so I couldn't find a test case to trigger it. The problem occurs when a non-i1 setcc is inverted. For example 'i8 = setcc' will get 'xor 0xff' to invert this. This is clearly wrong when the boolean contents are ZeroOrOne. This patch introduces getLogicalNOT and updates SetCC legalisation to use it. Reviewed by Hal Finkel. llvm-svn: 208641
* [DAGCombiner] Split up an indexed load if only the base pointer value is liveAdam Nemet2014-05-121-7/+30
| | | | | | | | | | | | | | | | | | | | Right now the load may not get DCE'd because of the side-effect of updating the base pointer. This can happen if we lower a read-modify-write of an illegal larger type (e.g. i48) such that the modification only affects one of the subparts (the lower i32 part but not the higher i16 part). See the testcase. In order to spot the dead load we need to revisit it when SimplifyDemandedBits decided that the value of the load is masked off. This is the CommitTargetLoweringOpt piece. I checked compile time with ARM64 by sending SPEC bitcode files through llc. No measurable change. Fixes <rdar://problem/16031651> llvm-svn: 208640
* Try to fix an SDAG dependence issue with sretReid Kleckner2014-05-122-18/+23
| | | | | | | | | | | | | | | | r208453 added support for having sret on the second parameter. In that change, the code for copying sret into a virtual register was hoisted into the loop that lowers formal parameters. This caused a "Wrong topological sorting" assertion failure during scheduling when a parameter is passed in memory. This change undoes that by creating a second loop that deals with sret. I'm worried that this fix is incomplete. I don't fully understand the dependence issues. However, with this change we produce the same DAGs we used to produce, so if they are broken, they are just as broken as they have always been. llvm-svn: 208637
* DebugInfo: Attach DW_AT_inline to inlined subprograms at DIE-construction ↵David Blaikie2014-05-121-4/+1
| | | | | | time rather than as a post-processing step. llvm-svn: 208636
* [RuntimeDyld] Add support for MachO __jump_table and __pointers sections, andLang Hames2014-05-127-23/+242
| | | | | | | | | | | SECTDIFF relocations on 32-bit x86. This fixes several of the MCJIT regression test failures that show up on 32-bit builds. <rdar://problem/16886294> llvm-svn: 208635
* Use cast<> for unchecked useMatt Arsenault2014-05-121-1/+1
| | | | llvm-svn: 208627
* use nullptr instead of NULLSebastian Pop2014-05-121-4/+4
| | | | llvm-svn: 208622
* Add support bswap16 to/from memory compiling to rev16 on ARM/ThumbLouis Gerbarg2014-05-122-0/+17
| | | | | | | | | | | The current patterns for REV16 misses mostn __builtin_bswap16() due to legalization promoting the operands to from load/stores toi32s and then truncing/extending them. This patch adds new patterns that catch the resultant DAGs and codegens them to rev16 instructions. Tests included. rdar://15353652 llvm-svn: 208620
* Use cast<> for unchecked useMatt Arsenault2014-05-121-2/+2
| | | | llvm-svn: 208618
* Use range forMatt Arsenault2014-05-122-6/+4
| | | | llvm-svn: 208617
* do not assert when delinearization failsSebastian Pop2014-05-121-8/+30
| | | | llvm-svn: 208615
* use isZero()Sebastian Pop2014-05-121-6/+5
| | | | llvm-svn: 208614
* DwarfDebug: Avoid an extra map lookup while constructing abstract scope DIEs ↵David Blaikie2014-05-121-19/+20
| | | | | | | | | | and reduce nesting/conditionals. One test case had to be updated as it still had the extra indirection for the variable list - removing the extra indirection got it back to passing. llvm-svn: 208608
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