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* [profile] Fix binary format reader error propagation.Mircea Trofin2018-04-131-5/+5
| | | | | | | | | | | | | | | | Summary: This was originally part of rL328132, and led to the discovery of the issues addressed in rL328987. Re-landing. Reviewers: xur, davidxl, bkramer Reviewed By: bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45545 llvm-svn: 330029
* Remove comment reference to itineraries. NFCI.Simon Pilgrim2018-04-131-1/+1
| | | | llvm-svn: 330025
* [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+imm) load instructionsSander de Smalen2018-04-133-0/+64
| | | | | | | | | | | | Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45618 llvm-svn: 330024
* [X86][AVX512] UNPCKL/H PS and PD should be scheduled with WriteFShuffle not ↵Simon Pilgrim2018-04-131-2/+2
| | | | | | WriteFAdd llvm-svn: 330023
* [X86] Remove remaining OpndItins/SizeItins from all instruction defs (PR37093)Simon Pilgrim2018-04-132-1715/+1301
| | | | llvm-svn: 330022
* Remove comment references to itineraries. NFCI.Simon Pilgrim2018-04-133-4/+4
| | | | llvm-svn: 330021
* Remove out of data comment. NFCI.Simon Pilgrim2018-04-131-2/+1
| | | | llvm-svn: 330019
* [PostRASink]Add register dependency check for implicit operandsJun Bum Lim2018-04-131-23/+103
| | | | | | | | | | | | | | | | Summary: This change extend the register dependency check for implicit operands in Copy instructions. Fixes PR36902. Reviewers: thegameg, sebpop, uweigand, jnspaulsson, gberry, mcrosier, qcolombet, MatzeB Reviewed By: thegameg Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44958 llvm-svn: 330018
* [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.Sander de Smalen2018-04-133-1/+107
| | | | | | | | | | | | | | | | | | | | Summary: Added instructions for contiguous stores, ST1, with scalar+imm addressing modes and corresponding tests. The patch also adds parsing of 'mul vl' as needed for the VL-scaled immediate. This is patch [6/6] in a series to add assembler/disassembler support for SVE's contiguous ST1 (scalar+imm) instructions. Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: rengolin Subscribers: tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45432 llvm-svn: 330014
* [X86] Remove OpndItins/SizeItins from all sse instruction defs (PR37093)Simon Pilgrim2018-04-132-622/+566
| | | | llvm-svn: 330013
* [NEON] Support intrinsic for scalar and vector versions of the VRINTN ↵Ivan A. Kosarev2018-04-131-1/+1
| | | | | | | | instruction Differential Revision: https://reviews.llvm.org/D45514 llvm-svn: 330011
* [NFC] fix trivial typos in commentsHiroshi Inoue2018-04-135-5/+5
| | | | | | "the the" -> "the", "we we" -> "we", etc llvm-svn: 330006
* [InstCombine]: foldSelectICmpAndAnd(): and is commutativeRoman Lebedev2018-04-131-24/+20
| | | | | | | | | | | | | | | | | | | | | Summary: The fold added in D45108 did not account for the fact that the and instruction is commutative, and if the mask is a variable, the mask variable and the fold variable may be swapped. I have noticed this by accident when looking into [[ https://bugs.llvm.org/show_bug.cgi?id=6773 | PR6773 ]] This extends/generalizes that fold, so it is handled too. Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45539 llvm-svn: 330001
* [AArch64][SVE] Asm: Add support for parsing and printing SVE vector lists.Sander de Smalen2018-04-133-2/+78
| | | | | | | | | | | | | | | | | | | Summary: Added Z_(b|h|s|d) vector list RegisterOperands along with support to add/print the vector lists. This is patch [5/6] in a series to add assembler/disassembler support for SVE's contiguous ST1 (scalar+imm) instructions. Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: fhahn Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45431 llvm-svn: 330000
* [X86] Introduce cldemote instructionGabor Buella2018-04-135-0/+12
| | | | | | | | | | | | | | Hint to hardware to move the cache line containing the address to a more distant level of the cache without writing back to memory. Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45256 llvm-svn: 329992
* [Support] Fix building for Windows on ARMMartin Storsjo2018-04-131-1/+9
| | | | | | | | | | | The commit in SVN r310001 that added support for this actually didn't use the right struct field for the frame pointer - for ARM, there is no register named Fp in the CONTEXT struct. On Windows, the R11 register is used as frame pointer. Differential Revision: https://reviews.llvm.org/D45590 llvm-svn: 329991
* [X86] Remove the pmuldq/pmuldq intrinsics and replace with native IR.Craig Topper2018-04-134-134/+45
| | | | | | | | This completes the work started in r329604 and r329605 when we changed clang to no longer use the intrinsics. We lost some InstCombine SimplifyDemandedBit optimizations through this change as we aren't able to fold 'and', bitcast, shuffle very well. llvm-svn: 329990
* Enable debug fission for thinLTO linked via gold-pluginYunlian Jiang2018-04-132-0/+68
| | | | | | | | | | | | | | Summary: This enables debug fission on implicit ThinLTO when linked with gold. It will put the .dwo files in a directory specified by user. Reviewers: tejohnson, pcc, dblaikie Reviewed By: pcc Subscribers: JDevlieghere, mehdi_amini, inglorion Differential Revision: https://reviews.llvm.org/D44792 llvm-svn: 329988
* [CallSiteSplit] Fix comment. NFCXin Tong2018-04-131-1/+1
| | | | llvm-svn: 329987
* [X86] Remove unused MoveLoadStoreItins/ShiftOpndItins schedule class wrappers.Simon Pilgrim2018-04-122-36/+14
| | | | | | Was being used to move around empty/unused itineraries... llvm-svn: 329970
* [X86] Remove x86 InstrItinClass entries (PR37093)Simon Pilgrim2018-04-123-241/+94
| | | | | | This removes the last of the x86 schedule itineraries, I'm intending to cleanup the remaining uses of NoItinerary/OpndItins/etc. before resolving PR37093. llvm-svn: 329967
* [DAGCombiner] simplify code; NFCSanjay Patel2018-04-121-3/+2
| | | | llvm-svn: 329964
* Don't call skipModule for CFI lowering passes.Eli Friedman2018-04-122-5/+0
| | | | | | | opt-bisect shouldn't skip these passes; they lower intrinsics which no other pass can handle. llvm-svn: 329961
* [ProfileSummary] Remove repeated cutoffs; NFCIGeorge Burgess IV2018-04-121-2/+2
| | | | | | | I'm told the repeat of "500000, 600000," is accidental, and should be removed. llvm-svn: 329959
* AArch64: Introduce a DAG combine for folding offsets into addresses.Peter Collingbourne2018-04-122-15/+68
| | | | | | | | | | | This is a code size win in code that takes offseted addresses frequently, such as C++ constructors that typically need to compute an offseted address of a vtable. This reduces the size of Chromium for Android's .text section by 108KB. Differential Revision: https://reviews.llvm.org/D45199 llvm-svn: 329956
* [DebugInfo] Create merged locations for instructions other than callsVedant Kumar2018-04-122-5/+6
| | | | | | | | | | | | | | | | | | This lifts a restriction on DILocation::getMergedLocation(), allowing it to create merged locations for instructions other than calls. Instruction::applyMergedLocation() now defaults to creating merged locations for all instructions. The default behavior of getMergedLocation() is unchanged: callers which invoke it directly are unaffected. This change will enable a follow-up Mem2Reg fix which improves crash reporting. Differential Revision: https://reviews.llvm.org/D45396 llvm-svn: 329955
* [ProfileSummary] Move a vector we're about to destroy anyway; NFCGeorge Burgess IV2018-04-121-3/+3
| | | | llvm-svn: 329954
* [X86] Remove InstrItinClass entries from all x86 instruction defs (PR37093)Simon Pilgrim2018-04-123-318/+284
| | | | llvm-svn: 329953
* [demangler] Add a partial demangling API for LLDB.Erik Pilkington2018-04-121-0/+191
| | | | | | | | | | This parses a mangled name into an AST (typically an intermediate stage in itaniumDemangle) and provides some functions to query certain properties or print certain parts of the demangled name. Differential revision: https://reviews.llvm.org/D44668 llvm-svn: 329951
* [demangler] NFC: Some refactoring to support partial demangling.Erik Pilkington2018-04-121-42/+97
| | | | | | | I'm committing this to libcxxabi too so that the two demanglers remain as simular as possible. llvm-svn: 329950
* [WebAssembly] libObject: Don't include the name the size of custom sectionsSam Clegg2018-04-121-1/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D45579 llvm-svn: 329947
* [X86] Remove InstrItinClass entries from SSE/AVX instructions defs (PR37093)Simon Pilgrim2018-04-122-521/+498
| | | | llvm-svn: 329945
* [ORC] Use insert rather than emplace.Lang Hames2018-04-121-19/+19
| | | | | | | Hopefully this will fix the build failure at http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/9028 llvm-svn: 329944
* Simplify; NFCIGeorge Burgess IV2018-04-121-18/+12
| | | | llvm-svn: 329943
* [X86] Remove explicit SSE/AVX schedule itineraries from defs (PR37093)Simon Pilgrim2018-04-123-526/+463
| | | | llvm-svn: 329940
* [RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0Sameer AbuAsal2018-04-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: GCC compresses the pseudo instruction "mv rd, rs", which is an alias of "addi rd, rs, 0", to "c.mv rd, rs". In LLVM we rely on the canonical MC instruction (MCInst) to do our compression checks and since there is no rule to compress "addi rd, rs, 0" --> "c.mv rd, rs" we lose this compression opportunity to gcc. In this patch we fix that by adding an addi to c.mv compression pattern, the instruction "mv rd, rs" will be compressed to "c.mv rd, rs" just like gcc does. Patch by Zhaoshi Zheng (zzheng) and Sameer (sabuasal). Reviewers: asb, apazos, zzheng, mgrang, shiva0217 Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, llvm-commits Differential Revision: https://reviews.llvm.org/D45583 llvm-svn: 329939
* [X86] Remove remaining gpr schedule itineraries (PR37093)Simon Pilgrim2018-04-124-353/+226
| | | | llvm-svn: 329938
* [X86] Introduce LLVM wbinvd intrinsicGabor Buella2018-04-121-1/+1
| | | | | | | | | | | | A previously missing intrinsic for an old instruction. Reviewers: craig.topper, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45312 llvm-svn: 329936
* Fix a typo in a comment; NFCGeorge Burgess IV2018-04-121-1/+1
| | | | llvm-svn: 329935
* [ORC] Plumb error notifications through the VSO interface.Lang Hames2018-04-124-203/+327
| | | | | | | This allows materializers to notify the VSO that they were unable to resolve or finalize symbols. llvm-svn: 329934
* [X86] Remove gpr shift/extension schedule itineraries (PR37093)Simon Pilgrim2018-04-123-343/+270
| | | | llvm-svn: 329933
* [Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-PrecisionLei Huang2018-04-122-1/+22
| | | | | | | | | | | Legalize and emit code for: * xscvsdqp * xscvudqp Differential Revision: https://reviews.llvm.org/D45230 llvm-svn: 329931
* [MCJIT] Remove the anchor from mcjit.Benjamin Kramer2018-04-121-2/+0
| | | | | | | This is a layering violation. LTO shouldn't depend on MCJIT. The right fix for this is moving the class somewhere else. llvm-svn: 329929
* [MIPS GlobalISel] remove superfluous #includes (NFC)Petar Jovanovic2018-04-125-14/+1
| | | | | | | Remove superfluous #includes. Minor code style change in MipsCallLowering::lowerFormalArguments(). llvm-svn: 329926
* [AArch64] Move AFI->setRedZone(false) to top of emitPrologueJessica Paquette2018-04-121-1/+5
| | | | | | | | | | | | | AFI->setRedZone(false) was put in the wrong place before, and so it only fired on functions that didn't have stack frames. This moves that to the top of emitPrologue to make sure that every function without a redzone has it set correctly. This also adds a function representing one of the early exit cases (GHC calling convention) to the MachineOutliner noredzone test to ensure that we can outline from functions like these, where we never use a redzone. llvm-svn: 329922
* revert r328921 - [DAGCombine] (float)((int) f) --> ftrunc (PR36617)Sanjay Patel2018-04-121-18/+0
| | | | | | | This change is exposing UB in source code - as was warned/predicted. :) See D44909 for discussion. Reverting while we figure out how to fix things. llvm-svn: 329920
* [Pipeliner] Use std::stable_sort when ordering NodeSetsKrzysztof Parzyszek2018-04-121-1/+1
| | | | | | | | | | | There are cases when individual NodeSets can be equal with respect to the ordering criteria. Since they are stored in an ordered container, use stable_sort to preserve the relative order of equal NodeSets. This should remove non-determinism discovered by shuffling done in llvm::sort with expensive checks enabled. llvm-svn: 329915
* [mips] Correct the predicates of the load/store (double)word for coprocessor 3.Simon Dardis2018-04-121-4/+6
| | | | llvm-svn: 329913
* [X86] Remove AES/CLMUL/CRC32/LDDQU/MOVNT/POPCNT/SHA schedule itineraries ↵Simon Pilgrim2018-04-124-100/+70
| | | | | | (PR37093) llvm-svn: 329912
* Revert "Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time."Benjamin Kramer2018-04-121-18/+13
| | | | | | This reverts commit r329865. Causes stage2/stage3 miscompare. llvm-svn: 329910
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