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* AMDGPU: Fix broken dynamic vector indexing for packed typesMatt Arsenault2018-05-081-4/+4
| | | | | | The intention of this was to multiply by 16, not shift by 16. llvm-svn: 331793
* DAG: Use correct shift width typeMatt Arsenault2018-05-081-1/+1
| | | | llvm-svn: 331792
* [Power9]Legalize and emit code for truncate and convert Quad-Precision to WordLei Huang2018-05-081-0/+10
| | | | | | | | | | | Legalize and emit code for: * xscvqpswz : VSX Scalar truncate & Convert Quad-Precision to Signed Word * xscvqpuwz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Word Differential Revision: https://reviews.llvm.org/D45635 llvm-svn: 331790
* AMDGPU: Use eraseFromParent to delete am instruction when it is no longer ↵Changpeng Fang2018-05-081-3/+6
| | | | | | | | | | | needed. Reviewer: Nicolai Differential Revision: https://reviews.llvm.org/D46438 llvm-svn: 331788
* [Power9]Legalize and emit code for truncate and convert QP to DWLei Huang2018-05-082-2/+27
| | | | | | | | | | | Legalize and emit code for: * xscvqpsdz : VSX Scalar truncate & Convert Quad-Precision to Signed Dword * xscvqpudz : VSX Scalar truncate & Convert Quad-Precision to Unsigned Dword Differential Revision: https://reviews.llvm.org/D45553 llvm-svn: 331787
* [CodeGenPrepare] Move Extension Instructions Through Logical And Shift ↵Guozhi Wei2018-05-081-0/+41
| | | | | | | | | | Instructions CodeGenPrepare pass move extension instructions close to load instructions in different BB, so they can be combined later. But the extension instructions can't move through logical and shift instructions in current implementation. This patch enables this enhancement, so we can eliminate more extension instructions. Differential Revision: https://reviews.llvm.org/D45537 llvm-svn: 331783
* [PowerPC] Unify handling for conversion of FP_TO_INT feeding a storeLei Huang2018-05-084-56/+149
| | | | | | | | | | | | Existing DAG combine only handles conversions for FP_TO_SINT: "{f32, f64} x { i32, i16 }" This patch simplifies the code to handle: "{ FP_TO_SINT, FP_TO_UINT } x { f64, f32 } x { i64, i32, i16, i8 }" Differential Revision: https://reviews.llvm.org/D46102 llvm-svn: 331778
* [AMDGPU] Added checks for dpp_ctrl valueStanislav Mekhanoshin2018-05-084-36/+99
| | | | | | | | | | | | - Report error for invalid dpp_ctrl values. - Changed the way it is reported, now the error will be emitted into asm and will work with release build as well. - Added dpp_ctrl value verifier for codegen. - Added symbolic constants for dpp_ctrl. Differential Revision: https://reviews.llvm.org/D46565 llvm-svn: 331775
* [X86] Tag PCONFIG instruction with WriteSystem scheduler classSimon Pilgrim2018-05-081-0/+2
| | | | llvm-svn: 331773
* [mips][msa] Pattern match the splat.d instructionStefan Maksimovic2018-05-082-11/+32
| | | | | | | | | | | Introduced a new pattern for matching splat.d explicitly. Both splat.d and splati.d can now be generated from the @llvm.mips.splat.d intrinsic depending on whether an immediate value has been passed. Differential Revision: https://reviews.llvm.org/D45683 llvm-svn: 331771
* [X86] Split off WriteIMul64 from WriteIMul schedule class (PR36931)Simon Pilgrim2018-05-0811-105/+84
| | | | | | | This fixes a couple of BtVer2 missing instructions that weren't been handled in the override. NOTE: There are still a lot of overrides that still need cleaning up! llvm-svn: 331770
* [X86] Split WriteIDiv into div/idiv 8/16/32/64 implementations (PR36930)Simon Pilgrim2018-05-0811-130/+113
| | | | | | | I've created the necessary classes but there are still a lot of overrides that need cleaning up. NOTE: The Znver1 model was missing some div/idiv variants in the instregex patterns and wasn't setting the resource cycles at all in the overrides. llvm-svn: 331767
* [X86] Add vector masked load/store scheduler classes (PR32857)Simon Pilgrim2018-05-0811-247/+163
| | | | | | Split off from existing vector load/store classes to remove InstRW overrides. llvm-svn: 331760
* [AArch64][SVE] Asm: Support for LD1R load-and-replicate scalar instructions.Sander de Smalen2018-05-084-1/+93
| | | | | | | | | | Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D46251 llvm-svn: 331758
* [X86] Add SchedWriteFTest/SchedWriteVecTest TEST scheduler classesSimon Pilgrim2018-05-0811-195/+75
| | | | | | Split off from SchedWriteVecLogic to remove InstRW overrides. llvm-svn: 331757
* [mips] Mark various memory instructions as being in microMIPS (NFC)Simon Dardis2018-05-081-10/+9
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46388 llvm-svn: 331756
* [AArch64] Disallow vector operand if FPR128 Q register is required.Sander de Smalen2018-05-083-206/+225
| | | | | | | | | | | | | | | | | | | | | | | | | Patch https://reviews.llvm.org/D41445 changed the behaviour of 'isReg()' to also return 'true' if the parsed register operand is a vector register. Code in the AsmMatcher checks if a register is a subclass of the expected register class. However, even though both parsed registers map to the same physical register, the 'v' register is of kind 'NeonVector', where 'q' is of type Scalar, where isSubclass() does not distinguish between the two cases. The solution is to use an AsmOperand instead of the register directly, and use the PredicateMethod to distinguish the two operands. This fixes for example: ldr v0, [x0] // 'v0' is an invalid operand for this instruction ldr q0, [x0] // valid Reviewers: aemerson, Gerolf, SjoerdMeijer, javed.absar Reviewed By: aemerson Differential Revision: https://reviews.llvm.org/D46310 llvm-svn: 331755
* [mips] Correct clo/clz predicatesSimon Dardis2018-05-082-22/+19
| | | | | | | | Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46125 llvm-svn: 331754
* [X86] Mark all byval parameters as aliasedJeremy Morse2018-05-081-1/+5
| | | | | | | | | | | | | | | This is a fix for PR30290: by marking all byval stack slots as being aliased, the instruction scheduler is more conservative about rescheduling memory accesses to such stack slots as an LLVM Value* might alias it. This fixes errors such as in the patched test case, where reads and writes to a data structure are illegally mixed. This could be fixed better in the future with better analysis for the instruction scheduler to know what Values alias what stack slots. Differential Revision: https://reviews.llvm.org/D45022 llvm-svn: 331749
* [X86][CET] Shadow stack fix for setjmp/longjmpAlexander Ivchenko2018-05-082-5/+251
| | | | | | | | | | | | This patch adds a shadow stack fix when compiling setjmp/longjmp with the shadow stack enabled. This allows setjmp/longjmp to work correctly with CET. Patch by mike.dvoretsky Differential Revision: https://reviews.llvm.org/D46181 llvm-svn: 331748
* Object: Find terminator correctly when reading long filenames in GNU ↵Hans Wennborg2018-05-081-4/+8
| | | | | | | | | | | | archives (PR37244) The code was previously relying on there being a null terminator somewhere in (or after) the string table, something made less likely by r330786. Differential Revision: https://reviews.llvm.org/D46527 llvm-svn: 331746
* [x86] Introduce the enclv instructionGabor Buella2018-05-083-1/+7
| | | | | | | | | | | | | | Summary: and use the -msgx flag as a requirement for the SGX instructions. Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46436 llvm-svn: 331742
* [LCSSA] Do not remove used PHI nodes in formLCSSAForInstructionsBjorn Pettersson2018-05-081-5/+10
| | | | | | | | | | | | | | | | | | | | | | | Summary: In formLCSSAForInstructions we speculatively add new PHI nodes, that sometimes ends up without having any uses. It has been discovered that sometimes an added PHI node can appear as being unused in one iteration of the Worklist, although it can end up being used by a PHI node added in a later iteration. We now check, a second time, that the PHI node still is unused before we remove it. This avoids an assert about "Trying to remove a phi with uses." for the added test case. Reviewers: davide, mzolotukhin, mattd, dberlin Reviewed By: mzolotukhin, dberlin Subscribers: dberlin, mzolotukhin, davide, bjope, uabelho, llvm-commits Differential Revision: https://reviews.llvm.org/D46422 llvm-svn: 331741
* [x86] Introduce the pconfig instructionGabor Buella2018-05-086-0/+38
| | | | | | | | | | Reviewers: craig.topper, zvi Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D46430 llvm-svn: 331739
* [DebugInfo] Accept `S` in augmentation strings in CIE.Fangrui Song2018-05-081-0/+3
| | | | | | glibc libc.a(sigaction.o) compiled from sysdeps/unix/sysv/linux/x86_64/sigaction.c uses "zRS". llvm-svn: 331738
* [MachineVerifier][GlobalISel] Verifying generic extends and truncatesRoman Tereshin2018-05-081-0/+52
| | | | | | | | | | | | | | | | | Making sure we don't truncate / extend pointers, don't try to change vector topology or bitcast vectors to scalars or back, and most importantly, don't extend to a smaller type or truncate to a large one. Reviewers: qcolombet t.p.northover aditya_nandakumar Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46490 llvm-svn: 331718
* [MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)Roman Tereshin2018-05-081-13/+20
| | | | | | | | | | | | | | MIParser wasn't able to parse LLTs like `<4 x p0>`, fixing that. Reviewers: qcolombet t.p.northover aditya_nandakumar Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46490 llvm-svn: 331712
* [NewPM] Emit inliner NoDefinition missed optimization remarkTeresa Johnson2018-05-081-1/+18
| | | | | | | | | | | | Summary: Makes this consistent with the old PM. Reviewers: eraman Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D46526 llvm-svn: 331709
* [WebAssembly] MC: Use existing MCSymbol.Index field rather than inventing ↵Sam Clegg2018-05-081-15/+11
| | | | | | | | | | | | | extra mapping MCSymbol has getIndex/setIndex which are implementation defined and on other platforms are used to store the symbol table index. It makes sense to use this rather than invent a new mapping. Differential Revision: https://reviews.llvm.org/D46555 llvm-svn: 331705
* [MC] ELFObjectWriter: Removing unneeded variable and castSam Clegg2018-05-071-5/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D46289 llvm-svn: 331704
* Revert r330742: Let TableGen write output only if it changed, instead of ↵Chandler Carruth2018-05-071-16/+5
| | | | | | | | | | | | | | | | | | | | doing so in cmake. This change causes us to re-run tablegen for every single target on every single build. This is much, much worse than the problem being fixed AFAICT. On my system, it makes a clean rebuild of `llc` with nothing changed go from .5s to over 8s. On systems with less parallelism, slower file systems, or high process startup overhead this will be even more extreme. The only way I see this could be a win is in clean builds where we churn the filesystem. But I think incremental rebuild is more important, and so if we want to re-instate this, it needs to be done in a way that doesn't trigger constant re-runs of tablegen. llvm-svn: 331702
* [MachineVerifier][GlobalISel] Checking that generic instrs have LLTs on all ↵Roman Tereshin2018-05-072-6/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | vregs Every generic machine instruction must have generic virtual registers only, that is, have a low-level type attached to each operand. Previously MachineVerifier would catch a type missing on an operand only if the previous operand for the the same type index exists and have a type attached to it and it will report it as a type mismatch. This is incosistent behaviour and a misleading error message. This commit makes sure MachineVerifier explicitly checks that the types are there for every operand and if not provides a straightforward error message. Reviewers: qcolombet t.p.northover bogner ab Reviewed By: qcolombet Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D46455 llvm-svn: 331694
* [MachineVerifier][GlobalISel] NFC, Improving MO printing and refactoring ↵Roman Tereshin2018-05-072-21/+28
| | | | | | | | | | | | | | | | | | | | visitMachineInstrBefore This is an NFC pre-commit for the following "Checking that generic instrs have LLTs on all vregs" commit. This overloads MachineOperand::print to make it possible to print LLTs with standalone machine operands. This also overloads MachineVerifier::print(...MachineOperand...) with an optional LLT using the newly introduced MachineOperand::print variant; no actual calls added. This also refactors MachineVerifier::visitMachineInstrBefore in the parts dealing with all generic instructions (checking Selected property, LLTs, and phys regs). llvm-svn: 331693
* AMDGPU/GlobalISel: Don't try to lower hull shadersTom Stellard2018-05-071-2/+3
| | | | | | | | | | | | Summary: The AMDGPU_HS calling convention is not supported yet. Reviewers: arsenm, nhaehnle Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D46149 llvm-svn: 331691
* [DAGCombiner] Masked merge: enhance handling of 'andn' with immediatesRoman Lebedev2018-05-071-4/+14
| | | | | | | | | | | | | | | | | | | | | Summary: Split off from D46031. The previous patch, D46493, completely disabled unfolding in case of immediates. But we can do better: {F6120274} {F6120277} https://rise4fun.com/Alive/xJS Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: andreadb, llvm-commits Differential Revision: https://reviews.llvm.org/D46494 llvm-svn: 331685
* [DagCombiner] Not all 'andn''s work with immediates.Roman Lebedev2018-05-073-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Split off from D46031. In masked merge case, this degrades IPC by decreasing instruction count. {F6108777} The next patch should be able to recover and improve this. This also affects the transform @spatel have added in D27489 / rL289738, and the test coverage for X86 was missing. But after i have added it, and looked at the changes in MCA, i'm somewhat confused. {F6093591} {F6093592} {F6093593} I'd say this regression is an improvement, since `IPC` increased in that case? Reviewers: spatel, craig.topper Reviewed By: spatel Subscribers: andreadb, llvm-commits, spatel Differential Revision: https://reviews.llvm.org/D46493 llvm-svn: 331684
* Remove explicit setting of the CFI jumptable section name, it does not appearDmitry Mikulin2018-05-071-6/+0
| | | | | | | | | | to be needed: jump table sections are created with .cfi.jumptable suffix. With this change each jump table is placed in a separate section, which allows the linker to re-order them. Differential Revision: https://reviews.llvm.org/D46537 llvm-svn: 331680
* [X86] Split WriteFAdd/WriteFCmp/WriteFMul schedule classesSimon Pilgrim2018-05-0712-172/+229
| | | | | | | | Split to support single/double for scalar, XMM and YMM/ZMM instructions - removing InstrRW overrides for these instructions. Fixes Atom ADDSUBPD instruction and reclassifies VFPCLASS as WriteFCmp which is closer in behaviour. llvm-svn: 331672
* [SelectionDAG] Transfer DbgValues when casts are optimized in ↵Aaron Smith2018-05-071-2/+4
| | | | | | | | | | | | | | | | | | | | | SelectionDAG::getNode Summary: getNode optimizes (ext (trunc x)) to x and the dbgvalue node on trunc is lost. The fix calls transferDbgValues to add the dbgvalue to x. Add DebugInfo/AArch64/dbg-value-i16.ll Patch by Sejong Oh! Reviewers: aprantl, javed.absar, llvm-commits, vsk Reviewed By: aprantl, vsk Subscribers: kristof.beyls, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D46348 llvm-svn: 331665
* [WebAssembly] Ensure all .debug_XXX section has proper symbol namesSam Clegg2018-05-072-4/+11
| | | | | | | | | | | Updated wasm section symbols names to match section name, and ensure all referenced sections will have a symbol (per DWARF spec v3, Figure 43) Patch by Yury Delendik! Differential Revision: https://reviews.llvm.org/D46543 llvm-svn: 331664
* [X86][AVX2] Tag VPMOVSX/VPMOVZX ymm instructions as WriteShuffle256Simon Pilgrim2018-05-076-82/+21
| | | | | | | | These are more like cross-lane shuffles than regular shuffles - we already do this for AVX512 equivalents. Differential Revision: https://reviews.llvm.org/D46229 llvm-svn: 331659
* [Hexagon] Move clamping of extended operands directly to MC code emitterKrzysztof Parzyszek2018-05-075-46/+38
| | | | llvm-svn: 331653
* [X86][Znver1] Remove WriteFMul/WriteFRcp InstRW overrides/aliases.Simon Pilgrim2018-05-071-44/+3
| | | | | | Fixes x87 schedules to more closely match Agner - AMD doesn't tend to "special case" x87 instructions as much as Intel. llvm-svn: 331645
* [X86] Split WriteFDiv schedule classes to support single/double scalar, XMM ↵Simon Pilgrim2018-05-0712-453/+206
| | | | | | | | and YMM/ZMM instructions. This removes all InstrRW overrides for these instructions - some x87 overrides remain but most use default (and realistic) values. llvm-svn: 331643
* [AMDGPU][Waitcnt] Remove the old waitcnt passMark Searles2018-05-075-718/+15
| | | | | | | | | Remove the old waitcnt pass ( si-insert-waits ), which is no longer maintained and getting crufty Differential Revision: https://reviews.llvm.org/D46448 llvm-svn: 331641
* Add option -verify-cfiinstrs to run verifier in CFIInstrInserterPetar Jovanovic2018-05-071-5/+11
| | | | | | | | | Instead of enabling it for non NDEBUG builds, use -verify-cfiinstrs to run verifier in CFIInstrInserter. It defaults to false. Differential Revision: https://reviews.llvm.org/D46444 llvm-svn: 331635
* [AMDGPU] Don't force WQM for DS opTim Renouf2018-05-071-3/+1
| | | | | | | | | | | | | | | | | | | | | | Summary: Previously, all DS ops forced WQM in a pixel shader. That was a hack to allow for graphics frontends using ds_swizzle to implement explicit derivatives, on SI/CI at least where DPP is not available. But it forced WQM for _any_ DS op. With this commit, DS ops no longer force WQM. Both graphics frontends (Mesa and LLPC) need to change to issue an explicit llvm.amdgcn.wqm intrinsic call when calculating explicit derivatives. The required Mesa change is: "amd/common: use llvm.amdgcn.wqm for explicit derivatives". Subscribers: qcolombet, arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D46051 Change-Id: I9b745b626fa91bbd66456e6cf41ee07eeea42f81 llvm-svn: 331633
* [X86] Split WriteFRcp/WriteFRsqrt/WriteFSqrt schedule classesSimon Pilgrim2018-05-0713-603/+228
| | | | | | | | | | | | | WriteFRcp/WriteFRsqrt are split to support scalar, XMM and YMM/ZMM instructions. WriteFSqrt is split into single/double/long-double sizes and scalar, XMM, YMM and ZMM instructions. This removes all InstrRW overrides for these instructions. NOTE: There were a couple of typos in the Znver1 model - notably a 1cy throughput for SQRT that is highly unlikely and doesn't tally with Agner. NOTE: I had to add Agner's numbers for several targets for WriteFSqrt80. llvm-svn: 331629
* Skip unreachable blocks for CFIInstrInserter verifyPetar Jovanovic2018-05-071-3/+4
| | | | | | | Iterate only through reachable blocks. This finetunes r330706 and it resolves build issue reported by Craig Topper. llvm-svn: 331628
* [SystemZ] Bugfix for MVCLoop CC clobbering.Jonas Paulsson2018-05-071-1/+1
| | | | | | | | MVCLoop clobbers CC (since it emits a compare/branch), but this was not modelled. Review: Ulrich Weigand llvm-svn: 331627
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