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* Fix updateTerminator to be resiliant to degenerate terminators whereChandler Carruth2012-04-161-7/+29
| | | | | | | | | | | | | | | | | | | | | both fallthrough and a conditional branch target the same successor. Gracefully delete the conditional branch and introduce any unconditional branch needed to reach the actual successor. This fixes memory corruption in 2009-06-15-RegScavengerAssert.ll and possibly other tests. Also, while I'm here fix a latent bug I spotted by inspection. I never applied the same fundamental fix to this fallthrough successor finding logic that I did to the logic used when there are no conditional branches. As a consequence it would have selected landing pads had they be aligned in just the right way here. I don't have a test case as I spotted this by inspection, and the previous time I found this required have of TableGen's source code to produce it. =/ I hate backend bugs. ;] Thanks to Jim Grosbach for helping me reason through this and reviewing the fix. llvm-svn: 154867
* MC assembly parser handling for trailing comma in macro instantiation.Jim Grosbach2012-04-161-5/+5
| | | | | | | | | A trailing comma means no argument at all (i.e., as if the comma were not present), not an empty argument to the invokee. rdar://11252521 llvm-svn: 154863
* ARM handle :lower16: and :upper16: after a '#' prefix.Jim Grosbach2012-04-161-13/+17
| | | | | | rdar://11252521 llvm-svn: 154862
* Remove support for the special 'fast' value for fpmath accuracy for the moment.Duncan Sands2012-04-162-26/+3
| | | | llvm-svn: 154850
* Fix incorrect atomics codegen introduced in r154705, and extend test to ↵Richard Smith2012-04-161-1/+1
| | | | | | catch it. llvm-svn: 154845
* Remove unused variableDavid Blaikie2012-04-161-1/+0
| | | | llvm-svn: 154841
* ARM assembly two-operand forms for VRSHL.Jim Grosbach2012-04-161-1/+36
| | | | | | rdar://11252521 llvm-svn: 154840
* Do not add offset in applyFixup. This has already been accounted for in Value. Akira Hatanaka2012-04-161-4/+2
| | | | llvm-svn: 154838
* ARM two-operand aliases for VRHADD instructions.Jim Grosbach2012-04-161-0/+32
| | | | | | rdar://11252521 llvm-svn: 154832
* Hexagon V5 (Floating Point) Support.Sirish Pande2012-04-1619-1468/+3365
| | | | llvm-svn: 154829
* Make it possible to indicate relaxed floating point requirements at the IR levelDuncan Sands2012-04-162-6/+48
| | | | | | | | | through the use of 'fpmath' metadata. Currently this only provides a 'fpaccuracy' value, which may be a number in ULPs or the keyword 'fast', however the intent is that this will be extended with additional information about NaN's, infinities etc later. No optimizations have been hooked up to this so far. llvm-svn: 154822
* Flip the new block-placement pass to be on by default.Chandler Carruth2012-04-161-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | This is mostly to test the waters. I'd like to get results from FNT build bots and other bots running on non-x86 platforms. This feature has been pretty heavily tested over the last few months by me, and it fixes several of the execution time regressions caused by the inlining work by preventing inlining decisions from radically impacting block layout. I've seen very large improvements in yacr2 and ackermann benchmarks, along with the expected noise across all of the benchmark suite whenever code layout changes. I've analyzed all of the regressions and fixed them, or found them to be impossible to fix. See my email to llvmdev for more details. I'd like for this to be in 3.1 as it complements the inliner changes, but if any failures are showing up or anyone has concerns, it is just a flag flip and so can be easily turned off. I'm switching it on tonight to try and get at least one run through various folks' performance suites in case SPEC or something else has serious issues with it. I'll watch bots and revert if anything shows up. llvm-svn: 154816
* Add a somewhat hacky heuristic to do something different from whole-loopChandler Carruth2012-04-161-3/+78
| | | | | | | | | | | | | rotation. When there is a loop backedge which is an unconditional branch, we will end up with a branch somewhere no matter what. Try placing this backedge in a fallthrough position above the loop header as that will definitely remove at least one branch from the loop iteration, where whole loop rotation may not. I haven't seen any benchmarks where this is important but loop-blocks.ll tests for it, and so this will be covered when I flip the default. llvm-svn: 154812
* Fix style violation in BBVectorize (pointed out by Bill Wendling)Hal Finkel2012-04-161-3/+3
| | | | llvm-svn: 154810
* Tweak the loop rotation logic to check whether the loop is naturallyChandler Carruth2012-04-161-11/+51
| | | | | | | | | | | laid out in a form with a fallthrough into the header and a fallthrough out of the bottom. In that case, leave the loop alone because any rotation will introduce unnecessary branches. If either side looks like it will require an explicit branch, then the rotation won't add any, do it to ensure the branch occurs outside of the loop (if possible) and maximize the benefit of the fallthrough in the bottom. llvm-svn: 154806
* Reapply 'Add reverseColor to raw_ostream'.Benjamin Kramer2012-04-163-0/+49
| | | | | | | To be used in printing unprintable source in clang diagnostics. Patch by Seth Cantrell, with a minor fix for mingw by me. llvm-svn: 154805
* Revert r154800 which breaks windows builders.Argyrios Kyrtzidis2012-04-163-50/+0
| | | | llvm-svn: 154802
* Replace vpermd/vpermps intrinic patterns with custom lowering to target ↵Craig Topper2012-04-162-18/+14
| | | | | | specific nodes. llvm-svn: 154801
* Add reverseColor to raw_ostream.Argyrios Kyrtzidis2012-04-163-0/+50
| | | | | | | To be used in printing unprintable source in clang diagnostics. Patch by Seth Cantrell! llvm-svn: 154800
* Change type profile for vpermv back to using operand type for the mask ↵Craig Topper2012-04-162-5/+5
| | | | | | argument to match intrinsic behavior. Add a bitcast to the lowering code to convert mask from v8i32 to v8f32 for vpermps. llvm-svn: 154798
* Flip the arguments when converting vpermd/vpermps intrinsics into ↵Craig Topper2012-04-161-3/+3
| | | | | | instructions. The intrinsic has the mask as the last operand, but the instruction has it as the second. llvm-svn: 154797
* Add a Fixme.Bill Wendling2012-04-161-0/+2
| | | | llvm-svn: 154793
* Simplify checking for pointer types in BBVectorize (this change was ↵Hal Finkel2012-04-161-5/+2
| | | | | | suggested by Duncan). llvm-svn: 154787
* Remove dead SD nodes after the combining pass. Fixes PR12201.Hal Finkel2012-04-161-0/+1
| | | | llvm-svn: 154786
* Rewrite how machine block placement handles loop rotation.Chandler Carruth2012-04-161-66/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a complex change that resulted from a great deal of experimentation with several different benchmarks. The one which proved the most useful is included as a test case, but I don't know that it captures all of the relevant changes, as I didn't have specific regression tests for each, they were more the result of reasoning about what the old algorithm would possibly do wrong. I'm also failing at the moment to craft more targeted regression tests for these changes, if anyone has ideas, it would be welcome. The first big thing broken with the old algorithm is the idea that we can take a basic block which has a loop-exiting successor and a looping successor and use the looping successor as the layout top in order to get that particular block to be the bottom of the loop after layout. This happens to work in many cases, but not in all. The second big thing broken was that we didn't try to select the exit which fell into the nearest enclosing loop (to which we exit at all). As a consequence, even if the rotation worked perfectly, it would result in one of two bad layouts. Either the bottom of the loop would get fallthrough, skipping across a nearer enclosing loop and thereby making it discontiguous, or it would be forced to take an explicit jump over the nearest enclosing loop to earch its successor. The point of the rotation is to get fallthrough, so we need it to fallthrough to the nearest loop it can. The fix to the first issue is to actually layout the loop from the loop header, and then rotate the loop such that the correct exiting edge can be a fallthrough edge. This is actually much easier than I anticipated because we can handle all the hard parts of finding a viable rotation before we do the layout. We just store that, and then rotate after layout is finished. No inner loops get split across the post-rotation backedge because we check for them when selecting the rotation. That fix exposed a latent problem with our exitting block selection -- we should allow the backedge to point into the middle of some inner-loop chain as there is no real penalty to it, the whole point is that it *won't* be a fallthrough edge. This may have blocked the rotation at all in some cases, I have no idea and no test case as I've never seen it in practice, it was just noticed by inspection. Finally, all of these fixes, and studying the loops they produce, highlighted another problem: in rotating loops like this, we sometimes fail to align the destination of these backwards jumping edges. Fix this by actually walking the backwards edges rather than relying on loopinfo. This fixes regressions on heapsort if block placement is enabled as well as lots of other cases where the previous logic would introduce an abundance of unnecessary branches into the execution. llvm-svn: 154783
* Merge vpermps/vpermd and vpermpd/vpermq SD nodes.Craig Topper2012-04-164-31/+20
| | | | llvm-svn: 154782
* Fix SDTypeProfile for vpermps. The mask operand should be v8i32.Craig Topper2012-04-161-2/+4
| | | | llvm-svn: 154781
* Spacing fixes and 80 column fixes. Use 0 instead of 0x80 for undef indices ↵Craig Topper2012-04-151-9/+12
| | | | | | in vpermps/vpermd. Hardware only looks at lower 3-bits. llvm-svn: 154780
* Remove AVX2 vpermq and vpermpd intrinsics. These can now be handled with ↵Craig Topper2012-04-151-17/+8
| | | | | | normal shuffle vectors. llvm-svn: 154778
* Fix PR12529. The Vxx family of instructions are only supported by AVX.Nadav Rotem2012-04-151-3/+13
| | | | | | Use non-vex instructions for SSE4. llvm-svn: 154770
* Wire up support for diagnostic ranges in the ARMAsmParser.Benjamin Kramer2012-04-151-3/+12
| | | | | | | | | | | | | | As an example, attach range info to the "invalid instruction" message: $ clang -arch arm -c asm.c asm.c:2:11: error: invalid instruction __asm__("foo r0"); ^ <inline asm>:1:2: note: instantiated into assembly here foo r0 ^~~ llvm-svn: 154765
* When emulating vselect using OR/AND/XOR make sure to bitcast the result back ↵Nadav Rotem2012-04-151-1/+2
| | | | | | to the original type. llvm-svn: 154764
* Added VPERM optimization for AVX2 shufflesElena Demikhovsky2012-04-155-4/+76
| | | | llvm-svn: 154761
* HexagonCopyToCombine.cpp: Silence two warnings, -Wunused-variable, with ↵NAKAMURA Takumi2012-04-151-0/+2
| | | | | | -Asserts. llvm-svn: 154759
* Target/Hexagon: Tweak to fix msvc build.NAKAMURA Takumi2012-04-151-2/+2
| | | | llvm-svn: 154758
* Rename "fpaccuracy" metadata to the more generic "fpmath". That's because I'mDuncan Sands2012-04-142-9/+9
| | | | | | | | | thinking of generalizing it to be able to specify other freedoms beyond accuracy (such as that NaN's don't have to be respected). I'd like the 3.1 release (the first one with this metadata) to have the more generic name already rather than having to auto-upgrade it in 3.2. llvm-svn: 154744
* Fix an error in BBVectorize important for vectorizing pointer types.Hal Finkel2012-04-141-0/+31
| | | | | | | | | | When vectorizing pointer types it is important to realize that potential pairs cannot be connected via the address pointer argument of a load or store. This is because even after vectorization, the address is still a scalar because the address of the higher half of the pair is implicit from the address of the lower half (it need not be, and should not be, explicitly computed). llvm-svn: 154735
* Enhance BBVectorize to more-properly handle pointer values and vectorize GEPs.Hal Finkel2012-04-141-2/+27
| | | | llvm-svn: 154734
* misched: Added CanHandleTerminators.Andrew Trick2012-04-131-3/+3
| | | | | | | | | This is a special flag for targets that really want their block terminators in the DAG. The default scheduler cannot handle this correctly, so it becomes the specialized scheduler's responsibility to schedule terminators. llvm-svn: 154712
* Fix X86 codegen for 'atomicrmw nand' to generate *x = ~(*x & y), not *x = ↵Richard Smith2012-04-132-27/+33
| | | | | | ~*x & y. llvm-svn: 154705
* Remove iostream from New Value Jump.Sirish Pande2012-04-131-1/+0
| | | | llvm-svn: 154703
* Add support to BBVectorize for vectorizing selects.Hal Finkel2012-04-131-0/+8
| | | | llvm-svn: 154700
* Add support for Hexagon Architectural feature, New Value Jump.Sirish Pande2012-04-137-10/+684
| | | | llvm-svn: 154696
* Pass to replace tranfer/copy instructions into combine instruction where ↵Sirish Pande2012-04-135-0/+484
| | | | | | possible. llvm-svn: 154695
* Reduce malloc traffic in DwarfAccelTableBenjamin Kramer2012-04-132-58/+28
| | | | | | | | | - Don't copy offsets into HashData, the underlying vector won't change once the table is finalized. - Allocate HashData and HashDataContents in a BumpPtrAllocator. - Allocate string map entries in the same allocator. - Random cleanups. llvm-svn: 154694
* On Darwin targets, only use vfma etc. if the source use fma() intrinsic ↵Evan Cheng2012-04-131-2/+5
| | | | | | explicitly. llvm-svn: 154689
* Add some comments, and fix a few places that missed setting Changed.Dan Gohman2012-04-131-2/+24
| | | | llvm-svn: 154687
* For ARM disassembly only print 32 unsigned bits for the address of branchKevin Enderby2012-04-131-2/+2
| | | | | | | targets so if the branch target has the high bit set it does not get printed as: beq 0xffffffff8008c404 llvm-svn: 154685
* Consider ObjC runtime calls objc_storeWeak and others which make a copy ofDan Gohman2012-04-131-14/+29
| | | | | | | their argument as "escape" points for objc_retainBlock optimization. This fixes rdar://11229925. llvm-svn: 154682
* By default, use Early-CSE instead of GVN for vectorization cleanup.Hal Finkel2012-04-131-2/+9
| | | | | | | | | | As has been suggested by Duncan and others, Early-CSE and GVN should do similar redundancy elimination, but Early-CSE is much less expensive. Most of my autovectorization benchmarks show a performance regresion, but all of these are < 0.1%, and so I think that it is still worth using the less expensive pass. llvm-svn: 154673
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