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* Implement a bastardized ABI.Evan Cheng2012-04-272-3/+5
| | | | llvm-svn: 155686
* - thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2Evan Cheng2012-04-272-16/+28
| | | | | | | | instructions. - However, it does support dmb, dsb, isb, mrs, and msr. rdar://11331541 llvm-svn: 155685
* Use ConstantExpr::getExtractElement when constant-folding vectorsDan Gohman2012-04-272-32/+51
| | | | | | | | | | | | | | | | | | | | | instead of getAggregateElement. This has the advantage of being more consistent and allowing higher-level constant folding to procede even if an inner extract element cannot be folded. Make ConstantFoldInstruction call ConstantFoldConstantExpression on the instruction's operands, making it more consistent with ConstantFoldConstantExpression itself. This makes sure that ConstantExprs get TargetData-aware folding before being handed off as operands for further folding. This causes more expressions to be folded, but due to a known shortcoming in constant folding, this currently has the side effect of stripping a few more nuw and inbounds flags in the non-targetdata side of constant-fold-gep.ll. This is mostly harmless. This fixes rdar://11324230. llvm-svn: 155682
* Break up getProfitableChainIncrement().Jakob Stoklund Olesen2012-04-261-39/+47
| | | | | | | | | | | The required checks are moved to ChainInstruction() itself and the policy decisions are moved to IVChain::isProfitableInc(). Also cache the ExprBase in IVChain to avoid frequent recomputations. No functional change intended. llvm-svn: 155676
* Turn IVChain into a struct.Jakob Stoklund Olesen2012-04-261-19/+42
| | | | | | No functional change intended. llvm-svn: 155675
* Add instcombine patterns for the following transformations:Chad Rosier2012-04-262-0/+19
| | | | | | | | | | (x & y) | (x ^ y) -> x | y (x & y) + (x ^ y) -> x | y Patch by Manman Ren. rdar://10770603 llvm-svn: 155674
* Fix the SD scheduler to avoid gluing the same node twice.Andrew Trick2012-04-261-3/+5
| | | | | | | | | | | DAGCombine strangeness may result in multiple loads from the same offset. They both may try to glue themselves to another load. We could insist that the redundant loads glue themselves to each other, but the beter fix is to bail out from bad gluing at the time we detect it. Fixes rdar://11314175: BuildSchedUnits assert. llvm-svn: 155668
* ARM: Thumb ldr(literal) base address alignment is 32-bits.Jim Grosbach2012-04-261-1/+2
| | | | | | | | | | The base address for the PC-relative load is Align(PC,4), so it's the address of the word containing the 16-bit instruction, not the address of the instruction itself. Ugh. rdar://11314619 llvm-svn: 155659
* Trivial change to set UseLeaForSP flag in addition to togglingPreston Gurd2012-04-261-0/+2
| | | | | | | | the FeatureLeaForSP feature bit when llvm auto detects Intel Atom. Patch by Andy Zhang llvm-svn: 155655
* [Support/YAML] Properly fix unitialized variable warning by inserting aMichael J. Spencer2012-04-261-6/+12
| | | | | | 'REPLACEMENT CHARACTER' (U+FFFD) when getAsInteger fails. llvm-svn: 155653
* Use VLD1 in NEON extenting-load patterns instead of VLDR.Tim Northover2012-04-261-56/+59
| | | | | | | On some cores it's a bad idea for performance to mix VFP and NEON instructions and since these patterns are NEON anyway, the NEON load should be used. llvm-svn: 155630
* Test commit.Tim Northover2012-04-261-2/+0
| | | | llvm-svn: 155626
* Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to ↵Craig Topper2012-04-262-13/+9
| | | | | | corei7-avx, core-avx-i, and core-avx2 cpu names. llvm-svn: 155618
* Teach the reassociate pass to fold chains of multiplies with repeatedChandler Carruth2012-04-261-10/+247
| | | | | | | | | | | | | | | | | elements to minimize the number of multiplies required to compute the final result. This uses a heuristic to attempt to form near-optimal binary exponentiation-style multiply chains. While there are some cases it misses, it seems to at least a decent job on a very diverse range of inputs. Initial benchmarks show no interesting regressions, and an 8% improvement on SPASS. Let me know if any other interesting results (in either direction) crop up! Credit to Richard Smith for the core algorithm, and helping code the patch itself. llvm-svn: 155616
* If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assumeEvan Cheng2012-04-263-7/+16
| | | | | | | | | | the feature set of v7a. This comes about if the user specifies something like -arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as uxtab in this case. rdar://11318438 llvm-svn: 155601
* Don't forget to reset 'first operand' flag when we're setting the ↵Bill Wendling2012-04-261-5/+8
| | | | | | MDNodeOperand value. llvm-svn: 155599
* Print IV chain numbers while collecting them.Jakob Stoklund Olesen2012-04-251-4/+5
| | | | llvm-svn: 155567
* Remove more dead code.Jakob Stoklund Olesen2012-04-251-3/+0
| | | | llvm-svn: 155566
* Unify internal representation of ARM instructions with a register ↵Richard Barton2012-04-252-4/+10
| | | | | | right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation. llvm-svn: 155565
* Remove the -disable-cross-class-join option.Jakob Stoklund Olesen2012-04-251-13/+4
| | | | | | | | Cross-class joins have been normal and fully supported for a while now. With TableGen generating the getMatchingSuperRegClass() hook, they are unlikely to cause problems again. llvm-svn: 155552
* Cross-class joining is winning.Jakob Stoklund Olesen2012-04-251-66/+0
| | | | | | | | | | | | Remove the heuristic for disabling cross-class joins. The greedy register allocator can handle the narrow register classes, and when it splits a live range, it can pick a larger register class. Benchmarks were unaffected by this change. <rdar://problem/11302212> llvm-svn: 155551
* Add ifdef around getSubtargetFeatureName in tablegen output file so that ↵Craig Topper2012-04-251-0/+1
| | | | | | only targets that want the function get it. This prevents other targets from getting an unused function warning. llvm-svn: 155538
* Use vector_shuffles instead of target specific unpack nodes for AVX ↵Craig Topper2012-04-251-18/+20
| | | | | | ZERO_EXTEND/ANY_EXTEND combine. These will be converted to target specific nodes during lowering. This is more consistent with other code. llvm-svn: 155537
* Reverting r155468. Chris and Chandler have convinced me that it's dangerous andLang Hames2012-04-251-35/+0
| | | | | | | | in poor taste. Talking through some alternate solutions with Chandler. llvm-svn: 155530
* Do not use $gp as a dedicated global register if the target ABI is not O32. Akira Hatanaka2012-04-251-2/+2
| | | | llvm-svn: 155522
* Simplify the known retain count tracking; use a boolean state insteadDan Gohman2012-04-251-41/+34
| | | | | | | of a precise count. Also, move RRInfo's Partial field into PtrState, now that it won't increase the size. llvm-svn: 155513
* Build custom predecessor and successor lists for each basic block.Dan Gohman2012-04-241-115/+101
| | | | | | | | These lists exclude invoke unwind edges and loop backedges which are being ignored. This makes it easier to ignore them consistently. llvm-svn: 155500
* ARM: improved assembler diagnostics for missing CPU features.Jim Grosbach2012-04-242-23/+42
| | | | | | | | | | | When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 llvm-svn: 155499
* Fix a naughty header include that breaks "installed" builds.Andrew Trick2012-04-241-2/+12
| | | | llvm-svn: 155486
* ConstantFoldSelectInstruction swapped the operands of the select.Nadav Rotem2012-04-241-1/+1
| | | | | | Fix 12592. Patch by Matt Pharr. llvm-svn: 155480
* MachineBasicBlock::SplitCriticalEdge() should follow LLVM IR variant and ↵Evan Cheng2012-04-241-0/+5
| | | | | | refuse to break edge to EH landing pad. rdar://11300144 llvm-svn: 155470
* Add support for llvm.arm.neon.vmull* intrinsics to InstCombine. This fixesLang Hames2012-04-241-0/+35
| | | | | | <rdar://problem/11291436>. llvm-svn: 155468
* Fix a crash on valid (if UB) bitcode that is produced for some globalChandler Carruth2012-04-241-3/+11
| | | | | | | | | | | | | | | | | | | | | constants in C++11 mode. I have no idea why it required such particular circumstances to get here, the code seems clearly to rely upon unchecked assumptions. Specifically, when we decide to form an index into a struct type, we may have gone through (at least one) zero-length array indexing round, which would have left the offset un-adjusted, and thus not necessarily valid for use when indexing the struct type. This is just an canonicalization step, so the correct thing is to refuse to canonicalize nonsensical GEPs of this form. Implemented, and test case added. Fixes PR12642. Pair debugged and coded with Richard Smith. =] I credit him with most of the debugging, and preventing me from writing the wrong code. llvm-svn: 155466
* ARM: Nuke remnant bogus code.Jim Grosbach2012-04-241-2/+0
| | | | | | | | r154362 was supposed to delete this bit, but obviously didn't. rdar://11305594 llvm-svn: 155465
* AVX: Add additional vbroadcast replacement sequences for integers.Nadav Rotem2012-04-241-3/+30
| | | | | | | Remove the v2f64 patterns because it does not match any vbroadcast instruction. llvm-svn: 155461
* cmake: new fileAndrew Trick2012-04-241-0/+1
| | | | llvm-svn: 155460
* misched: DAG builder must special case earlyclobberAndrew Trick2012-04-241-0/+9
| | | | llvm-svn: 155459
* misched: try (not too hard) to place debug values where they belongAndrew Trick2012-04-241-0/+25
| | | | llvm-svn: 155458
* misched: ignore debug values during schedulingAndrew Trick2012-04-241-6/+31
| | | | llvm-svn: 155457
* misched: DAG builder support for tracking register pressure within the ↵Andrew Trick2012-04-242-5/+58
| | | | | | | | | current scheduling region. The DAG builder is a convenient place to do it. Hopefully this is more efficient than a separate traversal over the same region. llvm-svn: 155456
* RegisterPressure: A utility for computing register pressure within aAndrew Trick2012-04-242-0/+718
| | | | | | | | | | | | | | | | | | MachineInstr sequence. This uses the new target interface for tracking register pressure using pressure sets to model overlapping register classes and subregisters. RegisterPressure results can be tracked incrementally or stored at region boundaries. Global register pressure can be deduced from local RegisterPressure results if desired. This is an early, somewhat untested implementation. I'm working on testing it within the context of a register pressure reducing MachineScheduler. llvm-svn: 155454
* AVX2: The BLENDPW instruction selects between vectors of v16i16 using an i8Nadav Rotem2012-04-241-6/+0
| | | | | | | immediate. We can't use it here because the shuffle code does not check that the lower part of the word is identical to the upper part. llvm-svn: 155440
* Refactor Thumb ITState handling in ARM Disassembler to more efficiently use ↵Richard Barton2012-04-241-31/+69
| | | | | | its vector llvm-svn: 155439
* AVX: We lower VECTOR_SHUFFLE and BUILD_VECTOR nodes into vbroadcast instructionsNadav Rotem2012-04-241-1/+42
| | | | | | | | | using the pattern (vbroadcast (i32load src)). In some cases, after we generate this pattern new users are added to the load node, which prevent the selection of the blend pattern. This commit provides fallback patterns which perform in-vector broadcast (using in-vector vbroadcast in AVX2 and pshufd on AVX1). llvm-svn: 155437
* Look for the 'Is Simulated' module flag. This indicates that the program is ↵Bill Wendling2012-04-241-4/+5
| | | | | | compiled to run on a simulator. llvm-svn: 155435
* Remove dangling spaces. Fix some other formatting.Craig Topper2012-04-241-8/+10
| | | | llvm-svn: 155429
* Simplify code a bit and make it compile better. Remove unused parameters.Craig Topper2012-04-241-21/+10
| | | | llvm-svn: 155428
* Add a missing cpu subtype.Evan Cheng2012-04-231-0/+4
| | | | llvm-svn: 155402
* Tidy up. 80 columns, whitespace, et. al.Jim Grosbach2012-04-234-59/+65
| | | | llvm-svn: 155399
* Optimize the vector UINT_TO_FP, SINT_TO_FP and FP_TO_SINT operations where ↵Nadav Rotem2012-04-231-0/+56
| | | | | | the integer type is i8 (commonly used in graphics). llvm-svn: 155397
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