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* Move constant-sized bitvector to the stack.Benjamin Kramer2014-09-111-2/+2
| | | | llvm-svn: 217600
* Combine fmul vector FP constants when unsafe math is allowed.Sanjay Patel2014-09-111-6/+22
| | | | | | | | | | | | | | | | | | | This is an extension of the change made with r215820: http://llvm.org/viewvc/llvm-project?view=revision&revision=215820 That patch allowed combining of splatted vector FP constants that are multiplied. This patch allows combining non-uniform vector FP constants too by relaxing the check on the type of vector. Also, canonicalize a vector fmul in the same way that we already do for scalars - if only one operand of the fmul is a constant, make it operand 1. Otherwise, we miss potential folds. This fold is also done by -instcombine, but it's possible that extra fmuls may have been generated during lowering. Differential Revision: http://reviews.llvm.org/D5254 llvm-svn: 217599
* typoSanjay Patel2014-09-111-1/+1
| | | | llvm-svn: 217597
* R600: Add cmpxchg instruction for evergreenAaron Watry2014-09-112-5/+29
| | | | | | | | | | | | | | | | | Refactored the R600_LDS_1A2D class a bit to get it to actually work. It seemed to be previously unused and broken. We also have to disable the conversion to the noret variant for now in R600ISelLowering because the getLDSNoRetOp method only handles 1A1D LDS ops. Someone can feel free to modify the AMDGPU::getLDSNoRetOp method to work for more than 1A1D variants of LDS operations. It's being left as a future TODO for now. Signed-off-by: Aaron Watry <awatry at gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217596
* R600: Add LDS_WRXCHG[_RET] instructions for Evergreen.Aaron Watry2014-09-111-0/+4
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217594
* R600: Add LDS_MIN_[U]INT[_RET] instructions for EvergreenAaron Watry2014-09-111-0/+8
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217593
* R600: Add LDS_XOR[_RET] instructions for EvergreenAaron Watry2014-09-111-0/+4
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217592
* R600: Add LDS_OR[_RET] instructions for EvergreenAaron Watry2014-09-111-0/+4
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217591
* R600: Add LDS_AND[_RET] instructions for EvergreenAaron Watry2014-09-111-0/+4
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217590
* R600: Add LDS_MAX_[U]INT[_RET] instructions for EvergreenAaron Watry2014-09-111-0/+8
| | | | | | | | | | | | | This was only present for SI before. Cayman may still be missing, but I am unable to test that currently. v2: Don't create atomicrmw max tests in separate file Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> CC: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 217589
* [AlignmentFromAssumptions] Don't crash just because the target is 32-bitHal Finkel2014-09-111-0/+4
| | | | | | | | | We used to crash processing any relevant @llvm.assume on a 32-bit target (because we'd ask SE to subtract expressions of differing types). I've copied our 'simple.ll' test, but with the data layout from arm-linux-gnueabihf to get some meaningful test coverage here. llvm-svn: 217574
* Build correct vector filled with undef nodesDavid Xu2014-09-111-4/+20
| | | | llvm-svn: 217570
* R600/SI: Fix losing chain when fixing reg class of loads.Matt Arsenault2014-09-101-6/+14
| | | | | | | The lost chain resulting in earlier side effecting nodes being deleted. llvm-svn: 217561
* R600/SI: Report offset in correct units for st64 DS instructionsMatt Arsenault2014-09-101-0/+15
| | | | | | | | | | | Need to convert the 64 element offset into bytes, not just the element size like the normal case instructions. Noticed by inspection. This can't be hit now because st64 instructions aren't emitted during instruction selection, and the post-RA scheduler isn't enabled. llvm-svn: 217560
* R600: Custom lower fremMatt Arsenault2014-09-102-0/+20
| | | | llvm-svn: 217553
* Add doInitialization/doFinalization to DataLayoutPass.Rafael Espindola2014-09-106-13/+16
| | | | | | | | | | | | | With this a DataLayoutPass can be reused for multiple modules. Once we have doInitialization/doFinalization, it doesn't seem necessary to pass a Module to the constructor. Overall this change seems in line with the idea of making DataLayout a required part of Module. With it the only way of having a DataLayout used is to add it to the Module. llvm-svn: 217548
* [AlignmentFromAssumptions] Don't divide by zero for unknown starting alignmentHal Finkel2014-09-101-2/+4
| | | | | | | | | | The routine that determines an alignment given some SCEV returns zero if the answer is unknown. In a case where we could determine the increment of an AddRec but not the starting alignment, we would compute the integer modulus by zero (which is illegal and traps). Prevent this by returning early if either the start or increment alignment is unknown (zero). llvm-svn: 217544
* [AArch64] Revert r216141 for cycloneGerolf Hoflehner2014-09-101-1/+1
| | | | | | | | | | The increase of the interleave factor to 4 has side-effects like performance losses eg. due to reminder loops being executed more frequently and may increase code size. It requires more analysis and careful heuristic tuning. Expect double digit gains in small benchmarks like lowercase.c and losses in puzzle.c. llvm-svn: 217540
* [PassManager] Adding Hidden attribute to EnableMLSM optionGerolf Hoflehner2014-09-101-2/+2
| | | | llvm-svn: 217539
* [MergedLoadStoreMotion] Move pass enabling option to PassManagerBuilderGerolf Hoflehner2014-09-102-7/+8
| | | | llvm-svn: 217538
* Cleanup: Use the appropriate API for accessing the DIVariable of aAdrian Prantl2014-09-101-1/+1
| | | | | | DBG_VALUE intrinsic. llvm-svn: 217533
* Make CallingConv::ID an alias of "unsigned".Alexey Samsonov2014-09-102-10/+6
| | | | | | | | | | | | | | | | | | | | Summary: Make CallingConv::ID a plain unsigned instead of enum with a fixed set of valus. LLVM IR allows arbitraty calling conventions (you are free to write cc12345), and loading them as enum is an undefined behavior. This was reported by UBSan. Test Plan: llvm regression test suite Reviewers: nicholas Reviewed By: nicholas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5248 llvm-svn: 217529
* Rename getMaximumUnrollFactor -> getMaxInterleaveFactor; also rename option ↵Sanjay Patel2014-09-108-53/+53
| | | | | | | | | | | names controlling this variable. "Unroll" is not the appropriate name for this variable. Clang already uses the term "interleave" in pragmas and metadata for this. Differential Revision: http://reviews.llvm.org/D5066 llvm-svn: 217528
* Removed misleading comment.Gerolf Hoflehner2014-09-101-1/+0
| | | | llvm-svn: 217527
* [AArch64] Address Chad's post commit review comments for r217504 (PBQP ↵Arnaud A. de Grandmaison2014-09-101-11/+10
| | | | | | experimental support) llvm-svn: 217518
* typoSanjay Patel2014-09-101-1/+1
| | | | llvm-svn: 217516
* Fix comments of createReplaceableForwardDecl() and createForwardDecl().Frederic Riss2014-09-101-4/+3
| | | | | | | | | | | | | Noticed while trying to understand how the merge of forward decalred types and defintions work. Reviewers: echristo, dblaikie, aprantl Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5291 llvm-svn: 217514
* [AArch64] Pacify lld buildbot complaining about an unused static function in ↵Arnaud A. de Grandmaison2014-09-101-0/+2
| | | | | | release build. llvm-svn: 217505
* [AArch64] Add experimental PBQP supportArnaud A. de Grandmaison2014-09-105-2/+435
| | | | | | | | | | This adds target specific support for using the PBQP register allocator on the AArch64, for the A57 cpu. By default, the PBQP allocator is not used, unless explicitely required on the command line with "-aarch64-pbqp". llvm-svn: 217504
* [AArch 64] Use a constant pool load for weak symbol references whenAsiri Rathnayake2014-09-104-6/+39
| | | | | | | | | | | | | | using static relocation model and small code model. Summary: currently we generate GOT based relocations for weak symbol references regardless of the underlying relocation model. This should be change so that in static relocation model we use a constant pool load instead. Patch from: Keith Walker Reviewers: Renato Golin, Tim Northover llvm-svn: 217503
* Add missing HWEncoding to base register class.Sid Manning2014-09-101-8/+10
| | | | | | | This change gives tblgen the information needed to fill in the HexagonRegEncodingTable. llvm-svn: 217500
* Attempt to pacify buildbots.David Majnemer2014-09-101-11/+0
| | | | llvm-svn: 217499
* ARM: don't size-reduce STMs using the LR register.Tim Northover2014-09-101-1/+1
| | | | | | | | | The only Thumb-1 multi-store capable of using LR is the PUSH instruction, which translates to STMDB, so we shouldn't convert STMIAs. Patch by Sergey Dmitrouk. llvm-svn: 217498
* Object: Add support for bigobjDavid Majnemer2014-09-102-114/+161
| | | | | | | | | | | | | | | | | | | | | | This adds support for reading the "bigobj" variant of COFF produced by cl's /bigobj and mingw's -mbig-obj. The most significant difference that bigobj brings is more than 2**16 sections to COFF. bigobj brings a few interesting differences with it: - It doesn't have a Characteristics field in the file header. - It doesn't have a SizeOfOptionalHeader field in the file header (it's only used in executable files). - Auxiliary symbol records have the same width as a symbol table entry. Since symbol table entries are bigger, so are auxiliary symbol records. Write support will come soon. Differential Revision: http://reviews.llvm.org/D5259 llvm-svn: 217496
* [mips] Remove inverted predicates from MipsSubtarget that were only used by ↵Daniel Sanders2014-09-102-14/+15
| | | | | | | | | | | | | | | | MipsCallingConv.td Summary: No functional change Reviewers: echristo, vmedic Reviewed By: echristo, vmedic Subscribers: echristo, llvm-commits Differential Revision: http://reviews.llvm.org/D5266 llvm-svn: 217494
* [mips] Return an ArrayRef from MipsCC::intArgRegs() and remove ↵Daniel Sanders2014-09-102-24/+19
| | | | | | | | | | | | | | | | MipsCC::numIntArgRegs() Summary: No functional change. Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5265 llvm-svn: 217485
* MergeFunctions: FunctionPtr has been renamed to FunctionNode.Stepan Dyatkovskiy2014-09-101-7/+7
| | | | | | | It's supposed to store additional pass information for current function here. That was the reason for name change. llvm-svn: 217483
* [asan-assembly-instrumentation] Added CFI directives to the generated ↵Yuri Gorshenin2014-09-104-1/+67
| | | | | | | | | | | | | | instrumentation code. Summary: [asan-assembly-instrumentation] Added CFI directives to the generated instrumentation code. Reviewers: eugenis Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5189 llvm-svn: 217482
* Drop the W postfix on the 16-bit registers.Job Noorman2014-09-107-196/+196
| | | | | | | This ensures the inline assembly register constraints are properly recognised in TargetLowering::getRegForInlineAsmConstraint. llvm-svn: 217479
* [MIPS] Add aliases for sync instruction used by Octeon CPUKai Nacke2014-09-101-0/+6
| | | | | | | | | This commit adds aliases for the sync instruction (synciobdma, syncs, syncw, syncws) which are used by the Octeon CPU. Reviewed by D. Sanders llvm-svn: 217477
* Use cast to MVT instead of EVT on a couple calls to getSizeInBits.Craig Topper2014-09-101-2/+2
| | | | llvm-svn: 217473
* [MCJIT] Remove redundant architecture check from RuntimeDyldMachOI386.Lang Hames2014-09-101-1/+1
| | | | llvm-svn: 217470
* Sink PrevCU updating into DwarfUnit::addRange to ensure consistencyDavid Blaikie2014-09-094-6/+8
| | | | | | | | | So that the two operations in DwarfDebug couldn't get separated (because I accidentally separated them in some work in progress), put them together. While we're here, move DwarfUnit::addRange to DwarfCompileUnit, since it's not relevant to type units. llvm-svn: 217468
* Remove DwarfDebug::PrevSection, PrevCU is sufficient for handling address ↵David Blaikie2014-09-093-15/+3
| | | | | | | | | | | | | range holes. PrevSection/PrevCU are used to detect holes in the address range of a CU to ensure the DW_AT_ranges does not include those holes. When we see a function with no debug info, though it may be in the same range as the prior and subsequent functions, there should be a gap in the CU's ranges. By setting PrevCU to null in that case, the range would not be extended to cover the gap. llvm-svn: 217466
* SampleProfile.cpp: Prune a stray \param added in r217437. [-Wdocumentation]NAKAMURA Takumi2014-09-091-1/+0
| | | | llvm-svn: 217465
* Add a scheduling model for AMD 16H Jaguar (btver2).Sanjay Patel2014-09-093-4/+350
| | | | | | | | | | | | | This is a first pass at a scheduling model for Jaguar. It's structured largely on the existing SandyBridge and SLM sched models. Using this model, in addition to turning on the PostRA scheduler, results in some perf wins on internal and 3rd party benchmarks. There's not much difference in LLVM's test-suite benchmarking subset of tests. Differential Revision: http://reviews.llvm.org/D5229 llvm-svn: 217457
* Merge alignment of common GlobalValue.Rafael Espindola2014-09-091-1/+10
| | | | | | Fixes pr20882. llvm-svn: 217455
* Use armv6k default for FreeBSD/ARMEd Maste2014-09-091-0/+1
| | | | | | Patch by Andrew Turner. llvm-svn: 217454
* When merging two common GlobalValues, keep the largest.Rafael Espindola2014-09-091-2/+17
| | | | llvm-svn: 217451
* Move some logic to ModuleLinker::shouldLinkFromSource. NFC.Rafael Espindola2014-09-091-49/+51
| | | | llvm-svn: 217449
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