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* [mips] Disable tail merging when long branch pass is enabled.Akira Hatanaka2013-10-071-1/+7
| | | | llvm-svn: 192124
* X86: Fix type check. Just because an integer type is illegal doesn't mean ↵Benjamin Kramer2013-10-071-1/+1
| | | | | | | | | it's i64. Fixes PR17495, where an i24 triggered this code. It's intended to optimize i64 loads on 32 bit x86. llvm-svn: 192123
* [mips] Define method MipsSubtarget::enableLongBranchPass.Akira Hatanaka2013-10-072-2/+5
| | | | llvm-svn: 192122
* Revert r191834 until we measure the effect of this benchmarks and maybe find ↵Alexey Samsonov2013-10-071-3/+56
| | | | | | a better way to fix it llvm-svn: 192121
* [mips] Fix definition of mfhi and mflo instructions to read from the wholeAkira Hatanaka2013-10-0710-79/+105
| | | | | | | | | | | | | | | | accumulator instead of its sub-registers, $hi and $lo. We need this change to prevent a mflo following a mtlo from reading an unpredictable/undefined value, as shown in the following example: mult $6, $7 // result of $6 * $7 is written to $lo and $hi. mflo $2 // read lower 32-bit result from $lo. mtlo $4 // write to $lo. the content of $hi becomes unpredictable. mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value. I don't have a test case for this change that reliably reproduces the problem. llvm-svn: 192119
* Formally added an explicit enum for DWARF TLS support. No functionality change.Richard Mitton2013-10-072-6/+8
| | | | llvm-svn: 192118
* Change objectsize intrinsic to accept different address spaces.Matt Arsenault2013-10-071-0/+22
| | | | | | | Bitcasting everything to i8* won't work. Autoupgrade the old intrinsic declarations to use the new mangling. llvm-svn: 192117
* [ARM] Improve build attributes emission.Amara Emerson2013-10-076-56/+91
| | | | llvm-svn: 192111
* [AArch64] Add support for NEON scalar arithmetic instructions:Chad Rosier2013-10-072-44/+141
| | | | | | SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS. llvm-svn: 192107
* Windows/Process.inc: Fix for +Asserts. &Buf[0] is not guaranteed if size is ↵NAKAMURA Takumi2013-10-071-1/+1
| | | | | | zero. llvm-svn: 192103
* Remove dead code.Rafael Espindola2013-10-072-169/+1
| | | | | | | | | Support for exception handling in the legacy JIT was removed in r181354 and this code was dead since then. Thanks to Yaron Keren for noticing it. llvm-svn: 192101
* Remove getEHExceptionRegister and getEHHandlerRegister.Rafael Espindola2013-10-0712-72/+0
| | | | | | They haven't been used for a long time. Patch by MathOnNapkins. llvm-svn: 192099
* Fix the documentation of getDefaultSubtargetFeatures.Rafael Espindola2013-10-071-2/+1
| | | | | | Patch by David Nadlinger. llvm-svn: 192098
* ARM: allow cortex-m0 to use hint instructionsTim Northover2013-10-075-9/+22
| | | | | | | | | | | The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have been ported across to the v6M architecture. Fortunately, v6M seems to sit nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it fairly easily. rdar://problem/15144406 llvm-svn: 192097
* Windows: Be more explicit with Win32 APIsDavid Majnemer2013-10-074-15/+33
| | | | | | | | | | | | This addresses several issues in a similar vein: - Use the Unicode APIs when possible, running nm on clang shows that we only use Unicode APIs except for FormatMessage, CreateSemaphore, and GetModuleHandle. AFAICT, the latter two are coming from MinGW and not LLVM itself. - Make getMainExecutable more resilient. It previously considered return values of zero from ::GetModuleFileNameA to be acceptable. llvm-svn: 192096
* Remove some instructions that seem to only exist to trick the filtering ↵Craig Topper2013-10-071-12/+0
| | | | | | checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. llvm-svn: 192090
* Remove FsMOVAPSrr and friends. They have no patterns and are no longer ↵Craig Topper2013-10-072-29/+4
| | | | | | selected anywhere. llvm-svn: 192089
* Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to ↵Craig Topper2013-10-072-1/+50
| | | | | | | | register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior and instruction selection already does this. llvm-svn: 192088
* Add disassembler support for long encodings for INC/DEC in 32-bit mode.Craig Topper2013-10-071-1/+15
| | | | llvm-svn: 192086
* Revert "Revert "Windows: Add support for unicode command lines""David Majnemer2013-10-077-82/+155
| | | | | | | This reverts commit r192070 which reverted r192069, I forgot to regenerate the configure scripts. llvm-svn: 192079
* Fix some assert messages to say the correct opcode name. Looks like one ↵Craig Topper2013-10-061-7/+7
| | | | | | assert got copy and pasted to many places. llvm-svn: 192078
* Revert "Windows: Add support for unicode command lines"David Majnemer2013-10-067-156/+83
| | | | | | | This is causing MinGW bots to fail. This reverts commit r192069. llvm-svn: 192070
* Windows: Add support for unicode command linesDavid Majnemer2013-10-067-83/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The MSVCRT deliberately sends main() code-page specific characters. This isn't too useful to LLVM as we end up converting the arguments to UTF-16 and subsequently attempt to use the result as, for example, a file name. Instead, we need to have the ability to access the Unicode command line and transform it to UTF-8. This has the distinct advantage over using the MSVC-specific wmain() function as our entry point because: - It doesn't work on cygwin. - It only work on MinGW with caveats and only then on certain versions. - We get to keep our entry point as main(). :) N.B. This patch includes fixes to other parts of lib/Support/Windows s.t. we would be able to take advantage of getting the Unicode paths. E.G. clang spawning clang -cc1 would want to give it Unicode arguments. Reviewers: aaron.ballman, Bigcheese, rnk, ruiu Reviewed By: rnk CC: llvm-commits, ygao Differential Revision: http://llvm-reviews.chandlerc.com/D1834 llvm-svn: 192069
* Add support for aliases with linkonce_odr.Rafael Espindola2013-10-063-11/+10
| | | | | | This will be used to extend constructor aliases in clang. llvm-svn: 192066
* X86: Don't fold spills into SSE operations if the stack is unaligned.Benjamin Kramer2013-10-061-0/+4
| | | | | | | Regalloc can emit unaligned spills nowadays, but we can't fold the spills into SSE ops if we can't guarantee alignment. PR12250. llvm-svn: 192064
* AVX-512: added scalar convert instructions and intrinsics.Elena Demikhovsky2013-10-063-13/+189
| | | | | | Fixed load folding in VPERM2I instruction. llvm-svn: 192063
* [Sparc] Do not emit nop after fcmp* instruction with V9.Venkatraman Govindaraju2013-10-062-7/+22
| | | | llvm-svn: 192056
* AVX-512: fixed shuffle loweringElena Demikhovsky2013-10-062-1/+15
| | | | | | in case of BLEND and added VSHUFPS patterns. llvm-svn: 192055
* [Sparc] Custom lower addc/adde/subc/sube on i64 in sparc64.Venkatraman Govindaraju2013-10-062-7/+55
| | | | | | This is required because i64 is a legal type but addxcc/subxcc reads icc carry bit, which are 32 bit conditional codes. llvm-svn: 192054
* [Sparc] Use addxcc/subxcc for adde/sube instead of addx/subx.Venkatraman Govindaraju2013-10-061-4/+4
| | | | | | addx/subx does not modify conditional codes whereas addxcc/subxx does. llvm-svn: 192053
* Add TBM instructions to loading folding tables.Craig Topper2013-10-051-1/+21
| | | | llvm-svn: 192046
* Rename this feature to "cx16" to match gcc's flag name. Apparently these stringsNick Lewycky2013-10-051-1/+1
| | | | | | are directly tied to the flag names in clang with no remapping in between? llvm-svn: 192044
* Emit a better error when running out of registers on inline asm.Benjamin Kramer2013-10-052-4/+6
| | | | | | | | | The most likely case where this error happens is when the user specifies too many register operands. Don't make it look like an internal LLVM bug when we can see that the error is coming from an inline asm instruction. For other instructions we keep the "ran out of registers" error. llvm-svn: 192041
* Remove underscores from TBM instruction names for consistency with other ↵Craig Topper2013-10-051-24/+24
| | | | | | instruction naming. llvm-svn: 192040
* Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns ↵Craig Topper2013-10-051-39/+20
| | | | | | are sufficient. llvm-svn: 192039
* Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into ↵Craig Topper2013-10-051-0/+6
| | | | | | (sub -2, x). llvm-svn: 192037
* Remove some really nasty uses of hasRawTextSupport.Rafael Espindola2013-10-0519-231/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When MC was first added, targets could use hasRawTextSupport to keep features working before they were added to the MC interface. The design goal of MC is to provide an uniform api for printing assembly and object files. Short of relaxations and other corner cases, a object file is just another representation of the assembly. It was never the intention that targets would keep doing things like if (hasRawTextSupport()) Set flags in one way. else Set flags in another way. When they do that they create two code paths and the object file is no longer just another representation of the assembly. This also then requires testing with llc -filetype=obj, which is extremelly brittle. This patch removes some of these hacks by replacing them with smaller ones. The ARM flag setting is trivial, so I just moved it to the constructor. For Mips, the patch adds two temporary hack directives that allow the assembly to represent the same things as the object file was already able to. The hope is that the mips developers will replace the hack directives with the same ones that gas uses and drop the -print-hack-directives flag. I will also try to implement a target streamer interface, so that we can move this out of the common code. In summary, for any new work, two rules of the thumb are * Don't use "llc -filetype=obj" in tests. * Don't add calls to hasRawTextSupport. llvm-svn: 192035
* Implement aarch64 neon instruction set AdvSIMD (Across).Jiangning Liu2013-10-052-0/+144
| | | | llvm-svn: 192028
* Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences ↵Craig Topper2013-10-051-0/+27
| | | | | | of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon. llvm-svn: 192026
* [Sparc] Use correct alignment while loading/storing fp128 values.Venkatraman Govindaraju2013-10-051-4/+13
| | | | llvm-svn: 192023
* Adding multiple GOT handling to RuntimeDyldELFAndrew Kaylor2013-10-052-59/+81
| | | | | | Patch by Ashok Thirumurthi llvm-svn: 192020
* Debug Info: In DIBuilder, the derived-from field of a DW_TAG_pointer_typeManman Ren2013-10-055-87/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | is updated to use DITypeRef. Move isUnsignedDIType and getOriginalTypeSize from DebugInfo.h to be static helper functions in DwarfCompileUnit. We already have a static helper function "isTypeSigned" in DwarfCompileUnit, and a pointer to DwarfDebug is added to resolve the derived-from field. All three functions need to go across link for derived-from fields, so we need to get hold of a type identifier map. A pointer to DwarfDebug is also added to DbgVariable in order to resolve the derived-from field. Debug info verifier is updated to check a derived-from field is a TypeRef. Verifier will not go across link for derived-from fields, in debug info finder, we go across the link to add derived-from fields to types. Function getDICompositeType is only used by dragonegg and since dragonegg does not generate identifier for types, we use an empty map to resolve the derived-from field. When printing a derived-from field, we use DITypeRef::getName to either return the type identifier or getName of the DIType. A paired commit at clang is required due to changes to DIBuilder. llvm-svn: 192018
* Reorganize some member variables and update a comment.Eric Christopher2013-10-051-6/+6
| | | | llvm-svn: 192017
* Fix one comment and update another. Slightly reformat.Eric Christopher2013-10-052-4/+3
| | | | llvm-svn: 192016
* [Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP ↵Venkatraman Govindaraju2013-10-051-1/+1
| | | | | | with fp128 operand. llvm-svn: 192015
* Add a resolve method on CompileUnit that forwards to DwarfDebug.Eric Christopher2013-10-052-8/+13
| | | | llvm-svn: 192014
* Debug info: Don't crash in SelectionDAGISel when a vreg that is beingAdrian Prantl2013-10-051-3/+7
| | | | | | | | pointed to by a dbg_value belonging to a function argument is eliminated during instruction selection. rdar://problem/15094721. llvm-svn: 192011
* Make a bunch of CompileUnit member functions private.Eric Christopher2013-10-052-36/+38
| | | | llvm-svn: 192009
* [Sparc] Correct the floating point conditional code mapping in ↵Venkatraman Govindaraju2013-10-041-8/+8
| | | | | | GetOppositeBranchCondition(). llvm-svn: 192006
* Minor formatting/comment rewording/etc.David Blaikie2013-10-041-5/+3
| | | | llvm-svn: 192005
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