summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* Revert "Add a target legalize hook for SplitVectorOperand"Rafael Espindola2013-07-262-5/+1
| | | | | | | | | | This reverts commit 187198. It broke the bots. The soft float test probably needs a -triple because of name differences. On the hard float test I am getting a "roundss $1, %xmm0, %xmm0", instead of "vroundss $1, %xmm0, %xmm0, %xmm0". llvm-svn: 187201
* Add a target legalize hook for SplitVectorOperandJustin Holewinski2013-07-262-1/+5
| | | | | | | | | | | | CustomLowerNode was not being called during SplitVectorOperand, meaning custom legalization could not be used by targets. This also adds a test case for NVPTX that depends on this custom legalization. Differential Revision: http://llvm-reviews.chandlerc.com/D1195 llvm-svn: 187198
* test commitRichard Osborne2013-07-261-1/+1
| | | | llvm-svn: 187195
* [XCore] Add TODO regarding byval structsRichard Osborne2013-07-261-0/+2
| | | | llvm-svn: 187193
* Re-implement the analysis of uses in mem2reg to be significantly moreChandler Carruth2013-07-261-87/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | robust. It now uses an InstVisitor and worklist to actually walk the uses of the Alloca transitively and detect the pattern which we can directly promote: loads & stores of the whole alloca and instructions we can completely ignore. Also, with this new implementation teach both the predicate for testing whether we can promote and the promotion engine itself to use the same code so we no longer have strange divergence between the two code paths. I've added some silly test cases to demonstrate that we can handle slightly more degenerate code patterns now. See the below for why this is even interesting. Performance impact: roughly 1% regression in the performance of SROA or ScalarRepl on a large C++-ish test case where most of the allocas are basically ready for promotion. The reason is because of silly redundant work that I've left FIXMEs for and which I'll address in the next commit. I wanted to separate this commit as it changes the behavior. Once the redundant work in removing the dead uses of the alloca is fixed, this code appears to be faster than the old version. =] So why is this useful? Because the previous requirement for promotion required a *specific* visit pattern of the uses of the alloca to verify: we *had* to look for no more than 1 intervening use. The end goal is to have SROA automatically detect when an alloca is already promotable and directly hand it to the mem2reg machinery rather than trying to partition and rewrite it. This is a 25% or more performance improvement for SROA, and a significant chunk of the delta between it and ScalarRepl. To get there, we need to make mem2reg actually capable of promoting allocas which *look* promotable to SROA without have SROA do tons of work to massage the code into just the right form. This is actually the tip of the iceberg. There are tremendous potential savings we can realize here by de-duplicating work between mem2reg and SROA. llvm-svn: 187191
* Fix more Intel syntax issues with FP instruction aliases. Test cases coming ↵Craig Topper2013-07-261-8/+8
| | | | | | in a subsequent patch. llvm-svn: 187187
* Make .bc en/decoding of AttrKind stableTobias Grosser2013-07-263-4/+216
| | | | | | | | | | | | | | | The bitcode representation attribute kinds are encoded into / decoded from should be independent of the current set of LLVM attributes and their position in the AttrKind enum. This patch explicitly encodes attributes to fixed bitcode values. With this patch applied, LLVM does not silently misread attributes written by LLVM 3.3. We also enhance the decoding slightly such that an error message is printed if an unknown AttrKind encoding was dected. Bonus: Dropping bitcode attributes from AttrKind is now easy, as old AttrKinds do not need to be kept to support the Bitcode reader. llvm-svn: 187186
* Take advantage of the register enums being in order to remove a couple ↵Craig Topper2013-07-261-18/+4
| | | | | | static tables. llvm-svn: 187182
* [PowerPC] Support powerpc64le as a syntax-checking target.Bill Schmidt2013-07-2616-14/+62
| | | | | | | | | | | | | | | | | | | | | | | This patch provides basic support for powerpc64le as an LLVM target. However, use of this target will not actually generate little-endian code. Instead, use of the target will cause the correct little-endian built-in defines to be generated, so that code that tests for __LITTLE_ENDIAN__, for example, will be correctly parsed for syntax-only testing. Code generation will otherwise be the same as powerpc64 (big-endian), for now. The patch leaves open the possibility of creating a little-endian PowerPC64 back end, but there is no immediate intent to create such a thing. The LLVM portions of this patch simply add ppc64le coverage everywhere that ppc64 coverage currently exists. There is nothing of any import worth testing until such time as little-endian code generation is implemented. In the corresponding Clang patch, there is a new test case variant to ensure that correct built-in defines for little-endian code are generated. llvm-svn: 187179
* PPC32 va_list is an actual structure so va_copy needs to copy the wholeRoman Divacky2013-07-252-1/+23
| | | | | | | structure not just a pointer. This implements that and thus fixes va_copy on PPC32. Fixes #15286. Both bug and patch by Florian Zeitz! llvm-svn: 187158
* Debug Info: update comments and add a FIXME.Manman Ren2013-07-251-2/+5
| | | | llvm-svn: 187157
* Debug Info: improve the verifier to check field types.Manman Ren2013-07-251-0/+4
| | | | | | | Make sure the context field of DIType is MDNode. Fix testing cases to make them pass the verifier. llvm-svn: 187150
* Remove the mblaze backend from llvm.Rafael Espindola2013-07-2574-10036/+1
| | | | | | Approval in here http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-July/064169.html llvm-svn: 187145
* RegAllocGreedy comment.Andrew Trick2013-07-251-1/+2
| | | | llvm-svn: 187141
* Evict local live ranges if they can be reassigned.Andrew Trick2013-07-251-1/+29
| | | | | | | | | | | | | | | | The previous change to local live range allocation also suppressed eviction of local ranges. In rare cases, this could result in more expensive register choices. This commit actually revives a feature that I added long ago: check if live ranges can be reassigned before eviction. But now it only happens in rare cases of evicting a local live range because another local live range wants a cheaper register. The benefit is improved code size for some benchmarks on x86 and armv7. I measured no significant compile time increase and performance changes are noise. llvm-svn: 187140
* Allocate local registers in order for optimal coloring.Andrew Trick2013-07-251-4/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also avoid locals evicting locals just because they want a cheaper register. Problem: MI Sched knows exactly how many registers we have and assumes they can be colored. In cases where we have large blocks, usually from unrolled loops, greedy coloring fails. This is a source of "regressions" from the MI Scheduler on x86. I noticed this issue on x86 where we have long chains of two-address defs in the same live range. It's easy to see this in matrix multiplication benchmarks like IRSmk and even the unit test misched-matmul.ll. A fundamental difference between the LLVM register allocator and conventional graph coloring is that in our model a live range can't discover its neighbors, it can only verify its neighbors. That's why we initially went for greedy coloring and added eviction to deal with the hard cases. However, for singly defined and two-address live ranges, we can optimally color without visiting neighbors simply by processing the live ranges in instruction order. Other beneficial side effects: It is much easier to understand and debug regalloc for large blocks when the live ranges are allocated in order. Yes, global allocation is still very confusing, but it's nice to be able to comprehend what happened locally. Heuristics could be added to bias register assignment based on instruction locality (think late register pairing, banks...). Intuituvely this will make some test cases that are on the threshold of register pressure more stable. llvm-svn: 187139
* Add a way to add a kind-value string pair to an attribute.Bill Wendling2013-07-251-0/+7
| | | | llvm-svn: 187138
* typo.Adrian Prantl2013-07-251-1/+1
| | | | llvm-svn: 187135
* AArch64: fix even more JIT failuresTim Northover2013-07-252-4/+4
| | | | | | | The last patch corrected some issues, but constant-pool entries had actual codegen bugs in the large memory model (which MCJIT uses). llvm-svn: 187126
* Don't end a file name with a dot. It looks odd.Rafael Espindola2013-07-251-1/+2
| | | | llvm-svn: 187124
* AArch64: don't mask off shift bits when processing JIT relocations.Tim Northover2013-07-251-4/+4
| | | | | | | This should actually make the MCJIT tests pass again on AArch64. I don't know how I missed their failure before. llvm-svn: 187120
* [SystemZ] Rework compare and branch supportRichard Sandiford2013-07-255-62/+129
| | | | | | | | | | | | | | Before the patch we took advantage of the fact that the compare and branch are glued together in the selection DAG and fused them together (where possible) while emitting them. This seemed to work well in practice. However, fusing the compare so early makes it harder to remove redundant compares in cases where CC already has a suitable value. This patch therefore uses the peephole analyzeCompare/optimizeCompareInstr pair of functions instead. No behavioral change intended, but it paves the way for a later patch. llvm-svn: 187116
* [SystemZ] Add LOCR and LOCGRRichard Sandiford2013-07-255-0/+118
| | | | llvm-svn: 187113
* [SystemZ] Add LOC and LOCGRichard Sandiford2013-07-254-0/+75
| | | | | | | As with the stores, these instructions can trap when the condition is false, so they are only used for things like (cond ? x : *ptr). llvm-svn: 187112
* [SystemZ] Add STOC and STOCGRichard Sandiford2013-07-257-51/+126
| | | | | | | | These instructions are allowed to trap even if the condition is false, so for now they are only used for "*ptr = (cond ? x : *ptr)"-style constructs. llvm-svn: 187111
* MI Sched: Register pressure heuristics.Andrew Trick2013-07-251-8/+32
| | | | | | Consider which set is being increased or decreased before comparing. llvm-svn: 187110
* MI Sched: track register pressure by importance of the set, not weight of ↵Andrew Trick2013-07-251-14/+20
| | | | | | the units. llvm-svn: 187109
* Dump LIS before regalloc. MI sched changes them.Andrew Trick2013-07-252-2/+4
| | | | llvm-svn: 187107
* Debug Info: improve the verifier to check field types.Manman Ren2013-07-251-0/+45
| | | | | | | | Make sure the context and type fields are MDNodes. We will generate verification errors if those fields are non-empty strings. Fix testing cases to make them pass the verifier. llvm-svn: 187106
* Respect llvm.used in Internalize.Rafael Espindola2013-07-253-21/+41
| | | | | | | | | | | | | | | The language reference says that: "If a symbol appears in the @llvm.used list, then the compiler, assembler, and linker are required to treat the symbol as if there is a reference to the symbol that it cannot see" Since even the linker cannot see the reference, we must assume that the reference can be using the symbol table. For example, a user can add __attribute__((used)) to a debug helper function like dump and use it from a debugger. llvm-svn: 187103
* Check that TD isn't NULL before dereferencing it down this path.Nick Lewycky2013-07-251-1/+1
| | | | llvm-svn: 187099
* Make these methods const correct.Rafael Espindola2013-07-252-4/+3
| | | | | | Thanks to Nick Lewycky for noticing it. llvm-svn: 187098
* Replace the "NoFramePointerElimNonLeaf" target option with a function attribute.Bill Wendling2013-07-253-1/+8
| | | | | | | | There's no need to specify a flag to omit frame pointer elimination on non-leaf nodes...(Honestly, I can't parse that option out.) Use the function attribute stuff instead. llvm-svn: 187093
* Fix a bug in IfConverter with nested predicates.Quentin Colombet2013-07-241-3/+3
| | | | | | | | | | | | | | | | | | | Prior to this patch, IfConverter may widen the cases where a sequence of instructions were executed because of the way it uses nested predicates. This result in incorrect execution. For instance, Let A be a basic block that flows conditionally into B and B be a predicated block. B can be predicated with A.BrToBPredicate into A iff B.Predicate is less "permissive" than A.BrToBPredicate, i.e., iff A.BrToBPredicate subsumes B.Predicate. The IfConverter was checking the opposite: B.Predicate subsumes A.BrToBPredicate. <rdar://problem/14379453> llvm-svn: 187071
* [mips] Make MipsAsmParser::parseCCRRegs return NoMatch instead of ParseFailAkira Hatanaka2013-07-241-2/+2
| | | | | | | when there wasn't a match. This behavior is consistent with other register parsing methods. llvm-svn: 187063
* Debug Info: improve the Finder.Manman Ren2013-07-241-0/+1
| | | | | | | Improve the Finder to handle context of a DIVariable used by DbgValueInst. Fix testing cases to make them pass the verifier. llvm-svn: 187052
* TRE: Move class into anonymous namespace.Benjamin Kramer2013-07-241-4/+6
| | | | | | While there shrink a dangerously large SmallPtrSet. llvm-svn: 187050
* Don't leak when expanding response files.Rafael Espindola2013-07-241-17/+15
| | | | | | | | | | | | | | Before this patch we would strdup each argument. If one was a response file, we would replace it with the response file contents, leaking the original strdup result. We now don't strdup the originals and let StringSaver free any memory it allocated. This also saves a bit of malloc traffic when response files are not used. Leak found by the valgrind build bot. llvm-svn: 187042
* Delete the buffer in createObjectFile if it fails.Rafael Espindola2013-07-241-1/+4
| | | | | | | | | | The Binary constructor takes ownership of the memory buffer. This is a fairly unfortunate interface, but for now make createObjectFile consistent with it by also deleting the buffer if it fails. Fixes a leak in llvm-ar found by the valgrind bots. llvm-svn: 187039
* [test commit] Minor comment change.Petar Jovanovic2013-07-241-3/+3
| | | | | | Testing commit access credentials. llvm-svn: 187032
* Fix a problem I introduced in r187029 where we would over-eagerlyChandler Carruth2013-07-241-3/+9
| | | | | | | | schedule an alloca for another iteration in SROA. This only showed up with a mixture of promotable and unpromotable selects and phis. Added a test case for this. llvm-svn: 187031
* I'm starting to commit KNL backend. I'll push patches one-by-one. This patch ↵Elena Demikhovsky2013-07-248-27/+190
| | | | | | | | includes support for the extended register set XMM16-31, YMM16-31, ZMM0-31. The full ISA you can see here: http://software.intel.com/en-us/intel-isa-extensions llvm-svn: 187030
* Fix PR16687 where we were incorrectly promoting an alloca that hadChandler Carruth2013-07-241-12/+29
| | | | | | | | | | | | | | | | | | | | | | pending speculation for a phi node. The problem here is that we were using growth of the specluation set as an indicator of whether speculation would occur, and if the phi node is already in the set we don't see it grow. This is a symptom of the fact that this signal is a total hack. Unfortunately, I couldn't really come up with a non-hacky way of signaling that promotion remains valid *after* speculation occurs, such that we only speculate when all else looks good for promotion. In the end, I went with at least a much more explicit approach of doing the work of queuing inside the phi and select processing and setting a preposterously named flag to convey that we're in the special state of requiring speculating before promotion. Thanks to Richard Trieu and Nick Lewycky for the excellent work reducing a testcase for this from a pretty giant, nasty assert in a big application. =] The testcase was excellent. llvm-svn: 187029
* allow tests to run on powerpc-darwin8 again, checking for __ppc__David Fang2013-07-241-2/+2
| | | | llvm-svn: 187027
* Split generated asm mnemonic matching table into a separate table for each ↵Craig Topper2013-07-245-1/+5
| | | | | | | | asm variant. This removes the need to store the asm variant in each row of the single table that existed before. Shaves ~16K off the size of X86AsmParser.o. llvm-svn: 187026
* Revert accidental commit.Craig Topper2013-07-241-1/+1
| | | | llvm-svn: 187021
* Fix aliases for shrd/shld to handle Intel syntax properly. Also suppress ↵Craig Topper2013-07-242-14/+14
| | | | | | them from being used by the asm printer. llvm-svn: 187020
* [mips] Use pristine object file while processing relocations.Akira Hatanaka2013-07-241-7/+20
| | | | | | | | | | | | | | | | | | | Similar to ARM change r182800, dynamic linker will read bits/addends from the original object rather than from the object that might have been patched previously. For the purpose of relocations for MCJIT stubs on MIPS, we internally use otherwise unused MIPS relocations. The change also enables MCJIT unit tests for MIPS (EL/BE), and the following two tests now pass: - MCJITTest.return_global and - MCJITTest.multiple_functions. These issues have been tracked as Bug 16250. Patch by Petar Jovanovic. llvm-svn: 187019
* Replace with a "null" RAUW with an assert since we'd actually likeEric Christopher2013-07-241-8/+8
| | | | | | to assume we're replacing. Clarify comments. llvm-svn: 187018
* Remove dead code.Eric Christopher2013-07-241-5/+0
| | | | llvm-svn: 187017
OpenPOWER on IntegriCloud