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* [msan] Make sure that report callbacks do not get merged.Evgeniy Stepanov2012-11-291-0/+8
| | | | llvm-svn: 168873
* Initial commit of MemorySanitizer.Evgeniy Stepanov2012-11-293-0/+1421
| | | | | | Compiler pass only. llvm-svn: 168866
* [asan/tsan] initialize the asan/tsan callbacks in runOnFunction as opposed ↵Kostya Serebryany2012-11-292-37/+48
| | | | | | to doInitialization. This is required to allow the upcoming changes in PassManager behavior llvm-svn: 168864
* [asan] when checking the noreturn attribute on the call, also check it on ↵Kostya Serebryany2012-11-291-1/+9
| | | | | | the callee llvm-svn: 168861
* Cleaned up a couple of comments.Preston Briggs2012-11-291-4/+4
| | | | llvm-svn: 168854
* Use MCPhysReg for RegisterClassInfo allocation orders.Jakob Stoklund Olesen2012-11-296-15/+17
| | | | | | This saves a bit of memory. llvm-svn: 168852
* Instruction::isAssociative() returns true for fmul/fadd if they are tagged ↵Shuxin Yang2012-11-291-0/+14
| | | | | | | | "unsafe" mode. Approved by: Eli and Michael. llvm-svn: 168848
* Avoid rewriting instructions twice.Jakob Stoklund Olesen2012-11-291-0/+9
| | | | | | | | | This could cause miscompilations in targets where sub-register composition is not always idempotent (ARM). <rdar://problem/12758887> llvm-svn: 168837
* Issue a fatal error if the line doesn't have a regular expression.Nick Lewycky2012-11-291-6/+12
| | | | | | | Also a couple not-user-visible changes; using empty() instead of size(), and make inSection() not insert NULL Regex*'s into StringMap when doing a lookup. llvm-svn: 168833
* When combining consecutive stores allow loads in between the stores, if the ↵Nadav Rotem2012-11-291-3/+61
| | | | | | loads do not alias. llvm-svn: 168832
* When we delete a dead basic block, see if any of its successors are dead andBill Wendling2012-11-281-3/+13
| | | | | | delete those as well. llvm-svn: 168829
* Define signed const-ext immediate operands and their predicates.Jyotsna Verma2012-11-282-0/+122
| | | | llvm-svn: 168810
* ARM: Implement CanLowerReturn so large vectors get expanded into sret.Benjamin Kramer2012-11-282-0/+17
| | | | | | Fixes 14337. llvm-svn: 168809
* Make the LiveRegMatrix analysis available to targets.Jakob Stoklund Olesen2012-11-2820-564/+21
| | | | | | | | | | | No functional change, just moved header files. Targets can inject custom passes between register allocation and rewriting. This makes it possible to tweak the register allocation before rewriting, using the full global interference checking available from LiveRegMatrix. llvm-svn: 168806
* Add backreference matching capabilities to Support/Regex, withEli Bendersky2012-11-282-2/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | appropriate unit tests. This change in itself is not expected to affect any functionality at this point, but it will serve as a stepping stone to improve FileCheck's variable matching capabilities. Luckily, our regex implementation already supports backreferences, although a bit of hacking is required to enable it. It supports both Basic Regular Expressions (BREs) and Extended Regular Expressions (EREs), without supporting backrefs for EREs, following POSIX strictly in this respect. And EREs is what we actually use (rightly). This is contrary to many implementations (including the default on Linux) of POSIX regexes, that do allow backrefs in EREs. Adding backref support to our EREs is a very simple change in the regcomp parsing code. I fail to think of significant cases where it would clash with existing things, and can bring more versatility to the regexes we write. There's always the danger of a backref in a specially crafted regex causing exponential matching times, but since we mainly use them for testing purposes I don't think it's a big problem. [it can also be placed behind a flag specific to FileCheck, if needed]. For more details, see: * http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-November/055840.html * http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121126/156878.html llvm-svn: 168802
* MCJIT depends on JIT.Benjamin Kramer2012-11-281-1/+1
| | | | | | | Unbreaks the CMake shared library build. This is nasty and should be fixed eventually. llvm-svn: 168800
* Fix initial frame state on powerpc64.Ulrich Weigand2012-11-281-1/+1
| | | | | | | | | The createPPCMCAsmInfo routine used PPC::R1 as the initial frame pointer register, but on PPC64 the 32-bit R1 register does not have a corresponding DWARF number, causing invalid CIE initial frame state to be emitted. Fix by using PPC::X1 instead. llvm-svn: 168799
* Fix warning. [-Wunused-variable]Patrik Hägglund2012-11-281-1/+1
| | | | llvm-svn: 168792
* Add error handling in getInt.Patrik Hägglund2012-11-281-38/+36
| | | | | | | | | Accordingly, update a testcase with a broken datalayout string. Also, we never parse negative numbers, because '-' is used as a separator. Therefore, use unsigned as result type. llvm-svn: 168785
* [asan] Split AddressSanitizer into two passes (FunctionPass, ModulePass), ↵Kostya Serebryany2012-11-282-25/+26
| | | | | | LLVM part. This requires a clang part which will follow. llvm-svn: 168781
* Add back support for reading and parsing 'deplibs'.Bill Wendling2012-11-285-0/+34
| | | | | | | This is for backwards compatibility for pre-3.x bc files. The code reads the code, but does nothing with it. llvm-svn: 168779
* misched: Analysis that partitions the DAG into subtrees.Andrew Trick2012-11-282-56/+222
| | | | | | | | | | | This is a simple, cheap infrastructure for analyzing the shape of a DAG. It recognizes uniform DAGs that take the shape of bottom-up subtrees, such as the included matrix multiplication example. This is useful for heuristics that balance register pressure with ILP. Two canonical expressions of the heuristic are implemented in scheduling modes: -misched-ilpmin and -misched-ilpmax. llvm-svn: 168773
* misched: rename ScheduleDAGILP to ScheduleDFS to prepare for other heuristics.Andrew Trick2012-11-282-2/+2
| | | | llvm-svn: 168772
* misched: better alias analysis.Andrew Trick2012-11-281-2/+3
| | | | | | | | | | | | | This fixes a hole in the "cheap" alias analysis logic implemented within the DAG builder itself, regardless of whether proper alias analysis is enabled. It now handles this pattern produced by LSR+CodeGenPrepare. %sunkaddr1 = ptrtoint * %obj to i64 %sunkaddr2 = add i64 %sunkaddr1, %lsr.iv %sunkaddr3 = inttoptr i64 %sunkaddr2 to i32* store i32 %v, i32* %sunkaddr3 llvm-svn: 168768
* misched: Debug output fix. Use an always valid iterator.Andrew Trick2012-11-281-1/+1
| | | | llvm-svn: 168767
* BBVectorize: Correctly merge SubclassOptionalDataHal Finkel2012-11-281-0/+1
| | | | | | | When two instructions are combined into a vector instruction, the resulting instruction must have the most-conservative flags. llvm-svn: 168765
* Add brief support for the fission .debug_info.dwo section forEric Christopher2012-11-281-0/+5
| | | | | | ELF output. llvm-svn: 168764
* Add comments.Eric Christopher2012-11-281-0/+4
| | | | llvm-svn: 168763
* Remove all references to TargetInstrInfoImpl.Jakob Stoklund Olesen2012-11-284-12/+12
| | | | | | This class has been merged into its super-class TargetInstrInfo. llvm-svn: 168760
* Move the guts of TargetInstrInfoImpl into the TargetInstrInfo class.Jakob Stoklund Olesen2012-11-283-691/+659
| | | | | | | The *Impl class no longer serves a purpose now that the super-class implementation is in CodeGen. llvm-svn: 168759
* Move Target{Instr,Register}Info.cpp into lib/CodeGen.Jakob Stoklund Olesen2012-11-284-2/+2
| | | | | | | | | | | | | | | | The Target library is not allowed to depend on the large CodeGen library, but the TRI and TII classes provide abstract interfaces that require both caller and callee to link to CodeGen. The implementation files for these classes provide default implementations of some of the hooks. These methods may need to reference CodeGen, so they belong in that library. We already have a number of methods implemented in the TargetInstrInfoImpl sub-class because of that. I will merge that class into the parent next. llvm-svn: 168758
* Moving SectionMemoryManager to MCJIT to avoid cross dependency between JIT ↵Andrew Kaylor2012-11-283-1/+1
| | | | | | and RuntimeDyld llvm-svn: 168755
* Revert r168630, r168631, and r168633 as these are causing nightly test failures.Chad Rosier2012-11-284-2/+4
| | | | llvm-svn: 168751
* This patch makes medium code model the default for 64-bit PowerPC ELF.Bill Schmidt2012-11-271-0/+5
| | | | | | | | | When the CodeGenInfo is to be created for the PPC64 target machine, a default code-model selection is converted to CodeModel::Medium provided we are not targeting the Darwin OS. Defaults for Darwin are unaffected. llvm-svn: 168747
* Attempt to make the comments for dwarf debug look more likeEric Christopher2012-11-272-274/+200
| | | | | | the coding standard would like. llvm-svn: 168737
* Reapply section moving, make sure string section is output last.Eric Christopher2012-11-271-24/+54
| | | | llvm-svn: 168736
* [arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier2012-11-271-9/+7
| | | | | | | | | classes. The vast majority of the remaining issues are due to uses of invalid registers, which are defined by getRegForValue(). Those will be a little more challenging to cleanup. rdar://12719844 llvm-svn: 168735
* [arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier2012-11-271-2/+4
| | | | | | | classes. rdar://12719844 llvm-svn: 168733
* [arm fast-isel] Appease the machine verifier by using the proper registerChad Rosier2012-11-271-5/+6
| | | | | | | classes. Also a bit of cleanup. rdar://12719844 llvm-svn: 168728
* Moving SectionMemoryManager into RuntimeDyld and adding unit tests for it.Andrew Kaylor2012-11-272-0/+227
| | | | | | | | The SectionMemoryManager now supports (and requires) applying section-specific page permissions. Clients using this memory manager must call either MCJIT::finalizeObject() or SectionMemoryManager::applyPermissions() before executing JITed code. See r168718 for changes from the previous implementation. llvm-svn: 168721
* Modified depends() to recognize that when all levels are "=" andPreston Briggs2012-11-271-1/+16
| | | | | | | | | there's no possible loo-independent dependence, then there's no dependence. Updated all test result appropriately. llvm-svn: 168719
* CSE: allow PerformTrivialCoalescing to check copies across basic blockManman Ren2012-11-271-2/+0
| | | | | | | | | | | | | | | | boundaries. Given the following case: BB0 %vreg1<def> = SUBrr %vreg0, %vreg7 %vreg2<def> = COPY %vreg7 BB1 %vreg10<def> = SUBrr %vreg0, %vreg2 We should be able to CSE between SUBrr in BB0 and SUBrr in BB1. rdar://12462006 llvm-svn: 168717
* instcombine: Don't replace all uses for instructions with no usesMeador Inge2012-11-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | My commit to migrate the printf simplifiers from the simplify-libcalls in r168604 introduced a regression reported by Duncan [1]. The problem is that in some cases the library call simplifier can return a new value that has no uses and the new value's type is different than the old value's type (which is fine because there are no uses). The specific case that triggered the bug looked something like: declare void @printf(i8*, ...) ... call void (i8*, ...)* @printf(i8* %fmt) Which we want to optimized into: call i32 @putchar(i32 104) However, the code was attempting to replace all uses of the printf with the putchar and the types differ, hence a crash. This is fixed by *just* deleting the original instruction when there are no uses. The old simplify-libcalls pass is already doing something similar. [1] http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-November/056338.html llvm-svn: 168716
* Remove duplicated #includes.Jakub Staszak2012-11-271-4/+0
| | | | llvm-svn: 168712
* SCEV: Even if the latch terminator is foldable we can't deduce the result of ↵Benjamin Kramer2012-11-271-3/+4
| | | | | | | | an unrelated condition with it. Fixes PR14432. llvm-svn: 168711
* X86: do not fold load instructions such as [V]MOVS[S|D] to other instructionsManman Ren2012-11-271-0/+15
| | | | | | | | | | | when the destination register is wider than the memory load. These load instructions load from m32 or m64 and set the upper bits to zero, while the folded instructions may accept m128. rdar://12721174 llvm-svn: 168710
* This patch implements medium code model support for 64-bit PowerPC.Bill Schmidt2012-11-278-10/+235
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default for 64-bit PowerPC is small code model, in which TOC entries must be addressable using a 16-bit offset from the TOC pointer. Additionally, only TOC entries are addressed via the TOC pointer. With medium code model, TOC entries and data sections can all be addressed via the TOC pointer using a 32-bit offset. Cooperation with the linker allows 16-bit offsets to be used when these are sufficient, reducing the number of extra instructions that need to be executed. Medium code model also does not generate explicit TOC entries in ".section toc" for variables that are wholly internal to the compilation unit. Consider a load of an external 4-byte integer. With small code model, the compiler generates: ld 3, .LC1@toc(2) lwz 4, 0(3) .section .toc,"aw",@progbits .LC1: .tc ei[TC],ei With medium model, it instead generates: addis 3, 2, .LC1@toc@ha ld 3, .LC1@toc@l(3) lwz 4, 0(3) .section .toc,"aw",@progbits .LC1: .tc ei[TC],ei Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the 32-bit offset of ei's TOC entry from the TOC base pointer. Similarly, .LC1@toc@l is a relocation requesting the lower 16 bits. Note that if the linker determines that ei's TOC entry is within a 16-bit offset of the TOC base pointer, it will replace the "addis" with a "nop", and replace the "ld" with the identical "ld" instruction from the small code model example. Consider next a load of a function-scope static integer. For small code model, the compiler generates: ld 3, .LC1@toc(2) lwz 4, 0(3) .section .toc,"aw",@progbits .LC1: .tc test_fn_static.si[TC],test_fn_static.si .type test_fn_static.si,@object .local test_fn_static.si .comm test_fn_static.si,4,4 For medium code model, the compiler generates: addis 3, 2, test_fn_static.si@toc@ha addi 3, 3, test_fn_static.si@toc@l lwz 4, 0(3) .type test_fn_static.si,@object .local test_fn_static.si .comm test_fn_static.si,4,4 Again, the linker may replace the "addis" with a "nop", calculating only a 16-bit offset when this is sufficient. Note that it would be more efficient for the compiler to generate: addis 3, 2, test_fn_static.si@toc@ha lwz 4, test_fn_static.si@toc@l(3) The current patch does not perform this optimization yet. This will be addressed as a peephole optimization in a later patch. For the moment, the default code model for 64-bit PowerPC will remain the small code model. We plan to eventually change the default to medium code model, which matches current upstream GCC behavior. Note that the different code models are ABI-compatible, so code compiled with different models will be linked and execute correctly. I've tested the regression suite and the application/benchmark test suite in two ways: Once with the patch as submitted here, and once with additional logic to force medium code model as the default. The tests all compile cleanly, with one exception. The mandel-2 application test fails due to an unrelated ABI compatibility with passing complex numbers. It just so happens that small code model was incredibly lucky, in that temporary values in floating-point registers held the expected values needed by the external library routine that was called incorrectly. My current thought is to correct the ABI problems with _Complex before making medium code model the default, to avoid introducing this "regression." Here are a few comments on how the patch works, since the selection code can be difficult to follow: The existing logic for small code model defines three pseudo-instructions: LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for constant pool addresses. These are expanded by SelectCodeCommon(). The pseudo-instruction approach doesn't work for medium code model, because we need to generate two instructions when we match the same pattern. Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY node for medium code model, and generates an ADDIStocHA followed by either a LDtocL or an ADDItocL. These new node types correspond naturally to the sequences described above. The addis/ld sequence is generated for the following cases: * Jump table addresses * Function addresses * External global variables * Tentative definitions of global variables (common linkage) The addis/addi sequence is generated for the following cases: * Constant pool entries * File-scope static global variables * Function-scope static variables Expanding to the two-instruction sequences at select time exposes the instructions to subsequent optimization, particularly scheduling. The rest of the processing occurs at assembly time, in PPCAsmPrinter::EmitInstruction. Each of the instructions is converted to a "real" PowerPC instruction. When a TOC entry needs to be created, this is done here in the same manner as for the existing LDtoc, LDtocJTI, and LDtocCPT pseudo-instructions (I factored out a new routine to handle this). I had originally thought that if a TOC entry was needed for LDtocL or ADDItocL, it would already have been generated for the previous ADDIStocHA. However, at higher optimization levels, the ADDIStocHA may appear in a different block, which may be assembled textually following the block containing the LDtocL or ADDItocL. So it is necessary to include the possibility of creating a new TOC entry for those two instructions. Note that for LDtocL, we generate a new form of LD called LDrs. This allows specifying the @toc@l relocation for the offset field of the LD instruction (i.e., the offset is replaced by a SymbolLo relocation). When the peephole optimization described above is added, we will need to do similar things for all immediate-form load and store operations. The seven "mcm-n.ll" test cases are kept separate because otherwise the intermingling of various TOC entries and so forth makes the tests fragile and hard to understand. The above assumes use of an external assembler. For use of the integrated assembler, new relocations are added and used by PPCELFObjectWriter. Testing is done with "mcm-obj.ll", which tests for proper generation of the various relocations for the same sequences tested with the external assembler. llvm-svn: 168708
* Never use .lcomm on platforms where it does not accept an alignmentUlrich Weigand2012-11-271-2/+7
| | | | | | | | | | | argument. Instead, use a pair of .local and .comm directives. This avoids spurious differences between binaries built by the integrated assembler vs. those built by the external assembler, since the external assembler may impose alignment requirements on .lcomm symbols where the integrated assembler does not. llvm-svn: 168704
* Remove the dependent libraries feature.Bill Wendling2012-11-2712-123/+0
| | | | | | The dependent libraries feature was never used and has bit-rotted. Remove it. llvm-svn: 168694
* tsan: instrument atomic nand operationDmitry Vyukov2012-11-271-0/+2
| | | | llvm-svn: 168684
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