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* [libFuzzer] make -runs=N flag also affect the simple runner (will execute ↵Kostya Serebryany2016-02-124-3/+28
| | | | | | every input N times) llvm-svn: 260649
* AMDGPU: Fix mishandling alignment when scalarizing vector loads/storesMatt Arsenault2016-02-121-2/+5
| | | | | | | I don't think this was causing any real problems, so I'm not sure how to test for this. llvm-svn: 260646
* AMDGPU: Initialize SILowerControlFlowMatt Arsenault2016-02-123-30/+43
| | | | llvm-svn: 260645
* AMDGPU: Remove trailing whitespaceMatt Arsenault2016-02-121-4/+4
| | | | llvm-svn: 260644
* [msan] Put msan constructor in a comdat.Evgeniy Stepanov2016-02-122-14/+27
| | | | | | | | | | | | | | MSan adds a constructor to each translation unit that calls __msan_init, and does nothing else. The idea is to run __msan_init before any instrumented code. This results in multiple constructors and multiple .init_array entries in the final binary, one per translation unit. This is absolutely unnecessary; one would be enough. This change moves the constructors to a comdat group in order to drop the extra ones. llvm-svn: 260632
* [LVI] Improve select handling to use conditionPhilip Reames2016-02-121-0/+19
| | | | | | | | | | This patches teaches LVI to recognize clamp idioms (e.g. select(a > 5, a, 5) will always produce something greater than 5. The tests end up being somewhat simplistic because trying to exercise the case I actually care about (a loop with a range check on a clamped secondary induction variable) ends up tripping across a couple of other imprecisions in the analysis. Ah, the joys of LVI... Differential Revision: http://reviews.llvm.org/D16827 llvm-svn: 260627
* ARMv7k: use Cortex-A7 by default even for tvOSTim Northover2016-02-111-0/+1
| | | | | | Also actually test the default CPU from those triples. llvm-svn: 260621
* [SLP] Add debug output for extract cost (NFC)Matthew Simpson2016-02-111-4/+6
| | | | llvm-svn: 260614
* Re-apply r238452, the bug was in clang and was fixed in r260567.Quentin Colombet2016-02-111-5/+10
| | | | | | | | | | | | | | | | Original commit message: [InstCombine] Fold IntToPtr and PtrToInt into preceding loads. Currently we only fold a BitCast into a Load when the BitCast is its only user. Do the same for any no-op cast. Patch by Philip Pfaffe! Differential Revision: http://reviews.llvm.org/D9152 llvm-svn: 260612
* [libfuzzer] Removing coverage-related flags from asan options.Mike Aizatsky2016-02-111-3/+1
| | | | | | | | | | | Summary: Reasons to remove are twofold: - we don't really need coverage=1 for libfuzzer operation - makes controlling coverage for fuzzer processes non-trivial. Differential Revision: http://reviews.llvm.org/D17168 llvm-svn: 260611
* [x86] simplify getZeroVector() ; NFCISanjay Patel2016-02-111-39/+20
| | | | | | | | | | | Let DAG.getConstant() handle the splatting; there's no need to repeat that logic here. See also: http://reviews.llvm.org/rL258833 http://reviews.llvm.org/rL260582 llvm-svn: 260609
* Revert "Refactor the PassManagerBuilder: extract a ↵Mehdi Amini2016-02-111-77/+73
| | | | | | | | | | "addFunctionSimplificationPasses()"" This reverts commit r260603. I didn't intend to push it :( From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 260607
* Revert "Define the ThinLTO Pipeline"Mehdi Amini2016-02-111-43/+1
| | | | | | | | This reverts commit r260604. I didn't intend to push this now. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 260606
* Revert "Add a new insert_as() method to DenseMap and use it for ↵Mehdi Amini2016-02-111-23/+17
| | | | | | | | | | | | | ConstantUniqueMap" This reverts commit r260458. It was backported on an internal branch and broke stage2 build. Since this can lead to weird random crash I'm reverting upstream as well while investigating. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 260605
* Define the ThinLTO PipelineMehdi Amini2016-02-111-1/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: On the contrary to Full LTO, ThinLTO can afford to shift compile time from the frontend to the linker: both phases are parallel. This pipeline is based on the proposal in D13443 for full LTO. We ] didn't move forward on this proposal because the link was far too long after that. This patch refactor the "function simplification" passes that are part of the inliner loop in a helper function (this part is NFC and can be commited separately to simplify the diff). The ThinLTO pipeline integrates in the regular O2/O3 flow: - The compile phase perform the inliner with a somehow lighter function simplification. (TODO: tune the inliner thresholds here) This is intendend to simplify the IR and get rid of obvious things like linkonce_odr that will be inlined. - The link phase will run the pipeline from the start, extended with some specific passes that leverage the augmented knowledge we have during LTO. Especially after the inliner is done, a sequence of globalDCE/globalOpt is performed, followed by another run of the "function simplification" passes. The measurements on the public test suite as well as on our internal suite show an overall net improvement. The binary size for the clang executable is reduced by 5%. We're still tuning it with the bringup of ThinLTO but this should provide a good starting point. Reviewers: tejohnson Subscribers: joker.eph, llvm-commits, dexonsmith Differential Revision: http://reviews.llvm.org/D17115 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 260604
* Refactor the PassManagerBuilder: extract a "addFunctionSimplificationPasses()"Mehdi Amini2016-02-111-73/+77
| | | | | | | | It is intended to contains the passes run over a function after the inliner is done with a function and before it moves to its callers. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 260603
* [IRTranslator] Use a single virtual register to represent any Value.Quentin Colombet2016-02-111-13/+11
| | | | | | PR26161. llvm-svn: 260602
* [AArch64] Implements the lowering of formal arguments for GlobalISel.Quentin Colombet2016-02-112-0/+53
| | | | | | | | | | | | | | | | This is just a trivial implementation: - Support only arguments passed in registers. - Support only "plain" arguments, i.e., no sext/zext attribute. At this point, it is possible to play with the IRTranslator on AArch64: llc -mtriple arm64-<vendor>-<os> -print-machineinstrs <input.ll> -o - -global-isel For now, we only support the translation of program with adds and returns. Follow-up patches are on their way to add a test case (the MIRParser is not ready as it is). llvm-svn: 260600
* AMDGPU/SI: Make sure MIMG descriptors and samplers stay in SGPRsTom Stellard2016-02-115-0/+72
| | | | | | | | | | | | | | | | Summary: It's possible to have resource descriptors and samplers stored in VGPRs, either by a VMEM instruction or in the case of samplers, floating-point calculations. When this happens, we need to use v_readfirstlane to copy these values back to sgprs. Reviewers: mareko, arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D17102 llvm-svn: 260599
* Add support for phi nodes in the LLVM C API testAmaury Sechet2016-02-111-0/+4
| | | | | | | | | | | | Summary: This required to add binding to Instruction::removeFromParent so that instruction can be forward declared and then moved at the right place. Reviewers: bogner, chandlerc, echristo, dblaikie, joker.eph, Wallbraker Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17057 llvm-svn: 260597
* [Target] Add a helper function to check if an opcode is invalid after isel.Quentin Colombet2016-02-111-1/+13
| | | | llvm-svn: 260590
* AMDGPU/SI: When splitting SMRD instructions, add its users to VALU worklistTom Stellard2016-02-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | Summary: When we split SMRD instructions into two MUBUFs we were adding the users of the newly created MUBUFs to the VALU worklist. However, the only users these instructions had was the REG_SEQUENCE that was inserted by splitSMRD when the original SMRD instruction was split. We need to make sure to add the users of the original SMRD to the VALU worklist before it is split. I have a test case, but it requires one other bug fix, so it will be added in a later commt. Reviewers: mareko, arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D17101 llvm-svn: 260588
* Set load alignment on aggregate loads.Pete Cooper2016-02-111-1/+2
| | | | | | | | | | | | | | | | When optimizing a extractvalue(load), we generate a load from the aggregate type. This load didn't have alignment set and so would get the alignment of the type. This breaks when the type is packed and so the alignment should be lower. For example, loading { int, int } would give us alignment of 4, but the original load from this type may have an alignment of 1 if packed. Reviewed by David Majnemer Differential revision: http://reviews.llvm.org/D17158 llvm-svn: 260587
* Revert "LiveIntervalAnalysis: Support moving of subregister defs in handleMove"Matthias Braun2016-02-111-152/+34
| | | | | | | | | | | | This is broke a bot: http://lab.llvm.org:8011/builders/clang-cmake-aarch64-quick/builds/4703/steps/test-suite/logs/test.log Reverting while I investigate. This reverts commit r260565. llvm-svn: 260586
* [WebAssembly] Reformat WebAssemblyFrameLowering and WebAssemblyISelLoweringDerek Schuff2016-02-114-82/+76
| | | | | | | | | | Reviewers: sunfish, jfb Subscribers: jfb, dschuff Differential Revision: http://reviews.llvm.org/D17156 llvm-svn: 260585
* [SelectionDAG] change getConstant() to use the input SDLoc when building ↵Sanjay Patel2016-02-111-5/+4
| | | | | | | | | | | | | | | | | | | | | | splat vectors The code change is simple enough: instead of attaching an anonymous SDLoc to splatted vector constants, use the scalar constant's existing SDLoc since that is what is passed into getConstant() as a param. But this changes instruction scheduling, so I'll explain why that happens. The motivation for this patch starts near: http://reviews.llvm.org/rL258833 ...x86's getZeroVector() could be similarly cleaned up and I thought it would be 'NFC'. But when I made that change locally, several x86 codegen tests wiggled. It turns out that the lack of SDLoc consistency in getConstant() changes the way ScheduleDAGRRList behaves. This is because the SDLoc contains 'IROrder' and some DAG scheduler algorithms use IROrder for tie-breaking. Differential Revision: http://reviews.llvm.org/D16972 llvm-svn: 260582
* [GlobalISel] Add the necessary plumbing to lower formal arguments.Quentin Colombet2016-02-111-0/+14
| | | | llvm-svn: 260579
* DwarfDebug: emit type units immediately.Peter Collingbourne2016-02-1110-85/+88
| | | | | | | | | | | | | | | | | | | Rather than storing type units in a vector and emitting them at the end of code generation, emit them immediately and destroy them, reclaiming the memory we were using for their DIEs. In one benchmark carried out against Chromium's 50 largest (by bitcode file size) translation units, total peak memory consumption with type units decreased by median 17%, or by 7% when compared against disabling type units. Tested using check-{llvm,clang}, the GDB 7.5 test suite (with '-fdebug-types-section') and by eyeballing llvm-dwarfdump output on those Chromium translation units with split DWARF both disabled and enabled, and verifying that the only changes were to addresses and abbreviation ordering. Differential Revision: http://reviews.llvm.org/D17118 llvm-svn: 260578
* Use copy initialization.Rafael Espindola2016-02-111-2/+2
| | | | | | We can do it since getMemBuffer returns a unique_ptr. llvm-svn: 260576
* [AArch64] Trivial implementation of lower return for the IRTranslator.Quentin Colombet2016-02-112-0/+34
| | | | llvm-svn: 260574
* [X86] New pass to change byte and word instructions to zero-extending versions.Kevin B. Smith2016-02-114-0/+290
| | | | | | Differential Revision: http://reviews.llvm.org/D17032 llvm-svn: 260572
* [codeview] Fix bug around multi-level wrapper inliningReid Kleckner2016-02-111-13/+20
| | | | | | | If there were wrapper functions with no instructions of their own in the inlining tree, we would fail to emit InlineSite records for them. llvm-svn: 260571
* [AArch64] Plug the beginning of the GlobalISel pipeline.Quentin Colombet2016-02-112-1/+14
| | | | llvm-svn: 260569
* Play nice with Visual Studio and attributesQuentin Colombet2016-02-111-1/+3
| | | | llvm-svn: 260568
* [CMake] Produce an empty library for GlobalISel when not building it.Quentin Colombet2016-02-113-5/+40
| | | | | | | | | | | | | | | | The rational for this change is that LLVMBuild cannot express conditional dependencies. Therefore, when we start optionally using GlobalISel library for say AArch64, without that change, all the tools that use the AArch64 library would need to explicitly link with GlobalISel when we ask for it. This does not scale. Instead, we will set the dependencies between the target and GlobalISel and if we did not ask to build GlobalISel, the library will just be empty. Thanks to Chris Bieneman and Mehdi Animi for the idea. llvm-svn: 260566
* LiveIntervalAnalysis: Support moving of subregister defs in handleMoveMatthias Braun2016-02-111-34/+152
| | | | | | | | | | | | | | | | If two definitions write to independent subregisters then they can be put in any order. LiveIntervalAnalysis::handleMove() did not support this previously because it looks like moving a definition of a vreg past another one. This is a modified version of a patch proposed (two years ago) by Vincent Lejeune! This version does not touch the read-undef flags and is extended for the case of moving a subregister def behind all uses - this can happen for subregister defs that are completely unused. Differential Revision: http://reviews.llvm.org/D9067 llvm-svn: 260565
* [GlobalISel] Teach the IRTranslator how to lower returns.Quentin Colombet2016-02-112-6/+42
| | | | llvm-svn: 260562
* [AMDGPU] Fix for "v_div_scale_f64 reg, vcc, ..." parsingTom Stellard2016-02-113-10/+10
| | | | | | | | | | | | | | | | | | Summary: Added support for "VOP3Only" attribute in VOP3bInst encoding. Set VOP3Only=1 for V_DIV_SCALE_F64/32 insns. Added support for multi-dest instructions in AMDGPUAs::cvt*(). Added lit test for "V_DIV_SCALE_F64|F32 vreg,vcc|sreg,vreg,vreg,vreg". Reviewers: tstellarAMD, arsenm Subscribers: arsenm, SamWot, nhaustov, vpykhtin Differential Revision: http://reviews.llvm.org/D16995 Patch By: Artem Tamazov llvm-svn: 260560
* [GlobalISel] Add a type to MachineInstr.Quentin Colombet2016-02-111-5/+20
| | | | | | | | | | | | | | | | | | | | | | | | We actually need that information only for generic instructions, therefore it would be nice not to have to pay the extra memory consumption for all instructions. Especially because a typed non-generic instruction does not make sense. The question is then, is it possible to have that information in a union or something? My initial thought was that we could have a derived class GenericMachineInstr with additional information, but in practice it makes little to no sense since generic MachineInstrs are likely turned into non-generic ones by just switching the opcode. In other words, we don't want to go through the process of creating a new, non-generic MachineInstr, object each time we do this switch. The memory benefit probably is not worth the extra compile time. Another option would be to keep the type of the MachineInstr in a side table. This would induce an extra indirection though. Anyway, I will file a PR to discuss about it and remember we need to come back to it at some point. llvm-svn: 260558
* [NVPTX] emit .file directives for files referenced by subprograms.Artem Belevich2016-02-111-0/+1
| | | | | | | | .. so .loc directives referring to those files work correctly. Differential Revision: http://reviews.llvm.org/D17086 llvm-svn: 260557
* [GlobalISel] Add a hook in TargetConfigPass to run GlobalISel.Quentin Colombet2016-02-111-2/+14
| | | | llvm-svn: 260553
* [GlobalISel][IRTranslator] Change the ownership of the MIRBuilder field.Quentin Colombet2016-02-111-10/+8
| | | | llvm-svn: 260551
* [GlobalISel][IRTranslator] Fix a typo in assert.Quentin Colombet2016-02-111-1/+1
| | | | llvm-svn: 260550
* [GlobalISel][IRTranslator] Teach the pass how to translate Add instructions.Quentin Colombet2016-02-111-1/+44
| | | | llvm-svn: 260549
* [GlobalISel] Add a MachineIRBuilder class.Quentin Colombet2016-02-112-0/+62
| | | | | | | Helper class to build machine instrs. This is a higher abstraction than MachineInstrBuilder. llvm-svn: 260547
* [lanai] Add Lanai triple.Jacques Pienaar2016-02-111-0/+10
| | | | | | | | | | Add triple for the Lanai backend. General Lanai backend discussion on llvm-dev thread "[RFC] Lanai backend". Differential Revision: http://reviews.llvm.org/D17003 llvm-svn: 260545
* Fixed typo in r260530Jun Bum Lim2016-02-111-5/+5
| | | | llvm-svn: 260541
* Revert r260507: "[X86] Enable the LEA optimization pass by default."Hans Wennborg2016-02-111-5/+4
| | | | | | This caused PR26575. llvm-svn: 260538
* [AArch64] Refactoring findMatchingStore() in aarch64-ldst-opt; NFCJun Bum Lim2016-02-111-11/+13
| | | | | | | | | | | | Summary: This change makes findMatchingStore() follow the same coding style introduced in r260275. Reviewers: gberry, junbuml Subscribers: aemerson, rengolin, haicheng, bmakam, mssimpso Differential Revision: http://reviews.llvm.org/D17083 llvm-svn: 260534
* [InstCombine] Simplify a known nonzero incoming value of PHIJun Bum Lim2016-02-111-0/+36
| | | | | | | | | | | | | | | | | | | | Summary: When a PHI is used only to be compared with zero, it is possible to replace an incoming value with any non-zero constant if the incoming value can be proved as a known nonzero value. For example, in below code, we can replace the incoming value %v with any non-zero constant based on the fact that the PHI is only used to be compared with zero and %v is a known non-zero value: %v = select %cond, 1, 2 %p = phi [%v, BB] ... %c = icmp eq, %p, 0 Reviewers: mcrosier, jmolloy, sanjoy Subscribers: hfinkel, mcrosier, majnemer, llvm-commits, haicheng, bmakam, mssimpso, gberry Differential Revision: http://reviews.llvm.org/D16240 llvm-svn: 260530
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