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* Add the 'resume' instruction for the new EH rewrite.Bill Wendling2011-07-3117-8/+95
| | | | | | | | | This adds the 'resume' instruction class, IR parsing, and bitcode reading and writing. The 'resume' instruction resumes propagation of an existing (in-flight) exception whose unwinding was interrupted with a 'landingpad' instruction (to be added later). llvm-svn: 136589
* Do not handle cases with >= and <= predicates.Jakub Staszak2011-07-311-7/+0
| | | | llvm-svn: 136588
* Remove untrue comment.Jakub Staszak2011-07-311-3/+0
| | | | llvm-svn: 136587
* Do not handle case where LHS is equal to zero, because InstCombiner always movesJakub Staszak2011-07-311-24/+8
| | | | | | it to RHS anyway. llvm-svn: 136586
* Add a small gep optimization I noticed was missing while reading some IL.Rafael Espindola2011-07-311-11/+13
| | | | llvm-svn: 136585
* Time the emission of debug values.Jakob Stoklund Olesen2011-07-311-1/+4
| | | | llvm-svn: 136584
* Add Zero Heurestics to BranchProbabilityInfo. If we compare value to zero weJakub Staszak2011-07-311-1/+91
| | | | | | | | | | | | | decide whether condition is likely to be true this way: x == 0 -> false x < 0 -> false x <= 0 -> false x != 0 -> true x > 0 -> true x >= 0 -> true llvm-svn: 136583
* Revert r136528 "Enable compact region splitting by default."Jakob Stoklund Olesen2011-07-301-1/+1
| | | | | | | While this generally helped x86-64, there was some large regressions for i386. llvm-svn: 136571
* Switch another of the old dependencies on implicitly produced syntheticChandler Carruth2011-07-301-1/+1
| | | | | | | rules to the new explicitly listed TableGen rules. Somehow I missed this in my original sweep. llvm-svn: 136567
* Revert r136253, r136263, r136269, r136313, r136325, r136326, r136329, r136338,Bill Wendling2011-07-3022-672/+44
| | | | | | | r136339, r136341, r136369, r136387, r136392, r136396, r136429, r136430, r136444, r136445, r136446, r136253 pending review. llvm-svn: 136556
* Added several architecture names.Sean Callanan2011-07-301-1/+2
| | | | llvm-svn: 136552
* Revert "Don't check liveness of unallocatable registers."Jakob Stoklund Olesen2011-07-302-11/+4
| | | | | | | The ARM target depends on CPSR liveness being tracked after register allocation. llvm-svn: 136548
* Don't check liveness of unallocatable registers.Jakob Stoklund Olesen2011-07-292-4/+11
| | | | | | | | | | | | This includes registers like EFLAGS and ST0-ST7. We don't check for liveness issues in the verifier and scavenger because registers will never be allocated from these classes. While in SSA form, we do care about the liveness of unallocatable unreserved registers. Liveness of EFLAGS and ST0 neds to be correct for MachineDCE and MachineSinking. llvm-svn: 136541
* Check for multiple defs in the machine code verifier.Jakob Stoklund Olesen2011-07-291-0/+5
| | | | llvm-svn: 136535
* Add an isSSA() flag to MachineRegisterInfo.Jakob Stoklund Olesen2011-07-293-1/+8
| | | | | | | | | | | | | This flag is true from isel to register allocation when the machine function is required to be in SSA form. The TwoAddressInstructionPass and PHIElimination passes clear the flag. The SSA flag wil be used by the machine code verifier to check for SSA form, and eventually an assertion can enforce it in +Asserts builds. This will catch the common target error of creating machine code with multiple defs of a virtual register. llvm-svn: 136532
* Do not lose branch weights when lowering SwitchInst.Jakub Staszak2011-07-292-17/+52
| | | | llvm-svn: 136529
* Enable compact region splitting by default.Jakob Stoklund Olesen2011-07-291-1/+1
| | | | | | | This helps generate better code in functions with high register pressure. llvm-svn: 136528
* Add support for the 'Q' constraint.Eric Christopher2011-07-291-0/+3
| | | | | | Fixes rdar://9866494 llvm-svn: 136523
* have the verifier catch gep's into opaque struct types. PR10473Chris Lattner2011-07-291-0/+4
| | | | llvm-svn: 136510
* ARM SRS instruction parsing, diassembly and encoding support.Jim Grosbach2011-07-293-25/+52
| | | | | | | | Fix the instruction encoding for operands. Refactor mode to use explicit instruction definitions per FIXME to be more consistent with loads/stores. Fix disassembler accordingly. Add tests. llvm-svn: 136509
* On mac, it seems the MC disassembler is actually using the targetinfoChandler Carruth2011-07-291-0/+2
| | | | | | | | for targets that don't have an MC-ized disassembler. I'm suspicious that this shouldn't actually be happening, but hoping to fix the CMake build on macs first, and investigate why second. llvm-svn: 136508
* Remove unneeded const_cast.Jakub Staszak2011-07-291-2/+2
| | | | llvm-svn: 136506
* ARM CPS mode immediate is 5 bits, not 4.Jim Grosbach2011-07-291-2/+2
| | | | llvm-svn: 136505
* Clear DbgValues in the end.Devang Patel2011-07-291-0/+1
| | | | llvm-svn: 136503
* Add more constantness in BranchProbabilityInfo.Jakub Staszak2011-07-291-10/+11
| | | | llvm-svn: 136502
* Clean up debug info after reassociation.Devang Patel2011-07-291-1/+21
| | | | llvm-svn: 136480
* ARM assembly parsing and encoding for RFE instruction.Jim Grosbach2011-07-293-13/+54
| | | | | | | | | | | Fill in the missing fixed bits and the register operand bits of the instruction encoding. Refactor the definition to make the mode explicit, which is consistent with how loads and stores are normally represented and makes parsing much easier. Add parsing aliases for pseudo-instruction variants. Update the disassembler for the new representations. Add tests for parsing and encoding. llvm-svn: 136479
* Don't look at $PWD in GetCurrentDirectory.Nick Lewycky2011-07-291-3/+0
| | | | llvm-svn: 136477
* ARM SRS and RFE instructions are not code-gen only.Jim Grosbach2011-07-291-12/+7
| | | | llvm-svn: 136475
* ARM range checking for mode on CPS instruction.Jim Grosbach2011-07-291-2/+2
| | | | llvm-svn: 136473
* Update FIXME.Jim Grosbach2011-07-291-5/+2
| | | | llvm-svn: 136470
* Tweak comment.Jim Grosbach2011-07-291-1/+1
| | | | llvm-svn: 136468
* Teach Path::GetCurrentDirectory to use $PWD, to support users who like to doNick Lewycky2011-07-291-2/+5
| | | | | | | | | | | | screwy things by setting PWD != getcwd(). For example, some developers I know will use this to control the value in gcc's DW_AT_comp_dir value in debug output. With this patch, that trick will now work on clang too. The only other effect of this change is that the static analysis will now respect $PWD when reporting the directory of the files in its HTML output. I think that's fine. llvm-svn: 136459
* Fix a lot of typos, improve (but not necessarily fix) grammaros and reflow someNick Lewycky2011-07-292-24/+22
| | | | | | lines. No functionality change. llvm-svn: 136458
* Misc optimizer+codegen work for 'cmpxchg' and 'atomicrmw'. They appear to beEli Friedman2011-07-297-31/+182
| | | | | | | | | working on x86 (at least for trivial testcases); other architectures will need more work so that they actually emit the appropriate instructions for orderings stricter than 'monotonic'. (As far as I can tell, the ARM, PPC, Mips, and Alpha backends need such changes.) llvm-svn: 136457
* Remove incEdgeWeight and decEdgeWeight. Set edge weight directly to avoidJakub Staszak2011-07-291-30/+35
| | | | | | rounding errors. llvm-svn: 136456
* Fix the MCDisassembler dependencies. These were just absurdly wrong.Chandler Carruth2011-07-291-34/+7
| | | | | | | | | | | | First off, only depend on the actual MC-ized disassemblers in the targets, not all of the libraries those in turn depend on. Second off, only depend on those MC-ized disassemblers for targets we're building. This should fix builds of fewer than all targets. llvm-svn: 136455
* Fix two tests that I crashed in the previous commits. The mask eltsBruno Cardoso Lopes2011-07-291-5/+17
| | | | | | on the second half must be reindexed. llvm-svn: 136454
* Match VPERMIL masks more strictly and update the target specific maskBruno Cardoso Lopes2011-07-291-7/+17
| | | | | | generation to always catch the weird cases. llvm-svn: 136453
* Add DecodeShuffle shuffle support for VPERMIPD variantesBruno Cardoso Lopes2011-07-294-29/+60
| | | | llvm-svn: 136452
* Add v8i32 and v4i64 vpermil patternsBruno Cardoso Lopes2011-07-291-0/+4
| | | | llvm-svn: 136451
* Fix a bug while generating target specific VPERMIL masks: skipBruno Cardoso Lopes2011-07-291-4/+12
| | | | | | undef mask elements. This fixes PR10529. llvm-svn: 136450
* Enable usage of SSE4 extracts and inserts in their 128-bit AVX forms.Bruno Cardoso Lopes2011-07-291-39/+29
| | | | | | Also tidy up code a bit. llvm-svn: 136449
* Cleanup PALIGNR handling and remove the old palign pattern fragment.Bruno Cardoso Lopes2011-07-294-43/+23
| | | | | | | Also make PALIGNR masks to don't match 256-bits, which isn't supported It's also a step to solve PR10489 llvm-svn: 136448
* Use the pointer type size.Bill Wendling2011-07-291-1/+1
| | | | | | With this, we can now compile a simple EH program. llvm-svn: 136446
* And now something that compiles...Bill Wendling2011-07-291-1/+1
| | | | llvm-svn: 136445
* Make sure to sext or trunc the result from the register.Bill Wendling2011-07-291-2/+2
| | | | llvm-svn: 136444
* Transfer implicit operands in NEONMoveFixPass.Jakob Stoklund Olesen2011-07-291-10/+20
| | | | | | | | | Later passes /are/ using this information when running the register scavenger. This fixes the second problem in PR10520. llvm-svn: 136440
* Add -verify-arm-pseudo-expand.Jakob Stoklund Olesen2011-07-291-0/+7
| | | | | | | | | | This hidden llc option runs the machine code verifier after expanding ARM pseudo-instructions, but before if-conversion. The machine code verifier is much better at pointing out liveness errors that can trip up the register scavenger. llvm-svn: 136439
* Make sure to correctly clear the exact/nuw/nsw flags off of shifts when they ↵Eli Friedman2011-07-291-19/+27
| | | | | | are combined together. <rdar://problem/9859829> llvm-svn: 136435
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