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* LoopVectorize: Use IRBuilder interface in more placesArnold Schwaighofer2013-05-111-25/+13
| | | | | | No functionality change intended. llvm-svn: 181665
* StringRefize some debug accel table bits.Benjamin Kramer2013-05-113-7/+7
| | | | llvm-svn: 181663
* InstCombine: Turn urem to bitwise-and more oftenDavid Majnemer2013-05-111-20/+2
| | | | | | | Use isKnownToBeAPowerOfTwo in visitUrem so that we may more aggressively fold away urem instructions. llvm-svn: 181661
* Change getFrameMoves to return a const reference.Rafael Espindola2013-05-119-57/+46
| | | | | | | To add a frame now there is a dedicated addFrameMove which also takes care of constructing the move itself. llvm-svn: 181657
* Remove more dead code.Rafael Espindola2013-05-112-13/+0
| | | | llvm-svn: 181656
* Remove dead code.Rafael Espindola2013-05-102-82/+0
| | | | llvm-svn: 181649
* SLPVectorizer: Add support for trees with external users.Nadav Rotem2013-05-102-9/+55
| | | | | | | | | | | | | For example: bar() { int a = A[i]; int b = A[i+1]; B[i] = a; B[i+1] = b; foo(a); <--- a is used outside the vectorized expression. } llvm-svn: 181648
* Add a debug printNadav Rotem2013-05-101-0/+2
| | | | llvm-svn: 181647
* Checkin in of first of several patches to finish implementation ofReed Kotler2013-05-1012-16/+282
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). llvm-svn: 181641
* Micro-optimization: don't shift an entire bitcode record over to get the code.Jordan Rose2013-05-101-3/+10
| | | | | | | | | | | Previously, BitstreamCursor read an abbreviated record by splatting the whole thing into a data vector, then extracting and removing the /first/ element. Now, it reads the first element--the record code--separately from the actual field values. No (intended) functionality change. llvm-svn: 181639
* PR14492: Debug Info: Support for values of non-integer non-type template ↵David Blaikie2013-05-103-4/+24
| | | | | | | | | | parameters. This is only tested for global variables at the moment (& includes tests for the unnamed parameter case, since apparently this entire function was completely untested previously) llvm-svn: 181632
* Fix unused variable error.Jyotsna Verma2013-05-101-2/+1
| | | | | | | Earlier, this variable was used in an assert and was causing failure on darwin. llvm-svn: 181630
* Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore.Jyotsna Verma2013-05-104-707/+81
| | | | | | No functionality change. llvm-svn: 181628
* Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.Jyotsna Verma2013-05-108-703/+170
| | | | llvm-svn: 181624
* Fix the R600 build.Rafael Espindola2013-05-102-3/+2
| | | | llvm-svn: 181621
* [ms-inline asm] Fix a crasher when we fail on a direct match.Chad Rosier2013-05-102-6/+9
| | | | | | | | | | | | | | | | | | The issue was that the MatchingInlineAsm and VariantID args to the MatchInstructionImpl function weren't being set properly. Specifically, when parsing intel syntax, the parser thought it was parsing inline assembly in the at&t dialect; that will never be the case. The crash was caused when the emitter tried to emit the instruction, but the operands weren't set. When parsing inline assembly we only set the opcode, not the operands, which is used to lookup the instruction descriptor. rdar://13854391 and PR15945 Also, this commit reverts r176036. Now that we're correctly parsing the intel syntax the pushad/popad don't match properly. I've reimplemented that fix using a MnemonicAlias. llvm-svn: 181620
* Remove unused argument.Rafael Espindola2013-05-1023-33/+27
| | | | llvm-svn: 181618
* Better output for long help strings for command-line options.Alexander Kornienko2013-05-101-8/+16
| | | | | | | | | | | | | | | | | | | | | Summary: This patch allows using \n inside long help strings for command-line options, so that all lines are equally indented. This is not a perfect solution, as we don't (and probably don't want to) know about terminal width, but it allows to format long help strings somehow readable without manually padding them with spaces. A motivating example is -help output from clang-format (source code in tools/clang-format/ClangFormat.cpp, see cl options offset, length, style, and dump-config). Reviewers: atrick, alexfh Reviewed By: alexfh CC: llvm-commits, rafael Differential Revision: http://llvm-reviews.chandlerc.com/D779 llvm-svn: 181608
* Remove unused function.Rafael Espindola2013-05-102-11/+0
| | | | llvm-svn: 181606
* InstCombine: Don't claim to be able to evaluate any shl in a zexted type.Benjamin Kramer2013-05-101-1/+11
| | | | | | | | | | The shift amount may be larger than the type leading to undefined behavior. Limit the transform to constant shift amounts. While there update the bits to clear in the result which may enable additional optimizations. PR15959. llvm-svn: 181604
* Implement AsmParser for ARM unwind directives.Logan Chien2013-05-102-27/+284
| | | | | | | | | | | | | | | | | | | This commit implements the AsmParser for fnstart, fnend, cantunwind, personality, handlerdata, pad, setfp, save, and vsave directives. This commit fixes some minor issue in the ARMELFStreamer: * The switch back to corresponding section after the .fnend directive. * Emit the unwind opcode while processing .fnend directive if there is no .handlerdata directive. * Emit the unwind opcode to .ARM.extab while processing .handlerdata even if .personality directive does not exist. llvm-svn: 181603
* DAGCombiner: Generate a correct constant for vector types when folding (xor ↵Benjamin Kramer2013-05-101-2/+1
| | | | | | | | (and)) into (and (not)). PR15948. llvm-svn: 181597
* InstCombine: Verify the type before transforming uitofp into select.Benjamin Kramer2013-05-101-22/+23
| | | | | | PR15952. llvm-svn: 181586
* R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen ↵Tom Stellard2013-05-105-1217/+12
| | | | | | | | | | | | | | patterns The BFE optimization was the only one we were actually using, and it was emitting an intrinsic that we don't support. https://bugs.freedesktop.org/show_bug.cgi?id=64201 Reviewed-by: Christian König <christian.koenig@amd.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181580
* R600: Expand SUB for v2i32/v4i32Tom Stellard2013-05-101-0/+2
| | | | | | | | | | Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181579
* R600: Expand MUL for v4i32/v2i32Tom Stellard2013-05-101-0/+2
| | | | | | | | | | | | Fixes piglit test for OpenCL builtin mul24, and allows mad24 to run. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181578
* R600: Expand SRA for v4i32/v2i32Tom Stellard2013-05-101-0/+2
| | | | | | | | | | | | v2: Add v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181577
* R600: Expand vselect for v4i32 and v2i32Tom Stellard2013-05-101-0/+3
| | | | | | | | | | | | v2: Add vselect v4i32 test Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181576
* [x86AsmParser] It's valid to stop parsing an operand at an immediate.Chad Rosier2013-05-091-1/+3
| | | | | | rdar://13854369 and PR15944 llvm-svn: 181564
* Teach SelectionDAG to constant fold all-constant FMA nodes the same way that ↵Owen Anderson2013-05-091-0/+15
| | | | | | it constant folds FADD, FMUL, etc. llvm-svn: 181555
* Fix a documentation warning: \bried -> \briefDmitri Gribenko2013-05-091-1/+1
| | | | llvm-svn: 181551
* Generate a compact unwind encoding in the face of a stack alignment push.Bill Wendling2013-05-091-0/+6
| | | | | | | | | | | | | We generate a `push' of a random register (%rax) if the stack needs to be aligned by the size of that register. However, this could mess up compact unwind generation. In particular, we want to still generate compact unwind in the presence of this monstrosity. Check if the push of of the %rax/%eax register. If it is and it's marked with the `FrameSetup' flag, then we can generate a compact unwind encoding for the function only if the push is the last FrameSetup instruction. llvm-svn: 181540
* Hexagon: Remove switch cases from GetDotNewPredOp and isPostIncrement functions.Jyotsna Verma2013-05-093-593/+46
| | | | | | No functionality change. llvm-svn: 181535
* [GVN] Split critical-edge on the fly, instead of postpone edge-splitting to nextShuxin Yang2013-05-091-13/+39
| | | | | | | | | | iteration. This on step toward non-iterative GVN. My local hack suggests that getting rid of iteration will speedup GVN by 30%+ on a medium sized input (2k LOC, C++). I cannot explain why not 2x or more at this moment. llvm-svn: 181532
* Hexagon: Use relation map for getMatchingCondBranchOpcode() and Jyotsna Verma2013-05-091-535/+5
| | | | | | getInvertedPredicatedOpcode() functions instead of switch cases. llvm-svn: 181530
* Simplify the code a bit.Bill Wendling2013-05-091-19/+10
| | | | | | | | | | The compact unwind registers were defined in two different places. It's better just to place them in the function that uses them and specify that this is a 64-bit or 32-bit machine. No functionality change. llvm-svn: 181529
* Don't replace an alias in llvm.used with its target.Rafael Espindola2013-05-091-2/+102
| | | | | | | When we replace an internal alias with its target, be careful not to replace the entry in llvm.used (and llvm.compiler_used). llvm-svn: 181524
* [XCore] Fix handling of functions where only the LR is spilled.Richard Osborne2013-05-091-27/+30
| | | | | | | | | | | | | | Previously we only checked if the LR required saving if the frame size was non zero. However because the caller reserves 1 word for the callee to use that doesn't count towards our frame size it is possible for the LR to need saving and for the frame size to be 0. We didn't hit when the LR needed saving because of a function calls because the 1 word of stack we must allocate for our callee means the frame size is always non zero in this case. However we can hit this case if the LR is clobbered in inline asm. llvm-svn: 181520
* InstCombine: Don't just copy known bits from the first operand of an srem.Benjamin Kramer2013-05-091-1/+1
| | | | | | | That's obviously wrong. Conservatively restrict it to the sign bit, which matches the original intention of this analysis. Fixes PR15940. llvm-svn: 181518
* libDebugInfo depends on libObject nowadays.Benjamin Kramer2013-05-091-1/+1
| | | | llvm-svn: 181510
* Change getRelocationAdditionalInfo to be ELF only.Rafael Espindola2013-05-093-15/+4
| | | | | | | It was only implemented for ELF where it collected the Addend, so this patch also renames it to getRelocationAddend. llvm-svn: 181502
* Revert "Make sure debug info contains linkage names (DW_AT_MIPS_linkage_name)"Eric Christopher2013-05-091-15/+11
| | | | | | | | temporarily while investigating gdb.cp/templates.exp. This reverts commit r181471. llvm-svn: 181496
* LoopVectorizer: Don't assert on the absence of induction variablesArnold Schwaighofer2013-05-091-1/+2
| | | | | | | | | A computable loop exit count does not imply the presence of an induction variable. Scalar evolution can return a value for an infinite loop. Fixes PR15926. llvm-svn: 181495
* Make sure debug info contains linkage names (DW_AT_MIPS_linkage_name)Eric Christopher2013-05-081-11/+15
| | | | | | | | | for constructors and destructors since the original declaration given by the AT_specification both won't and can't. Patch by Yacine Belkadi, I've cleaned up the testcases. llvm-svn: 181471
* Add DebugIR pass -- emits IR file and replace source lines with IR lines in MDDaniel Malea2013-05-083-0/+254
| | | | | | | | | | | - requires existing debug information to be present - fixes up file name and line number information in metadata - emits a "<orig_filename>-debug.ll" succinct IR file (without !dbg metadata or debug intrinsics) that can be read by a debugger - initialize pass in opt tool to enable the "-debug-ir" flag - lit tests to follow llvm-svn: 181467
* Pull up AssemblyWriter interface into header to allow subclassingDaniel Malea2013-05-081-84/+42
| | | | | | | | | | | - made all functions virtual so that subclasses can specialize them - add printInstructionLine so that subclasses can choose whether or not to print the newline character (without having to implement printBasicBlock() - added a second constructor to AssemblyWriter that does not require a SlotTracker, as required in order to keep the SlotTracker helper class outside AsmWriter.h and buried in the implementation. llvm-svn: 181466
* Add line tracking support to FormattedStream Daniel Malea2013-05-081-20/+25
| | | | | | | | - previously formatted_raw_ostream tracked columns, now it tracks lines too - used by (upcoming) DebugIR pass to know the line number to connect to each IR instruction llvm-svn: 181463
* [mips] Add instruction selection pattern for (seteq $LHS, 0).Akira Hatanaka2013-05-081-0/+2
| | | | llvm-svn: 181459
* Remove unused isLegalAddressImmediate() method.Roman Divacky2013-05-082-21/+0
| | | | llvm-svn: 181452
* [PowerPC] Fix regression in generating @ha/@l relocsUlrich Weigand2013-05-081-1/+10
| | | | | | | | | | | | | | | | The patch I committed as revision 167864 introduced a regression that causes LLVM to no longer generate appropriate relocs for @ha/@l symbol references (but fail an assertion instead). This is fixed here by re-enabling support for the VK_PPC_GAS_HA16/ VK_PPC_GAS_LO16 variant kinds (and their Darwin variants) in PPCELFObjectWriter.cpp. Tested by running projects/test-suite in -m32 mode with the integrated assembler forced on. A standalone test case will be committed shortly as well. llvm-svn: 181450
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