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* [ThinLTO] Use NoPromote flag in summary during promotionTeresa Johnson2016-10-291-13/+19
| | | | | | | | | | | | | | | | Summary: Replace the check of whether a GV has a section with the flag check in the summary. This is in preparation for using the NoPromote flag to convey other situations when we can't promote (e.g. locals used in inline asm). Reviewers: mehdi_amini Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26063 llvm-svn: 285507
* IR: Remove a no longer needed assert.Peter Collingbourne2016-10-291-5/+0
| | | | | | | This assert was checking for a miscompile in a version of GCC that we no longer support. llvm-svn: 285506
* [X86] Use intrinsics table for VPMULHRSW intrincis so that the legacy ↵Craig Topper2016-10-293-12/+13
| | | | | | | | intrinsics can select EVEX encoded instructions when available. This requires a minor rename of the instructions due to the use of different tablegen classes and how the names are concatenated. llvm-svn: 285501
* [ValueTracking] recognize more variants of smin/smaxSanjay Patel2016-10-291-10/+18
| | | | | | | | | | | | | Try harder to detect obfuscated min/max patterns: the initial pattern was added with D9352 / rL236202. There was a bug fix for PR27137 at rL264996, but I think we can do better by folding the corresponding smax pattern and commuted variants. The codegen tests demonstrate the effect of ValueTracking on the backend via SelectionDAGBuilder. We can't expose these differences minimally in IR because we don't have smin/smax intrinsics for IR. Differential Revision: https://reviews.llvm.org/D26091 llvm-svn: 285499
* [InstCombine] re-use bitcasted compare operands in selects (PR28001)Sanjay Patel2016-10-291-0/+50
| | | | | | | | | | | These mixed bitcast patterns show up with SSE/AVX intrinsics because we bitcast function parameters to <2 x i64>. The bitcasts obfuscate the expected min/max forms as shown in PR28001: https://llvm.org/bugs/show_bug.cgi?id=28001#c6 Differential Revision: https://reviews.llvm.org/D25943 llvm-svn: 285495
* [DAGCombiner] (REAPPLIED) Add vector demanded elements support to ↵Simon Pilgrim2016-10-291-13/+111
| | | | | | | | | | | | | | | | | | | | computeKnownBits Currently computeKnownBits returns the common known zero/one bits for all elements of vector data, when we may only be interested in one/some of the elements. This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original computeKnownBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1. The approach was found to be easier than trying to add a per-element known bits solution, for a similar usefulness given the combines where computeKnownBits is typically used. I've only added support for a few opcodes so far (the ones that have proven straightforward to test), all others will default to demanding all elements but can be updated in due course. DemandedElts support could similarly be added to computeKnownBitsForTargetNode in a future commit. This looked like this had caused compile time regressions on some buildbots (and was reverted in rL285381), but appears to have just been a harmless bystander! Differential Revision: https://reviews.llvm.org/D25691 llvm-svn: 285494
* Fixed FMA + FNEG combine.Elena Demikhovsky2016-10-291-3/+13
| | | | | | | | Masked form of FMA should be omitted in this optimization. Differential Revision: https://reviews.llvm.org/D25984 llvm-svn: 285492
* AMDGPU: Use 1/2pi inline imm on VIMatt Arsenault2016-10-297-14/+43
| | | | | | I'm guessing at how it is supposed to be printed llvm-svn: 285490
* AArch64DeadRegisterDefinitionsPass: Cleanup; NFCMatthias Braun2016-10-291-54/+53
| | | | | | | | | | | - Fix doxygen file comment - reduce indentation in loop - Factor out some common subexpressions - Move independent helper function out of class - Fix Changed flag (this is not strictly NFC but a bugfix, but the flag seems ignored anyway) llvm-svn: 285488
* Define calculateDbgStreamSize for consistency.Rui Ueyama2016-10-291-1/+5
| | | | llvm-svn: 285487
* [APFloat] Remove the redundent function body of uninitialized ctor, which ↵Tim Shen2016-10-291-4/+1
| | | | | | should be done in r285468 llvm-svn: 285486
* Resubmit "Add support for advanced number formatting."Zachary Turner2016-10-292-93/+171
| | | | | | | | | | | | | This resubmits r284436 and r284437, which were reverted in r284462 as they were breaking the AArch64 buildbot. The breakage on AArch64 turned out to be a miscompile which is still not fixed, but is actively tracked at llvm.org/pr30748. This resubmission re-writes the code in a way so as to make the miscompile not happen. llvm-svn: 285483
* [DAGCombiner] Fix a crash visiting `AND` nodes.Davide Italiano2016-10-281-1/+6
| | | | | | | | | | Instead of asserting that the shift count is != 0 we just bail out as it's not profitable trying to optimize a node which will be removed anyway. Differential Revision: https://reviews.llvm.org/D26098 llvm-svn: 285480
* AMDGPU/SI: Don't use non-0 waitcnt values when waiting on Flat instructionsTom Stellard2016-10-283-2/+27
| | | | | | | | | | | | | | Summary: Flat instruction can return out of order, so we need always need to wait for all the outstanding flat operations. Reviewers: tony-tye, arsenm Subscribers: kzhuravl, wdng, nhaehnle, llvm-commits, yaxunl Differential Revision: https://reviews.llvm.org/D25998 llvm-svn: 285479
* AMDGPU: Fix instruction flags for s_endpgmMatt Arsenault2016-10-281-2/+1
| | | | | | | Set isReturn, remove hasSideEffects. Also remove hasCtrlDep, I'm not really sure what that does. llvm-svn: 285476
* Refactor DW_LNE_* into Dwarf.defAdrian Prantl2016-10-281-8/+6
| | | | llvm-svn: 285475
* Refactor DW_LNS_* into Dwarf.defAdrian Prantl2016-10-281-13/+6
| | | | llvm-svn: 285474
* Refactor DW_APPLE_PROPERTY_* into Dwarf.defAdrian Prantl2016-10-281-31/+6
| | | | llvm-svn: 285473
* Refactor DW_CFA_* into Dwarf.defAdrian Prantl2016-10-281-32/+6
| | | | llvm-svn: 285472
* Refactor all DW_FORM_* constants into Dwarf.defAdrian Prantl2016-10-281-34/+6
| | | | llvm-svn: 285470
* [APFloat] Fix memory bugs revealed by MSanTim Shen2016-10-281-3/+8
| | | | | | | | | | Reviewers: eugenis, hfinkel, kbarton, iteratee, echristo Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D26102 llvm-svn: 285468
* SDAG: Make sure we use an allocatable reg class when we create this vregJustin Bogner2016-10-281-0/+2
| | | | | | | As per the discussion on r280783, if constrainRegClass fails we need to call getAllocatableClass like we did before that commit. llvm-svn: 285467
* AMDGPU: Add definitions for scalar store instructionsMatt Arsenault2016-10-287-23/+147
| | | | | | | | | | Also add glc bit to the scalar loads since they exist on VI and change the caching behavior. This currently has an assembler bug where the glc bit is incorrectly accepted on SI/CI which do not have it. llvm-svn: 285463
* AMDGPU: Rename glc operand typeMatt Arsenault2016-10-284-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | While trying to add the glc bit to SMEM instructions on VI with the new refactoring I ran into some kind of shadowing problem for the glc operand when using the pseudoinstruction as a multiclass parameter. Everywhere that currently uses it defines the operand to have the same name as its type, i.e. glc:$glc which works. For some reason now it conflicts, and its up evaluating to the wrong thing. For the real encoding classes, let Inst{16} = !if(ps.has_glc, glc, ?); was not being evaluated and still visible in the Inst initializer in the expanded td file. In other cases I got a a different error about an illegal operand where this was using { 0 } initializer from the bits<1> glc initializer instead of evaluating it as false in the if. For consistency all of the operand types should probably be captialized to avoid conflicting with the variable names unless somebody has a better idea of how to fix this. llvm-svn: 285462
* [NVPTX] Compute 'rem' using the result of 'div', if possible.Justin Lebar2016-10-281-0/+36
| | | | | | | | | | | | | | | | | | | | | Summary: In isel, transform Num % Den into Num - (Num / Den) * Den if the result of Num / Den is already available. Reviewers: tra Subscribers: hfinkel, llvm-commits, jholewinski Differential Revision: https://reviews.llvm.org/D26090 llvm-svn: 285461
* Don't leave unused divs/rems sitting around in BypassSlowDivision.Justin Lebar2016-10-281-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This "pass" eagerly creates div and rem instructions even when only one is needed -- it relies on a later pass (machine DCE?) to clean them up. This is problematic not just from a cleanliness perspective (this pass is running during CodeGenPrepare, so should leave the IR in a better state), but it also creates a problem for instruction selection. If we always have a div+rem, isel will always select a divrem instruction (if possible), even when a single div or rem would do. Specifically, in NVPTX, we want to compute rem from the output of div, if available. But if a div is not available, we want to leave the rem alone. This transformation is overeager if div is always available. Because this code runs as part of CodeGenPrepare, it's nontrivial to write a test for this change. But this will effectively be tested by a later patch which adds the aforementioned change to NVPTX isel. Reviewers: tra Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26088 llvm-svn: 285460
* Don't claim the udiv created in BypassSlowDivision is exact.Justin Lebar2016-10-281-2/+1
| | | | | | | | | | | | | | | | | | | Summary: In BypassSlowDivision's short-dividend path, we would create e.g. udiv exact i32 %a, %b "exact" here means that we are asserting that %a is a multiple of %b. But we have no reason to believe this must be true -- this is just a bug, as far as I can tell. Reviewers: tra Subscribers: jholewinski, llvm-commits Differential Revision: https://reviews.llvm.org/D26097 llvm-svn: 285459
* AMDGPU: Diagnose using too many SGPRsMatt Arsenault2016-10-283-8/+27
| | | | | | This is possible when using inline asm. llvm-svn: 285447
* Handle non-~0 lane masks on live-in registers in LivePhysRegsKrzysztof Parzyszek2016-10-281-2/+3
| | | | | | | | | | | | | | | | | When LivePhysRegs adds live-in registers, it recognizes ~0 as a special lane mask indicating the entire register. If the lane mask is not ~0, it will only add the subregisters that overlap the specified lane mask. The problem is that if a live-in register does not have subregisters, and the lane mask is not ~0, it will not be added to the live set. (The given lane mask may simply be the lane mask of its register class.) If a register does not have subregisters, add it to the live set if the lane mask is non-zero. Differential Revision: https://reviews.llvm.org/D26094 llvm-svn: 285440
* SpeculativeExecution: Allow speculating more inst typesMatt Arsenault2016-10-281-0/+18
| | | | | | | Partial step towards removing the whitelist and only using TTI's cost. llvm-svn: 285438
* AMDGPU: Fix using incorrect private resource with no allocationMatt Arsenault2016-10-283-48/+97
| | | | | | | | | | | It's possible to have a use of the private resource descriptor or scratch wave offset registers even though there are no allocated stack objects. This would result in continuing to use the maximum number reserved registers. This could go over the number of SGPRs available on VI, or violate the SGPR limit requested by the function attributes. llvm-svn: 285435
* Implement vector count leading/trailing bytes with zero lsb and vector parityNemanja Ivanovic2016-10-281-7/+14
| | | | | | | | | builtins - llvm portion This patch corresponds to review https://reviews.llvm.org/D26003. Committing on behalf of Zaara Syeda. llvm-svn: 285434
* [ThinLTO] Use flags from summary when writing variable summary (NFC)Teresa Johnson2016-10-281-1/+1
| | | | | | | | | | | | We already read the flags out of the summary when writing the summary records for functions and aliases, do the same for variables. This is an NFC change for now since the flags computed on the fly from the GlobalValue currently will always match those in the summary already, but once I send a follow-on patch to set the NoRename flag for locals in the llvm.used set this becomes a necessary change. llvm-svn: 285433
* [MemorySSA] Add const to getClobberingMemoryAccess.George Burgess IV2016-10-281-3/+3
| | | | | | | | Thanks to bryant for the patch! Differential Revision: https://reviews.llvm.org/D26086 llvm-svn: 285432
* Move the DWARF attribute constants into Dwarf.def and delete 300 lines of ↵Adrian Prantl2016-10-281-195/+6
| | | | | | silly code. llvm-svn: 285425
* MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFCMatthias Braun2016-10-286-7/+6
| | | | llvm-svn: 285423
* TargetPassConfig: Move addPass of IPRA RegUsageInfoProp down.Matthias Braun2016-10-281-3/+3
| | | | | | | | | TargetPassConfig::addMachinePasses() does some housekeeping first: Handling the -print-machineinstrs flag and doing an initial printing "After Instruction Selection". There is no reason for RegUsageInfoProp to run before those two steps. llvm-svn: 285422
* Import/update constants from the DWARF 5 public review draft document.Adrian Prantl2016-10-285-9/+26
| | | | | | https://reviews.llvm.org/D26051 llvm-svn: 285421
* [Hexagon] Maintain kill flags through splitting in expand-condsetsKrzysztof Parzyszek2016-10-281-40/+96
| | | | | | | Do not use LiveIntervals to recalculate kills, because that cannot be done accurately without implicit uses on predicated instructions. llvm-svn: 285409
* [Loads] Fix crash in is isDereferenceableAndAlignedPointer()Tom Stellard2016-10-281-2/+5
| | | | | | | | | | | | | | | Summary: We were trying to add APInt values with different bit sizes after visiting an addrspacecast instruction which changed the bit width of the pointer. Reviewers: majnemer, hfinkel Subscribers: hfinkel, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D24774 llvm-svn: 285407
* [SelectionDAG] computeKnownBits - early-out if any BUILD_VECTOR element has ↵Simon Pilgrim2016-10-281-0/+4
| | | | | | | | no known bits No need to check the remaining elements - no common known bits are available. llvm-svn: 285399
* [SelectionDAG] Tidyup UDIV computeKnownBits implementationSimon Pilgrim2016-10-281-2/+0
| | | | | | No need to clear KnownOne2/KnownZero2 bits as the next call to computeKnownBits will overwrite them anyway llvm-svn: 285398
* [SelectionDAG] Increment computeKnownBits recursion depth for ↵Simon Pilgrim2016-10-281-2/+2
| | | | | | SMIN/SMAX/UMIN/UMAX like all other ops llvm-svn: 285397
* [LCSSA] Perform LCSSA verification only for the current loop nest.Igor Laevsky2016-10-284-4/+45
| | | | | | | | | Now LPPassManager will run LCSSA verification only for the top-level loop which was processed on the current iteration. Differential Revision: https://reviews.llvm.org/D25873 llvm-svn: 285394
* Revert "[DAGCombiner] Add vector demanded elements support to computeKnownBits"Juergen Ributzka2016-10-281-111/+13
| | | | | | | This seems to have increased LTO compile time bejond 2x of previous builds. See http://lab.llvm.org:8080/green/job/clang-stage2-configure-Rlto/10676/ llvm-svn: 285381
* [Reassociate] Removing instructions mutates the IR.Davide Italiano2016-10-281-1/+3
| | | | | | | | | Fixes PR 30784. Discussed with Justin, who pointed out that in the new PassManager infrastructure we can have more fine-grained control on which analyses we want to preserve, but this is the best we can do with the current infrastructure. llvm-svn: 285380
* [ThinLTO] Create AliasSummary when building indexTeresa Johnson2016-10-282-7/+27
| | | | | | | | | | | | | | | | | | | Summary: Previously we were creating the alias summary on the fly while writing the summary to bitcode. This moves the creation of these summaries to the module summary index builder where we build the rest of the summary index. This is going to be necessary for setting the NoRename flag for values possibly used in inline asm or module level asm. Reviewers: mehdi_amini Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26049 llvm-svn: 285379
* [ThinLTO] Rename HasSection to NoRename (NFC)Teresa Johnson2016-10-283-5/+6
| | | | | | | | | | | | | | Summary: This is in preparation for a change to utilize this flag for symbols referenced/defined in either inline or module level assembly. Reviewers: mehdi_amini Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26048 llvm-svn: 285376
* [IR] Clang-format my previous commit. NFCI.Davide Italiano2016-10-281-2/+2
| | | | llvm-svn: 285375
* [ConstantFold] Get the correct vector type when folding a getelementptr.Davide Italiano2016-10-281-6/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D26014 llvm-svn: 285371
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