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* Sparc: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-081-3/+3
| | | | | | | Remove the only implicit conversions from MachineInstrBundleIterator to MachineInstr* in the Sparc backend. llvm-svn: 274913
* WebAssembly: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-083-33/+30
| | | | | | | | Avoid implicit conversions from MachineInstrBundleIterator to MachineInstr* in the WebAssembly backend by preferring MachineInstr& over MachineInstr*. llvm-svn: 274912
* AsmPrinter: Avoid implicit iterator conversions in ↵Duncan P. N. Exon Smith2016-07-081-2/+2
| | | | | | DbgValueHistoryCalculator, NFC llvm-svn: 274911
* [CrossDSOCFI] Change the pass so that it doesn't require doInitialization()Davide Italiano2016-07-081-19/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D21357 llvm-svn: 274910
* [X86][AVX2] Add support for target shuffle combining to VPERMPD/VPERMQSimon Pilgrim2016-07-081-2/+19
| | | | llvm-svn: 274908
* SelectionDAG: Avoid implicit iterator conversions in SelectionDAGBuilder, NFCDuncan P. N. Exon Smith2016-07-081-1/+2
| | | | llvm-svn: 274907
* AMDGPU: Remove implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-089-172/+176
| | | | | | | | | | | Remove remaining implicit conversions from MachineInstrBundleIterator to MachineInstr* from the AMDGPU backend. In most cases, I made them less attractive by preferring MachineInstr& or using a ranged-based for loop. Once all the backends are fixed I'll make the operator explicit so that this doesn't bitrot back. llvm-svn: 274906
* [SCCP] Fold constants as we build them whne visiting cast instructions.Davide Italiano2016-07-081-2/+4
| | | | | | | | | This should be slightly more efficient and could avoid spurious overdefined markings, as Eli pointed out. Differential Revision: http://reviews.llvm.org/D22122 llvm-svn: 274905
* SelectionDAG: Avoid implicit iterator conversions in SelectionDAGISel, NFCDuncan P. N. Exon Smith2016-07-081-8/+8
| | | | llvm-svn: 274904
* SelectionDAG: Avoid implicit iterator conversions in ScheduleDAGSDNodes, NFCDuncan P. N. Exon Smith2016-07-081-1/+1
| | | | llvm-svn: 274903
* AMDGPU: Make infinite loop clear, NFCDuncan P. N. Exon Smith2016-07-081-1/+2
| | | | | | | | | | | | | | | Change a while loop that was checking for nullptr on an iterator-to-pointer conversion to an infinite for loop. Now it's clear that the condition doesn't terminate. The only change in behaviour is if an invalid iterator (holding nullptr) was passed into AMDGPUCFGStructurizer::reversePredicateSetter. There are only two callers, and they both dereference the iterator before sending it in, so rather than adding an early return to avoid the loop I've just asserted (using a static_cast, to avoid an implicit conversion to pointer). llvm-svn: 274902
* SelectionDAG: Avoid implicit iterator conversions in FastISel, NFCDuncan P. N. Exon Smith2016-07-081-3/+4
| | | | llvm-svn: 274899
* Target: Avoid getFirstTerminator() => pointer, NFCDuncan P. N. Exon Smith2016-07-083-10/+10
| | | | | | | | | | | | | | Stop using an implicit conversion from the return of MachineBasicBlock::getFirstTerminator to MachineInstr*. In two cases, directly dereference to a MachineInstr& since later code assumes it's valid. In a third case, change to an iterator since later code checks against MachineBasicBlock::end. Although the fix for the third case avoids undefined behaviour, I expect this doesn't cause a functionality change in practice (since the basic block already has a terminator). llvm-svn: 274898
* CodeGen: Avoid iterator conversions in TwoAddressInstructionPass, NFCDuncan P. N. Exon Smith2016-07-081-55/+51
| | | | | | | | | | | | Mostly through preferring MachineInstr&, avoid implicit conversions from iterator to pointer. Although this may bitrot (since there are other uses blocking me from removing the implicit operator), this removes the last of the implicit conversions from MachineInstrBundleIterator to MachineInstr* in the LLVMCodeGen build target. llvm-svn: 274893
* CodeGen: Use MachineInstr& in StackSlotColoring, NFCDuncan P. N. Exon Smith2016-07-081-14/+11
| | | | | | Avoid implicit iterator to pointer conversions. llvm-svn: 274892
* [InstCombine] check for one-use before turning simple logic op into a selectSanjay Patel2016-07-081-2/+2
| | | | llvm-svn: 274891
* IR: Set a TargetPrefix for nvvm intrinsicsJustin Bogner2016-07-081-2/+3
| | | | | | | | | Since these are named nvvm_* rather than nvptx_*, we also need to update getArchTypePrefix. It's a bit unusual for getArchTypePrefix not to match the backend name, but I think this fits the intent of the function in this case. llvm-svn: 274890
* CodeGen: Use MachineInstr& in RegisterScavenging, NFCDuncan P. N. Exon Smith2016-07-081-16/+15
| | | | | | | Prefer MachineInstr& in order to avoid implicit conversions from MachineInstrBundleIterator to MachineInstr*. llvm-svn: 274888
* AMDGPU: Minor adjustment to r274817Matt Arsenault2016-07-081-1/+1
| | | | | | | | | | The commit message is inaccurate, modifiesRegister will check for partial defs of exec. We currently don't ever emit partial defs of exec, so it doesn't really matter. llvm-svn: 274886
* [InstCombine] allow or(sext(A), B) --> A ? -1 : B transform for vectorsSanjay Patel2016-07-081-4/+5
| | | | llvm-svn: 274883
* [SystemZ] Add support for the .word directive.Zhan Jun Liau2016-07-081-0/+3
| | | | | | | | | | | | | Summary: Branch off the work to add support for the .word directive, using addAliasForDirective. Reviewers: koriakin Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D22142 llvm-svn: 274878
* [DSE] Minor refactor based on D21007. NFC.Chad Rosier2016-07-081-39/+50
| | | | llvm-svn: 274877
* [CodeGen, TargetPassConfig] Remove a race from createRegAllocPassDavid Majnemer2016-07-081-6/+14
| | | | | | | | The createRegAllocPass reads and writes to a global variable 'Registry' via calls to getDefault and setDefault. Run this under a call_once to avoid races. llvm-svn: 274875
* PeepholeOptimizer: Make pass name match DEBUG_TYPEMatt Arsenault2016-07-081-2/+2
| | | | llvm-svn: 274874
* [SystemZ] Add support for missing instructionsZhan Jun Liau2016-07-082-4/+93
| | | | | | | | | | | | | | | | | Summary: Add support to allow clang integrated assembler to recognize some missing instructions, for openssl. Instructions are: LM, LMH, LMY, STM, STMH, STMY, ICM, ICMH, ICMY, SLA, SLAK, TML, TMH, EX, EXRL. Reviewers: uweigand Subscribers: koriakin, llvm-commits Differential Revision: http://reviews.llvm.org/D22050 llvm-svn: 274869
* Move setName after accessing NameEric Liu2016-07-081-5/+2
| | | | llvm-svn: 274862
* Make a std::string copy of StringRef Name so that it remains valid when the ↵Eric Liu2016-07-081-1/+4
| | | | | | | | | | | | | | original Name is overridden. Summary: lib/IR/AutoUpgrade.cpp:348 and lib/IR/AutoUpgrade.cpp:350 upset sanitizer. Reviewers: bkramer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D22140 llvm-svn: 274861
* [Sparc] Leon errata fix passes.Chris Dewhurst2016-07-088-173/+869
| | | | | | | | | | | | Errata fixes for various errata in different versions of the Leon variants of the Sparc 32 bit processor. The nature of the errata are listed in the comments preceding the errata fix passes. Relevant unit tests are implemented for each of these. Note: Running clang-format has changed a few other lines too, unrelated to the implemented errata fixes. These have been left in as this keeps the code formatting consistent. Differential Revision: http://reviews.llvm.org/D21960 llvm-svn: 274856
* Do not expand SDIV when compiling for minimum code sizeSjoerd Meijer2016-07-081-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D22139 llvm-svn: 274855
* InstCombine rule to fold truncs whose value is availableAnna Thomas2016-07-082-17/+50
| | | | | | | | | | | | | We can fold truncs whose operand feeds from a load, if the trunc value is available through a prior load/store. This change is from: http://reviews.llvm.org/D21246, which folded the trunc but missed the bitcast or ptrtoint/inttoptr required in the RAUW call, when the load type didnt match the prior load/store type. Differential Revision: http://reviews.llvm.org/D21791 llvm-svn: 274853
* [AMDGPU] fix ds_swizzle_b32 opcode for VI (bz 28371)Valery Pykhtin2016-07-082-1/+21
| | | | | | Differential Revision: http://reviews.llvm.org/D22049 llvm-svn: 274852
* Addressing post-commit comments regarding not expanding UDIV;Sjoerd Meijer2016-07-081-2/+2
| | | | | | we don't expand only when compiling for minimum code size. llvm-svn: 274847
* Code size optimisation: don't expand a div to a mul and and a shift sequence.Sjoerd Meijer2016-07-081-0/+5
| | | | | | | | | As a result, the urem instruction will not be expanded to a sequence of umull, lsrs, muls and sub instructions, but just a call to __aeabi_uidivmod. Differential Revision: http://reviews.llvm.org/D22131 llvm-svn: 274843
* [AArch64] Macro fusion of simple ALU ops with branches for Broadcom's VulcanPankaj Gode2016-07-081-0/+1
| | | | | | | | | | Support for the macro fusion of simple ALU ops with branches for the Vulcan sub-target. Patch by Meador Inge <meadori@gmail.com> Differential Revision: http://reviews.llvm.org/D22042 llvm-svn: 274837
* [X86][SSE] Accept any shuffle mask that is all zeroesSimon Pilgrim2016-07-081-0/+7
| | | | | | Until we have a better way to extract constants through bitcasted build vectors (and how to handle undefs of partial lanes etc.) at least accept build vectors that are all zeroes. llvm-svn: 274833
* Bug 28444: Fix assertion when extract_vector_elt has mismatched typeMatt Arsenault2016-07-081-1/+1
| | | | | | | For some reason extract_vector_elt is sometimes allowed to have a different result type than the vector element type. llvm-svn: 274829
* [AVX512] Remove and autoupgrade a duplicate set of 512-bit masked shift ↵Craig Topper2016-07-083-15/+25
| | | | | | | | intrinsics. I'm not sure if clang ever used these builtin names or not. llvm-svn: 274827
* [PM] Port UnreachableBlockElim to the new Pass ManagerWei Mi2016-07-084-25/+41
| | | | | | Differential Revision: http://reviews.llvm.org/D22124 llvm-svn: 274824
* Add an assertion for the value enumerator (bitcode writer) NFCMehdi Amini2016-07-081-1/+6
| | | | | | | | I have an LTO snapshot (for which I don't have sources) that can't be read back by LLVM. It seems the writer emitted broken bitcode and this assertions aims at catching such cases. llvm-svn: 274819
* AMDGPU: Move si_mask_branch register operand to be a useMatt Arsenault2016-07-083-6/+8
| | | | llvm-svn: 274818
* AMDGPU: Cleanup. Use definesRegister instead of manual loopMatt Arsenault2016-07-081-6/+2
| | | | | | | Also this will be more precise since it will check exec_lo/exec_hi writes. llvm-svn: 274817
* ARM: support high registers in __builtin_longjmp on WoASaleem Abdulrasool2016-07-082-4/+34
| | | | | | | | | | Windows on ARM uses a pure thumb-2 environment. This means that it can select a high register when doing a __builtin_longjmp. We would use a tLDRi which would truncate the register to a low register. Use a t2LDRi12 to get the full register file access. Tweak the code to just load into PC, as that is an interworking branch on all supported cores anyways. llvm-svn: 274815
* [lanai] Use peephole optimizer to generate more conditional ALU operations.Jacques Pienaar2016-07-0715-364/+707
| | | | | | | | | | | | | | | | | Summary: * Similiar to the ARM backend yse the peephole optimizer to generate more conditional ALU operations; * Add predicated type with default always true to RR instructions in LanaiInstrInfo.td; * Move LanaiSetflagAluCombiner into optimizeCompare; * The ASM parser can currently only handle explicitly specified CC, so specify ".t" (true) where needed in the ASM test; * Remove unused MachineOperand flags; Reviewers: eliben Subscribers: aemerson Differential Revision: http://reviews.llvm.org/D22072 llvm-svn: 274807
* Recommit r274692 - [X86] Transform setcc + movzbl into xorl + setccMichael Kuperstein2016-07-074-1/+192
| | | | | | | | | | | xorl + setcc is generally the preferred sequence due to the partial register stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller. This fixes PR28146. The original commit tried inserting an 8bit-subreg into a GR32 (not GR32_ABCD) which was not appreciated by fast regalloc on 32-bit. llvm-svn: 274802
* [tsan] Try harder to not instrument gcov countersVedant Kumar2016-07-071-2/+2
| | | | | | | | GCOVProfiler::emitProfileArcs() can create many variables with names starting with "__llvm_gcov_ctr", so llvm appends a numeric suffix to most of them. Teach tsan about this. llvm-svn: 274801
* Add checks to the MachOObjectFile() constructor to make sure load commands sizesKevin Enderby2016-07-071-0/+19
| | | | | | are the correct multiple. llvm-svn: 274798
* [PM] Port InstSimplify to the new pass manager.Davide Italiano2016-07-073-44/+64
| | | | llvm-svn: 274796
* [DSE] Remove dead stores in end blocks containing fenceAnna Thomas2016-07-071-0/+8
| | | | | | | | | | We can remove dead stores in the presence of fence instructions. Fence does not change an otherwise thread local store to visible. reviewers: reames, dexonsmith, jfb Differential Revision: http://reviews.llvm.org/D22001 llvm-svn: 274795
* Add a missing semicolon.Rui Ueyama2016-07-071-1/+1
| | | | llvm-svn: 274794
* Clang-format LoadStoreVectorizerAlina Sbirlea2016-07-071-35/+33
| | | | | | | | | | Reviewers: llvm-commits, jlebar, arsenm Subscribers: mzolotukhin Differential Revision: http://reviews.llvm.org/D22107 llvm-svn: 274792
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