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* [LoopVectorize] Keep hints from original loop on the vector loopHal Finkel2016-04-291-0/+5
| | | | | | | | | | | | | | | | We need to keep loop hints from the original loop on the new vector loop. Failure to do this meant that, for example: void foo(int *b) { #pragma clang loop unroll(disable) for (int i = 0; i < 16; ++i) b[i] = 1; } this loop would be unrolled. Why? Because we'd vectorize it, thus dropping the hints that unrolling should be disabled, and then we'd unroll it. llvm-svn: 267970
* [msan] Handle vector compare x86 intrinsics.Evgeniy Stepanov2016-04-291-0/+69
| | | | | | This handles SSE and SSE2 cmp_* and comiXX_* intrinsics. llvm-svn: 267966
* [llvm-pdbdump] Try to appease the ASan botDavid Majnemer2016-04-291-0/+5
| | | | | | We didn't check that the file was large enough to hold a super block. llvm-svn: 267965
* [X86] Use nested switches to vary the operand to helper functions that were ↵Craig Topper2016-04-291-43/+74
| | | | | | previously called in multiple cases. This seems to help the inliner reduce code. NFC llvm-svn: 267964
* [llvm-pdbdump] Restore error messages, handle bad block sizesDavid Majnemer2016-04-281-1/+1
| | | | | | | We lost the ability to report errors, bring it back. Also, correctly validate the block size. llvm-svn: 267955
* LiveIntervalAnalysis: Remove LiveVariables requirementMatthias Braun2016-04-284-8/+11
| | | | | | | | | | | | This requirement was a huge hack to keep LiveVariables alive because it was optionally used by TwoAddressInstructionPass and PHIElimination. However we have AnalysisUsage::addUsedIfAvailable() which we can use in those passes. This re-applies r260806 with LiveVariables manually added to PowerPC to hopefully not break the stage 2 bots this time. llvm-svn: 267954
* [llvm-pdbdump] Correctly read data larger than a blockDavid Majnemer2016-04-281-25/+15
| | | | | | | | | A bug was introduced when the code was refactored which resulted in a bad memory access. This fixes PR27565. llvm-svn: 267953
* [LoopDist] Emit optimization remarks (-Rpass*)Adam Nemet2016-04-281-0/+25
| | | | | | | | | | | | | | | | I closely followed the precedents set by the vectorizer: * With -Rpass-missed, the loop is reported with further details pointing to -Rpass--analysis. * -Rpass-analysis reports the details why distribution has failed. * Regardless of -Rpass*, when distribution fails for a loop where distribution was forced with the pragma, a warning is produced according to -Wpass-failed. In this case the analysis info is also printed even without -Rpass-analysis. llvm-svn: 267952
* [LoopDist] Improve debug messagesAdam Nemet2016-04-281-6/+6
| | | | | | | | | | | The next patch will start using these for -Rpass-analysis so they won't be internal-only anymore. Move the 'Skipping; ' prefix that some of the message are using into the 'fail' function. We don't want to include this prefix in the -Rpass-analysis report. llvm-svn: 267951
* [LoopDist] Add helper to print debug message when distribution fails. NFCAdam Nemet2016-04-281-23/+20
| | | | | | This will form the basis to emit optimization remarks (-Rpass*). llvm-svn: 267950
* [Inliner] Preserve llvm.mem.parallel_loop_access metadataHal Finkel2016-04-281-0/+31
| | | | | | | | | | | | | | | | | | | | | | | When inlining a call site with llvm.mem.parallel_loop_access metadata, this metadata needs to be propagated to all cloned memory-accessing instructions. Otherwise, inlining parts of the loop body will invalidate the annotation. With this functionality, we now vectorize the following as expected: void Body(int *res, int *c, int *d, int *p, int i) { res[i] = (p[i] == 0) ? res[i] : res[i] + d[i]; } void Test(int *res, int *c, int *d, int *p, int n) { int i; #pragma clang loop vectorize(assume_safety) for (i = 0; i < 1600; i++) { Body(res, c, d, p, i); } } llvm-svn: 267949
* Read discriminators correctly from object file.Dehao Chen2016-04-282-48/+34
| | | | | | | | | | | | | | | Summary: This is the follow-up patch for http://reviews.llvm.org/D19436 * Update the discriminator reading algorithm to match the assignment algorithm. * Add test to cover the new algorithm. Reviewers: dnovillo, echristo, dblaikie Subscribers: danielcdh, dblaikie, echristo, llvm-commits, joker.eph Differential Revision: http://reviews.llvm.org/D19522 llvm-svn: 267945
* [CodeGen] Remove extra ';'Marcin Koscielnicki2016-04-281-1/+1
| | | | | | Squashes a -Wpedantic warning. llvm-svn: 267944
* [PowerPC] Fix the EH_SjLj_Setup pseudo.Marcin Koscielnicki2016-04-282-1/+6
| | | | | | | | | | | | | | | | | | | This instruction is just a control flow marker - it should not actually exist in the object file. Unfortunately, nothing catches it before it gets to AsmPrinter. If integrated assembler is used, it's considered to be a normal 4-byte instruction, and emitted as an all-0 word, crashing the program. With external assembler, a comment is emitted. Fixed by setting Size to 0 and handling it in MCCodeEmitter - this means the comment will still be emitted if integrated assembler is not used. This broke an ASan test, which has been disabled for a long time as a result (see the discussion on D19657). We can reenable it once this lands. llvm-svn: 267943
* [RDF] Recognize tail calls in graph creationKrzysztof Parzyszek2016-04-281-4/+20
| | | | llvm-svn: 267939
* Fix warning in PDB code. NFCAmaury Sechet2016-04-281-1/+1
| | | | llvm-svn: 267938
* LiveIntervalAnalysis: No need to deal with dead subregister defs anymore.Matthias Braun2016-04-281-20/+3
| | | | | | | | The DetectDeadLaneMask already ensures that we have no dead subregister definitions making the special handling in LiveIntervalAnalysis unnecessary. This reverts most of r248335. llvm-svn: 267937
* [RDF] Improve handling of inline-asmKrzysztof Parzyszek2016-04-281-4/+5
| | | | | | | - Keep implicit defs from inline-asm instructions. - Treat register references from inline-asm as fixed. llvm-svn: 267936
* Add parentheses to silence -Wparentheses warnings.Zachary Turner2016-04-281-6/+6
| | | | llvm-svn: 267934
* [RDF] Add option to keep dead phi nodes in DFGKrzysztof Parzyszek2016-04-283-4/+15
| | | | | | | | | | Dead phi nodes are needed for code motion (such as copy propagation), where a new use would be placed in a location that would be dominated by a dead phi. Such a transformation is not legal for copy propagation, and the existence of the phi would prevent it, but if the phi is not there, it may appear to be valid. llvm-svn: 267932
* Read the rest of the DBI substreams, and parse source info.Zachary Turner2016-04-281-11/+124
| | | | | | | | | | | | | We now read out the rest of the substreams from the DBI streams. One of these substreams, the FileInfo substream, contains information about which source files contribute to each module (aka compiland). This patch additionally parses out the file information from that substream, and dumps it in llvm-pdbdump. Differential Revision: http://reviews.llvm.org/D19634 Reviewed by: ruiu llvm-svn: 267928
* This reverts commit r265505.Kit Barton2016-04-287-268/+0
| | | | | | | Revert "[Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random number, set bool, and dfp test significance". This patch has caused a functional regression in SPEC2k6 namd, and a performance regression in mesa-pipe. llvm-svn: 267927
* [Hexagon] Add instruction aliases for vector unsigned compare-equalKrzysztof Parzyszek2016-04-281-0/+65
| | | | | | Unsigned compare-equal instructions are mapped to signed compare-equal. llvm-svn: 267925
* AMDGPU: Emit error if too much LDS is usedMatt Arsenault2016-04-281-0/+5
| | | | llvm-svn: 267922
* Remove doInitialization() and doFinalization() member declarations without ↵Yaron Keren2016-04-281-16/+0
| | | | | | | | definitions. Visual C++ 2015 flags this in the IDE. llvm-svn: 267919
* Reset the TopRPTracker's position in ScheduleDAGMILive::initQueuesKrzysztof Parzyszek2016-04-281-5/+11
| | | | | | | | | | | | | | | | | | | ScheduleDAGMI::initQueues changes the RegionBegin to the first non-debug instruction. Since it does not track register pressure, it does not affect any RP trackers. ScheduleDAGMILive inherits initQueues from ScheduleDAGMI, and it does reset the TopTPTracker in its schedule method. Any derived, target-specific scheduler will need to do it as well, but the TopRPTracker is only exposed as a "const" object to derived classes. Without the ability to modify the tracker directly, this leaves a derived scheduler with a potential of having the TopRPTracker out-of-sync with the CurrentTop. The symptom of the problem: void llvm::ScheduleDAGMILive::scheduleMI(llvm::SUnit *, bool): Assertion `TopRPTracker.getPos() == CurrentTop && "out of sync"' failed. Differential Revision: http://reviews.llvm.org/D19438 llvm-svn: 267918
* AMDGPU: Fix mishandling array allocations when promoting allocaMatt Arsenault2016-04-281-1/+3
| | | | | | | | The canonical form for allocas is a single allocation of the array type. In case we see a non-canonical array alloca, make sure we aren't replacing this with an array N times smaller. llvm-svn: 267916
* Add "PIE Level" metadata to module flags.Sriraman Tallam2016-04-281-0/+14
| | | | | | http://reviews.llvm.org/D19671 llvm-svn: 267911
* Fix some Clang-tidy modernize and Include What You Use warnings.Eugene Zelenko2016-04-281-6/+16
| | | | | | Differential revision: http://reviews.llvm.org/D19673 llvm-svn: 267910
* [PGO] Fix incorrect Twine usage in emitting optimization remarks.Rong Xu2016-04-281-9/+8
| | | | | | | Should not store Twine objects to local variables. This is fixed the test failures with r267815 in VS2015 X64 build. llvm-svn: 267908
* Minor format change and fixing typos in the comments. NFC.Rong Xu2016-04-281-10/+7
| | | | llvm-svn: 267905
* [Hexagon] Define certain aliases for vector instructionsKrzysztof Parzyszek2016-04-283-0/+43
| | | | | | | | | Specifically: Vd = #0 -> Vd = vxor(Vd, Vd) Vdd = #0 -> Vdd.w = vsub(Vdd.w, Vdd.w) Vdd = Vss -> Vdd = vcombine(Vss.H, Vss.L) llvm-svn: 267901
* [mips][atomics] Fix partword atomic binary operation implementationSimon Dardis2016-04-283-6/+15
| | | | | | | | | | | | | | | Currently Mips::emitAtomicBinaryPartword() does not properly respect the width of pointers. For MIPS64 this causes the memory address that the ll/sc sequence uses to be truncated. At runtime this causes a segmentation fault. This can be fixed by applying similar changes as r266204, so that a full 64bit pointer is loaded. Reviewers: dsanders Differential Review: http://reviews.llvm.org/D19651 llvm-svn: 267900
* [SLPVectorizer] Extend SLP Vectorizer to deal with aggregates.Arch D. Robison2016-04-281-37/+151
| | | | | | | | The refactoring portion part was done as r267748. http://reviews.llvm.org/D14185 llvm-svn: 267899
* [GVN] Minor code cleanup. NFC.Chad Rosier2016-04-281-65/+60
| | | | | | | Differential Revision: http://reviews.llvm.org/D18828 Patch by Aditya Kumar! llvm-svn: 267898
* [Hexagon] Handle double-vector registers as new-value producersKrzysztof Parzyszek2016-04-283-3/+42
| | | | | | Patch by Colin LeMahieu. llvm-svn: 267897
* Debug Info: Restore the pre-r240853 behavior for DWARF2 bitfields.Adrian Prantl2016-04-281-24/+10
| | | | | | | | | The DWARF2 specification of DW_AT_bit_offset is ambiguous for little-endian machines, but by restoring to the old behavior we match what debuggers expect and what other popular compilers generate. llvm-svn: 267896
* Debug info: Support DWARF4 bitfields via DW_AT_data_bit_offset.Adrian Prantl2016-04-281-28/+30
| | | | | | | | | | | | | The DWARF2 specification of DW_AT_bit_offset was written from the perspective of a big-endian machine with unclear semantics for other systems. DWARF4 deprecated DW_AT_bit_offset and introduced a new attribute DW_AT_data_bit_offset that simply counts the number of bits from the beginning of the containing entity regardless of endianness. After this patch LLVM emits DW_AT_bit_offset for DWARF 2 or 3 and DW_AT_data_bit_offset when DWARF 4 or later is requested. llvm-svn: 267895
* [EarlyCSE] Change LoadValue field Value *Data to Instruction *Inst. NFC.Geoff Berry2016-04-281-9/+9
| | | | | | Made in preparation for adding MemorySSA support to EarlyCSE. llvm-svn: 267893
* [RDF] Handle undefined registers in RDF copy propagationKrzysztof Parzyszek2016-04-281-1/+6
| | | | | | | When updating the graph, make sure that new uses without reaching defs are handled correctly. llvm-svn: 267891
* [EarlyCSE] Sort includes. NFC.Geoff Berry2016-04-281-1/+1
| | | | | | | | | | Reviewers: mcrosier Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D19617 llvm-svn: 267890
* Rangify for loops, NFC.Yaron Keren2016-04-281-22/+14
| | | | llvm-svn: 267889
* [Inliner] Formatting. NFC.Chad Rosier2016-04-281-36/+41
| | | | | | | Patch by Aditya Kumar! Differential Revision: http://reviews.llvm.org/D19047 llvm-svn: 267888
* [InstCombine] Remove trailing whitespace. NFC.Ahmed Bougacha2016-04-281-1/+1
| | | | | | r267873. llvm-svn: 267887
* [InstCombine][SSE] Add MOVMSK support to SimplifyDemandedUseBitsSimon Pilgrim2016-04-281-0/+22
| | | | | | | | | | The MOVMSK instructions copies a vector elements' sign bits to the low bits of a scalar register and zeros the high bits. This patch adds MOVMSK support to SimplifyDemandedUseBits so that its aware that the upper bits are known to be zero. It also removes the call to MOVMSK if none of the lower bits are actually required and just returns zero. Differential Revision: http://reviews.llvm.org/D19614 llvm-svn: 267873
* [X86] Remove unused operand from a function and all its callers. NFCCraig Topper2016-04-285-10/+8
| | | | llvm-svn: 267854
* [CodeGen] Default CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF to Expand in ↵Craig Topper2016-04-2815-85/+14
| | | | | | TargetLoweringBase. This is what the majority of the targets want and removes a bunch of code. Set it to Legal explicitly in the few cases where that's the desired behavior. llvm-svn: 267853
* CodeGen: Add DetectDeadLanes pass.Matthias Braun2016-04-284-0/+534
| | | | | | | | | | | | | | | | | | | | The DetectDeadLanes pass performs a dataflow analysis of used/defined subregister lanes across COPY instructions and instructions that will get lowered to copies. It detects dead definitions and uses reading undefined values which are obscured by COPY and subregister usage. These dead definitions cause trouble in the register coalescer which cannot deal with definitions suddenly becoming dead after coalescing COPY instructions. For now the pass only adds dead and undef flags to machine operands. It should be possible to extend it in the future to remove the dead instructions and redo the analysis for the affected virtual registers. Differential Revision: http://reviews.llvm.org/D18427 llvm-svn: 267851
* LiveIntervalAnalysis: Fix handleMove() using wrong value numbersMatthias Braun2016-04-281-2/+1
| | | | | | | | | | handleMove() was incorrectly swapping two value numbers. This was missed before because the problem only occured when moving subregister definitions and needed -verify-machineinstrs to be detected. I cannot add a testcase as long as I cannot reapply r260905/r260806. llvm-svn: 267840
* [AArch64] Expand CTTZ for all vector types.Craig Topper2016-04-281-0/+9
| | | | llvm-svn: 267837
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