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* [AArch64][SVE] Enable DiagnosticPredicates for SVE LD1 instructions.Sander de Smalen2018-04-261-14/+27
| | | | | | | | | | | | | | | | | | | | This patch extends the PredicateMethod of AsmOperands used in SVE's LD1 instructions with a DiagnosticPredicate. This makes them 'context sensitive' to the operand that has been parsed and tells the user to use the right register (with expected shift/extend), rather than telling the immediate is out of range when it actually parsed a register. Patch [2/2] in a series to improve assembler diagnostics for SVE: - Patch [1/2]: https://reviews.llvm.org/D45879 - Patch [2/2]: https://reviews.llvm.org/D45880 Reviewers: olista01, stoklund, craig.topper, mcrosier, rengolin, echristo, fhahn, SjoerdMeijer, evandro, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D45880 llvm-svn: 330934
* [NVPTX] Deduplicate code. No functionality change.Benjamin Kramer2018-04-261-18/+6
| | | | llvm-svn: 330933
* [RISCV] Implement isLegalAddressingMode for RISC-VAlex Bradbury2018-04-262-0/+30
| | | | | | | | | | | | This has no impact on codegen for the current RISC-V unit tests or my small benchmark set and very minor changes in a few programs in the GCC torture suite. Based on this, I haven't been able to produce a representative test program that demonstrates a benefit from isLegalAddressingMode. I'm committing the patch anyway, on the basis that presenting accurate information to the target-independent code is preferable to relying on incorrect generic assumptions. llvm-svn: 330932
* [LoopInterchange] Ignore debug intrinsics during legality checks.Florian Hahn2018-04-261-3/+3
| | | | | | | | | | | | Reviewers: aprantl, mcrosier, karthikthecool Reviewed By: aprantl Subscribers: mattd, vsk, #debug-info, llvm-commits Differential Revision: https://reviews.llvm.org/D45379 llvm-svn: 330931
* [AArch64][SVE] Asm: Support for gather LD1/LDFF1 (scalar + vector) load ↵Sander de Smalen2018-04-262-1/+212
| | | | | | | | | | | | | | | | | | instructions. Patch [2/3] in series to add support for SVE's gather load instructions that use scalar+vector addressing modes: - Patch [1/3]: https://reviews.llvm.org/D45951 - Patch [2/3]: https://reviews.llvm.org/D46023 - Patch [3/3]: https://reviews.llvm.org/D45958 Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D46023 llvm-svn: 330928
* [X86] Print 'tbyte ptr' instead of 'xword ptr' for f80mem in Intel syntax.Craig Topper2018-04-261-1/+1
| | | | | | This matches objdump. llvm-svn: 330922
* [X86] Remove alignment restriction on loading folding of pcmp[ei]str* during ↵Craig Topper2018-04-261-4/+4
| | | | | | | | isel too. This is a follow up to the changes in r330896 which enabled folding after isel during peephole and register allocation. llvm-svn: 330897
* [x86] Allow folding unaligned memory operands into pcmp[ei]str*Chandler Carruth2018-04-261-4/+4
| | | | | | | | | | | instructions. These have special permission according to the x86 manual to read unaligned memory, and this folding is done by ICC and GCC as well. This corrects one of the issues identified in PR37246. llvm-svn: 330896
* Revert "[SCEV] Make computeExitLimit more simple and more powerful"Max Kazantsev2018-04-261-17/+58
| | | | | | | | | | | This reverts commit 023c8be90980e0180766196cba86f81608b35d38. This patch triggers miscompile of zlib on PowerPC platform. Most likely it is caused by some pre-backend PPC-specific pass, but we don't clearly know the reason yet. So we temporally revert this patch with intention to return it once the problem is resolved. See bug 37229 for details. llvm-svn: 330893
* [codeview] Ignore .cv_loc directives at the end of a functionReid Kleckner2018-04-253-0/+19
| | | | | | | | | | If no data or instructions are emitted after a location directive, we should clear the cv_loc when we change sections, or it will be emitted at the beginning of the next section. This violates our invariant that all .cv_loc directives belong to the same section. Add clearer assertions for this. llvm-svn: 330884
* [CostModel][X86] Remove hard coded SDIV/UDIV vector costsSimon Pilgrim2018-04-251-37/+13
| | | | | | Algorithmically compute the 'x20' SDIV/UDIV vector costs - this is necessary for PR36550 when DIV costs will be driven from the scheduler models. llvm-svn: 330870
* AMDGPU/R600: Move int_r600_store_stream_output to the public intrinsic fileTom Stellard2018-04-251-4/+0
| | | | | | | | | | | | | | | | Summary: The TableGen'd GlobalISel instruction selector assumes all intrinsics are in the public Intrinsic:: namespace. Reviewers: jvesely, nhaehnle Reviewed By: jvesely, nhaehnle Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45989 llvm-svn: 330866
* [AMDGPU] Waitcnt pass: add debug optionsMark Searles2018-04-251-11/+75
| | | | | | | | | | | | | | | | | - Add "amdgpu-waitcnt-forcezero" to force all waitcnt instrs to be emitted as s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) - Add debug counters to control force emit of s_waitcnt instrs; debug counters: si-insert-waitcnts-forceexp: force emit s_waitcnt expcnt(0) instrs si-insert-waitcnts-forcevm: force emit s_waitcnt lgkmcnt(0) instrs si-insert-waitcnts-forcelgkm: force emit s_waitcnt vmcnt(0) instrs - Add some debug statements Note that a variant of this patch was previously committed/reverted. Differential Revision: https://reviews.llvm.org/D45888 llvm-svn: 330862
* [SimplifyLibcalls] Atoi, strtol replacementsDavid Bolvansky2018-04-251-0/+55
| | | | | | | | | | | | Reviewers: spatel, lebedev.ri, xbolva00, efriedma Reviewed By: xbolva00, efriedma Subscribers: efriedma, llvm-commits Differential Revision: https://reviews.llvm.org/D45418 llvm-svn: 330860
* [MIR] Add support for debug metadata for fixed stack objectsFrancis Visoiu Mistrih2018-04-252-17/+28
| | | | | | | | | | | | | | | Debug var, expr and loc were only supported for non-fixed stack objects. This patch adds the following fields to the "fixedStack:" entries, and renames the ones from "stack:" to: * debug-info-variable * debug-info-expression * debug-info-location Differential Revision: https://reviews.llvm.org/D46032 llvm-svn: 330859
* [WebAssebmly] Add Module name to WasmSymbolSam Clegg2018-04-251-0/+1
| | | | | | | | | | | | Imports in a wasm module can have custom module name. This change adds the module name to the WasmSymbol structure so that the linker can preserve this module name. This is needed to fix: https://bugs.llvm.org/show_bug.cgi?id=37168 Differential Revision: https://reviews.llvm.org/D45797 llvm-svn: 330854
* [X86] Form MUL_IMM for multiplies with 3/5/9 to encourage LEA formation over ↵Craig Topper2018-04-251-2/+6
| | | | | | | | | | load folding. Previously we only formed MUL_IMM when we split a constant. This blocked load folding on those cases. We should also form MUL_IMM for 3/5/9 to favor LEA over load folding. Differential Revision: https://reviews.llvm.org/D46040 llvm-svn: 330850
* [RISCV] Allow call pseudoinstruction to be used to call a function name that ↵Alex Bradbury2018-04-251-9/+12
| | | | | | | | | | coincides with a register name Previously `call zero`, `call f0` etc would fail. This leads to compilation failures if building programs that define functions with those names and using -save-temps. llvm-svn: 330846
* [ICP] Do not attempt type matching for variable length arguments.Taewook Oh2018-04-251-5/+7
| | | | | | | | | | | | | | | | | Summary: When performing indirect call promotion, current implementation inspects "all" parameters of the callsite and attemps to match with the formal argument type of the callee function. However, it is not possible to find the type for variable length arguments, and the compiler crashes when it attemps to match the type for variable lenght argument. It seems that the bug is introduced with D40658. Prior to that, the type matching is performed only for the parameters whose ID is less than callee->getFunctionNumParams(). The attached test case will crash without the patch. Reviewers: mssimpso, davidxl, davide Reviewed By: mssimpso Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D46026 llvm-svn: 330844
* Rename Attributes.gen, Intrinsics.gen to Attributes.inc, Intrinsics.incNico Weber2018-04-251-7/+7
| | | | | | | | | Virtually all other tablegen outputs are called .inc, not .gen, so rename these two too for consistency. No behavior change. https://reviews.llvm.org/D46058 llvm-svn: 330843
* [InstCombine] clean up foldSelectICmpAnd(); NFCSanjay Patel2018-04-251-46/+39
| | | | | | | | | | As discussed in D45862, we want to delete parts of this code because it can create more instructions than it removes. But we also want to preserve some folds that are winners, so tidy up what's here to make splitting the good from bad a bit easier. llvm-svn: 330841
* [CostModel][X86] Recursive call for cost of imul for packed v16i16 constant ↵Simon Pilgrim2018-04-251-1/+3
| | | | | | | | shift left. Don't just assume cost = 1. llvm-svn: 330834
* [AArch64][GlobalISel] Implement selection for the llvm.trap intrinsic.Amara Emerson2018-04-251-0/+9
| | | | | | rdar://38674040 llvm-svn: 330831
* [RISCV] Expand function call to "call" pseudoinstructionShiva Chen2018-04-253-10/+18
| | | | | | | | | | | | | | | | To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
* [RISCV] Support "call" pseudoinstruction in the MC layerShiva Chen2018-04-257-4/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | To do this: 1. Add PseudoCALLIndirct to match indirect function call. 2. Add PseudoCALL to support parsing and print pseudo `call` in assembly 3. Expand PseudoCALL to the following form with R_RISCV_CALL relocation type while encoding: auipc ra, func jalr ra, ra, 0 If we expand PseudoCALL before emitting assembly, we will see auipc and jalr pair when compile with -S. It's hard for assembly parser to parsing this pair and identify it's semantic is function call and then insert R_RISCV_CALL relocation type. Although we could insert R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO12_I relocation types instead of R_RISCV_CALL. Due to RISCV relocation design, auipc and jalr pair only can relax to jal with R_RISCV_CALL + R_RISCV_RELAX relocation types. We expand PseudoCALL as late as encoding(RISCVMCCodeEmitter) instead of before emitting assembly(RISCVAsmPrinter) because we want to preserve call pseudoinstruction in assembly code. It's more readable and assembly parser could identify call assembly and insert R_RISCV_CALL relocation type. Differential Revision: https://reviews.llvm.org/D45859 llvm-svn: 330826
* [mips] Teach the delay slot filler to transform 'jal' for microMIPSSimon Dardis2018-04-251-0/+1
| | | | | | | | | | ISel is currently picking 'JAL' over 'JAL_MM' for calling a function when targeting microMIPS. A later patch will correct this behaviour. This patch extends the mechanism for transforming instructions into their short delay to recognise 'JAL_MM' for transforming into 'JALS_MM'. llvm-svn: 330825
* [X86] Split WriteFMA into XMM, Scalar and YMM/ZMM scheduler classesSimon Pilgrim2018-04-2512-170/+201
| | | | | | | | This removes all the FMA InstRW overrides. If we ever get PR36924, then we can remove many of these declarations from models. llvm-svn: 330820
* [AMDGPU] Revert b0efc4fd6 (https://reviews.llvm.org/D40556)Alexander Timofeev2018-04-251-64/+15
| | | | llvm-svn: 330818
* [X86][SKX] Setup WriteFAdd and remove unnecessary InstRW scheduler overrides.Simon Pilgrim2018-04-251-140/+7
| | | | llvm-svn: 330813
* [X86][SNB] Remove unnecessary WriteFBlendLd InstRW scheduler overrides.Simon Pilgrim2018-04-251-4/+2
| | | | llvm-svn: 330812
* [mips] Fix the definition of sync, synciSimon Dardis2018-04-255-11/+36
| | | | | | | | | | Also, fix the disassembly of synci for microMIPS. Reviewers: abeserminji, smaksimovic, atanasyan Differential Revision: https://reviews.llvm.org/D45870 llvm-svn: 330810
* [LoopInterchange] Use getExitBlock()/getExitingBlock instead of manual impl.Florian Hahn2018-04-251-33/+27
| | | | | | | | | | | | | | | This also means we have to check if the latch is the exiting block now, as `transform` expects the latches to be the exiting blocks too. https://bugs.llvm.org/show_bug.cgi?id=36586 Reviewers: efriedma, davide, karthikthecool Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D45279 llvm-svn: 330806
* [AArch64][SVE] Asm: Add AsmOperand classes for SVE gather/scatter addressing ↵Sander de Smalen2018-04-254-8/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | modes. This patch adds parsing support for 'vector + shift/extend' and corresponding asm operand classes, needed for implementing SVE's gather/scatter addressing modes. The added combinations of vector (ZPR) and Shift/Extend are: Unscaled: ZPR64ExtLSL8: signed 64-bit offsets (z0.d) ZPR32ExtUXTW8: unsigned 32-bit offsets (z0.s, uxtw) ZPR32ExtSXTW8: signed 32-bit offsets (z0.s, sxtw) Unpacked and unscaled: ZPR64ExtUXTW8: unsigned 32-bit offsets (z0.d, uxtw) ZPR64ExtSXTW8: signed 32-bit offsets (z0.d, sxtw) Unpacked and scaled: ZPR64ExtUXTW<scale>: unsigned 32-bit offsets (z0.d, uxtw #<shift>) ZPR64ExtSXTW<scale>: signed 32-bit offsets (z0.d, sxtw #<shift>) Scaled: ZPR32ExtUXTW<scale>: unsigned 32-bit offsets (z0.s, uxtw #<shift>) ZPR32ExtSXTW<scale>: signed 32-bit offsets (z0.s, sxtw #<shift>) ZPR64ExtLSL<scale>: unsigned 64-bit offsets (z0.d, lsl #<shift>) ZPR64ExtLSL<scale>: signed 64-bit offsets (z0.d, lsl #<shift>) Patch [1/3] in series to add support for SVE's gather load instructions that use scalar+vector addressing modes: - Patch [1/3]: https://reviews.llvm.org/D45951 - Patch [2/3]: https://reviews.llvm.org/D46023 - Patch [3/3]: https://reviews.llvm.org/D45958 Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D45951 llvm-svn: 330805
* [DebugInfo] Invalidate debug info in ReassociatePass::RewriteExprTreeBjorn Pettersson2018-04-251-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When Reassociate is rewriting an expression tree it may reuse old binary expression nodes, for new expressions. Whenever an expression node is reused, but with a non-trivial change in the result, we need to invalidate any debug info that is associated with the node. If for example rewriting x = mul a, b y = mul c, x into x = mul c, b y = mul a, x we still get the same result for 'y', but 'x' is a new expression. All debug info referring to 'x' must be invalidated (marked as optimized out) since we no longer calculate the expected value. As a side-effect this patch avoid (at least some) problems where reassociate could end up creating IR with debug-use before def. Earlier the dbg.value nodes where left untouched in the IR, while the reused binary nodes where sinked to just before the root node of the rewritten expression tree. See PR27273 for more info about such problems. Reviewers: dblaikie, aprantl, dexonsmith Reviewed By: aprantl Subscribers: JDevlieghere, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D45975 llvm-svn: 330804
* Merging r46043:David Bolvansky2018-04-251-3/+3
| | | | | | ------------------------------------------------------------------------ llvm-svn: 330799
* [DivRemPairs] Fix non-determinism in use list order.Geoff Berry2018-04-251-3/+8
| | | | | | | | | | | | | | | | | Summary: Use a MapVector instead of a DenseMap for RemMap since it is iteratated over and the order of iteration can effect the order that new instructions are created. This can in turn effect the use list order of div/rem input values if multiple new instructions are created that share any input values. Reviewers: spatel Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D45858 llvm-svn: 330792
* [PM/LoopUnswitch] Begin teaching SimpleLoopUnswitch to use the newChandler Carruth2018-04-251-70/+78
| | | | | | | | | | | | | | | | | | | | | | | update API for dominators rather than doing manual, hacky updates. This is just the first step, but in some ways the most important as it moves the non-trivial unswitching to update the domtree rather than fully recalculating it each time. Subsequent patches should remove the custom update logic used by the trivial unswitch and replace it with uses of the update API. This also fixes a number of bugs I was seeing when testing non-trivial unswitch due to it querying the quasi-correct dominator tree. Now the tree is 100% correct and safe to query. That said, there are still more bugs I can see with non-trivial unswitch just running over the test suite, so more bugfix patches are needed as well. Thanks to both Sanjoy and Fedor for reviews and testing! Differential Revision: https://reviews.llvm.org/D45943 llvm-svn: 330787
* [MachineOutliner] Check for explicit uses of LR/W30 in MI operandsJessica Paquette2018-04-241-0/+5
| | | | | | | | | | Before, the outliner would grab ADRPs that used LR/W30. This patch fixes that by checking for explicit uses of those registers before the special-casing for ADRPs. This also adds a test that ensures that those sorts of ADRPs won't be outlined. llvm-svn: 330783
* [DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legalCraig Topper2018-04-241-8/+4
| | | | | | | | | | | | We were previously prefering ZEXTLOAD over EXTLOAD if it is legal. This triggers during X86's promotion of i16->i32. Not sure about other targets. Using ZEXTLOAD can prevent folding it to SEXTLOAD later if we were to promote a sign extended operand like we would need for SRA. However, X86 doesn't currently promote i16 SRA. I was looking into doing that which is how I found this issue. This is also blocking our ability to fold 4 byte aligned EXTLOADs with "loadi32". This is what caused most of the test changes here. Differential Revision: https://reviews.llvm.org/D45585#inline-402825 llvm-svn: 330781
* [X86] Account for partial stack slot spills (PR30821)Warren Ristow2018-04-243-81/+134
| | | | | | | | | | | | | | | | | | | | | | | Previously, _any_ store or load instruction was considered to be operating on a spill if it had a frameindex as an operand, and thus was fair game for optimisations such as "StackSlotColoring". This usually works, except on architectures where spills can be partially restored, for example on X86 where a spilt vector can have a single component loaded (zeroing the rest of the target register). This can be mis-interpreted and the zero extension unsoundly eliminated, see pr30821. To avoid this, this commit optionally provides the caller to isLoadFromStackSlot and isStoreToStackSlot with the number of bytes spilt/loaded by the given instruction. Optimisations can then determine that a full spill followed by a partial load (or vice versa), for example, cannot necessarily be commuted. Patch by Jeremy Morse! Differential Revision: https://reviews.llvm.org/D44782 llvm-svn: 330778
* AMDGPU: Remove deprecated llvm.AMDGPU.kilp intrinsicTom Stellard2018-04-243-11/+0
| | | | | | | | | | | | | | Summary: This is no longer used by mesa since its 18.0.0 release. Reviewers: nhaehnle Reviewed By: nhaehnle Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D45988 llvm-svn: 330775
* AMDGPU/GlobalISel: Fall-back to SelectionDAG for non-void functionsTom Stellard2018-04-241-0/+4
| | | | | | | | | | | | Reviewers: arsenm, nhaehnle Reviewed By: nhaehnle Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45843 llvm-svn: 330774
* [CaptureTracking] Fixup const correctness of DomTree arg (NFC)Daniel Neilson2018-04-241-3/+3
| | | | | | | | | Summary: The PointerMayBeCapturedBefore function's DomTree arg should be const instead of non-const. There are no non-const uses of it in the function. llvm-svn: 330769
* AMDGPU/GlobalISel: Add support for amdgpu_ps calling conventionTom Stellard2018-04-241-14/+49
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45837 llvm-svn: 330767
* [wasm] Fix uninitialized memory introduced in r330749.Chandler Carruth2018-04-241-1/+1
| | | | | | | Found with MSan. This was causing all the WASM MC tests to fail about 10% of the time. llvm-svn: 330764
* [X86][SKX] Setup WriteFMul and remove unnecessary InstRW scheduler overrides.Simon Pilgrim2018-04-241-27/+1
| | | | llvm-svn: 330760
* [X86] Split off PHMINPOSUW to their own schedule classSimon Pilgrim2018-04-2411-12/+14
| | | | | | This also fixes Jaguar's schedule which was treating it as the WriteVecIMul default. llvm-svn: 330756
* [AMDGPU] Truncate packed inline constantStanislav Mekhanoshin2018-04-242-1/+8
| | | | | | | | | | | | | | | | If a packed inline constant is sign extended it must be truncated after the shift. I.e. a constant (0xH0000, 0xHBC00), will be represented as 0xFFFFFFFFBC000000 in the IR because the immediate is sign extended to 64 bit. After the value shifted right by 16 to use it in a low part with op_sel_hi it becomes 0xFFFFFFFFBC00 and does not qualify as inline constant any longer. Fixed the error and added verification code. Without the fix and with the verification bug is causing pk_max_f16_literal.ll to fail. Differential Revision: https://reviews.llvm.org/D45987 llvm-svn: 330752
* [XOP] v4i32 IFMA 'VPMACS' instructions should use the WritePMULLD schedule classSimon Pilgrim2018-04-241-15/+28
| | | | llvm-svn: 330751
* [WebAssembly] Use section index in relocation section headerSam Clegg2018-04-242-78/+37
| | | | | | | | | | | Rather than referring to sections my their code, use the absolute index of the target section within the module. See https://github.com/WebAssembly/tool-conventions/issues/52 Differential Revision: https://reviews.llvm.org/D45980 llvm-svn: 330749
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