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* [InstCombine] Add range metadata to cttz/ctlz/ctpop intrinsic calls based on ...Craig Topper2017-06-211-0/+46
* [InstCombine] Don't let folding (select (icmp eq (and X, C1), 0), Y, (or Y, C...Craig Topper2017-06-211-4/+16
* [Reassociate] Support xor reassociating for splat vectorsCraig Topper2017-06-211-24/+22
* [AMDGPU][MC][GFX9] Corrected VOP3P relevant code to fix disassembler failuresDmitry Preobrazhensky2017-06-214-11/+6
* [DAG] Move BaseIndexOffset into separate Libarary. NFC.Nirav Dave2017-06-213-114/+97
* [DAG] Remove Node csonstruction from BaseIndexOffset match. NFCI.Nirav Dave2017-06-211-52/+69
* [AMDGPU][MC] Corrected V_*QSAD* instructions to check that dest register is d...Dmitry Preobrazhensky2017-06-213-5/+84
* [x86] fix formatting; NFCSanjay Patel2017-06-211-15/+13
* [AARCH64][LSE] Preliminary support for ARMv8.1 LSE Atomics.Christof Douma2017-06-214-5/+114
* [Support] Add RetryAfterSignal helper functionPavel Labath2017-06-213-25/+12
* [AArch64] Add early exit to promoteLoadFromStore.Florian Hahn2017-06-211-1/+4
* [MIPS] Fix for selecting of DINS/INS instructionStrahinja Petrovic2017-06-211-0/+5
* Use range-loop in machine-scheduler. NFCI.Javed Absar2017-06-211-94/+72
* [AMDGPU] SDWA: merge VI and GFX9 pseudo instructionsSam Kolton2017-06-2115-281/+323
* [AArch64] Preserve register flags when promoting a load from store.Florian Hahn2017-06-211-3/+4
* [DAGCombiner] Add another combine from build vector to shuffleGuy Blank2017-06-211-0/+5
* [SCEV] Make MulOpsInlineThreshold lower to avoid excessive compilation timeMax Kazantsev2017-06-211-1/+1
* [XRay] Reduce synthetic references emitted by XRayDean Michael Berris2017-06-211-8/+6
* [ImplicitNullChecks] Uphold an invariant in areMemoryOpsAliasedSerguei Katkov2017-06-211-24/+15
* [NewGVN] Fix a bug that made the store verifier less effective.Davide Italiano2017-06-201-6/+4
* clang-format a region.Rafael Espindola2017-06-201-20/+19
* [codeview] YAMLize all section offsets and indices in symbol recordsReid Kleckner2017-06-201-24/+22
* Fix a crash in DwarfDebug::validThroughout.Adrian Prantl2017-06-201-3/+5
* [Statepoint] Add helper functions for GCRelocate and GCResultAnna Thomas2017-06-201-0/+12
* Support: chunk writing on LinuxSaleem Abdulrasool2017-06-202-1/+16
* AMDGPU: Allow vectorization of packed typesMatt Arsenault2017-06-202-8/+20
* [codeview] Fully initialize DataSym when mapping from YAMLReid Kleckner2017-06-201-0/+2
* [AMDGPU] Fix illegal shrink of V_SUBB_U32 and V_ADDC_U32Stanislav Mekhanoshin2017-06-201-0/+2
* AMDGPU: Start adding global_* instructionsMatt Arsenault2017-06-206-6/+106
* [GISel]: Add G_FMA opcode for fused multiply addsAditya Nandakumar2017-06-201-0/+7
* AMDGPU: Do operand folding in program orderMatt Arsenault2017-06-201-5/+3
* [PDB] Don't write uninitialized bytes to a PDB file.Zachary Turner2017-06-202-0/+3
* RegisterScavenging: Followup to r305625Matthias Braun2017-06-201-41/+38
* AMDGPU: Preserve undef when folding register operandsMatt Arsenault2017-06-201-0/+2
* [AMDGPU] Eliminate SGPR to VGPR copy when possibleStanislav Mekhanoshin2017-06-201-0/+30
* AMDGPU: Fix crash with undef vreg input operandMatt Arsenault2017-06-201-1/+1
* [PowerPC] fix trivial typos in comment, NFCHiroshi Inoue2017-06-201-1/+1
* [GSoC] Flag value completion for clangYuka Takahashi2017-06-203-6/+39
* [x86] enable CGP memcmp() expansion for 2/4/8 byte sizesSanjay Patel2017-06-203-1/+13
* [X86][SSE] Relax 0/-1 vector element insertion to work for any vector with >=...Simon Pilgrim2017-06-201-1/+2
* DAG: correctly legalize UMULO.Tim Northover2017-06-201-11/+18
* [InstCombine] fix code/test comments for r305792; NFCSanjay Patel2017-06-201-1/+1
* [InstCombine] try to canonicalize xor-of-icmps to and-of-icmpsSanjay Patel2017-06-201-0/+24
* [globalisel][tablegen] Add support for COPY_TO_REGCLASS.Daniel Sanders2017-06-202-10/+30
* [X86][SSE] Dropped old INSERT_VECTOR_ELT lowering TODOSimon Pilgrim2017-06-201-2/+0
* [GlobalISel][X86] fix compilation error ( -Werror=unused-function )Igor Breger2017-06-201-2/+2
* [SelectionDAG] Fix an use-after-free issue introduced in r305775.Haojian Wu2017-06-201-2/+2
* [GlobalISel][X86] Get correct RegClass for given RegBank.Igor Breger2017-06-201-17/+26
* [GlobalISel] combine not symmetric merge/unmerge nodes.Igor Breger2017-06-201-13/+58
* [SCEV][NFC] Fix a misleading description of AddOpsInlineThresholdMax Kazantsev2017-06-201-1/+1
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