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* Remove trailing whitespace. NFCI.Simon Pilgrim2017-06-231-1/+1
| | | | llvm-svn: 306121
* GlobalISel: remove G_SEQUENCE instruction.Tim Northover2017-06-233-76/+1
| | | | | | | | It was trying to do too many things. The basic lumping together of values for legalization purposes is now handled by G_MERGE_VALUES. More complex things involving gaps and odd sizes are handled by G_INSERT sequences. llvm-svn: 306120
* GlobalISel: convert buildSequence to use non-deprecated instructions.Tim Northover2017-06-232-10/+26
| | | | | | | | G_SEQUENCE is going away soon so as a first step the MachineIRBuilder needs to be taught how to emulate it with alternatives. We use G_MERGE_VALUES where possible, and a sequence of G_INSERTs if not. llvm-svn: 306119
* [InlineCost] Do not take INT_MAX when Cost is negativeJun Bum Lim2017-06-231-5/+11
| | | | | | | | | | | | | | Summary: visitSwitchInst should not take INT_MAX when Cost is negative. Instead of INT_MAX , we also use a valid upperbound cost when overflow occurs in Cost. Reviewers: hans, echristo, dmgreen Reviewed By: dmgreen Subscribers: mcrosier, javed.absar, llvm-commits, eraman Differential Revision: https://reviews.llvm.org/D34436 llvm-svn: 306118
* [SystemZ] Remove unnecessary serialization before volatile loadsUlrich Weigand2017-06-234-17/+6
| | | | | | | | | | | | | | | | | This reverts the use of TargetLowering::prepareVolatileOrAtomicLoad introduced by r196905. Nothing in the semantics of the "volatile" keyword or the definition of the z/Architecture actually requires that volatile loads are preceded by a serialization operation, and no other compiler on the platform actually implements this. Since we've now seen a use case where this additional serialization causes noticable performance degradation, this patch removes it. The patch still leaves in the serialization before atomic loads, which is now implemented directly in lowerATOMIC_LOAD. (This also seems overkill, but that can be addressed separately.) llvm-svn: 306117
* AMDGPU/GlobalISel: Mark 32-bit G_AND as legalTom Stellard2017-06-231-0/+1
| | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D34349 llvm-svn: 306112
* [SystemZ] Fix trap issue and enable expensive checks.Jonas Paulsson2017-06-232-8/+3
| | | | | | | | | | | | | | | | | | | | | | | The isBarrier/isTerminator flags have been removed from the SystemZ trap instructions, so that tests do not fail with EXPENSIVE_CHECKS. This was just an issue at -O0 and did not affect code output on benchmarks. (Like Eli pointed out: "targets are split over whether they consider their "trap" a terminator; x86, AArch64, and NVPTX don't, but ARM, MIPS, PPC, and SystemZ do. We should probably try to be consistent here.". This is still the case, although SystemZ has switched sides). SystemZ now returns true in isMachineVerifierClean() :-) These Generic tests have been modified so that they can be run with or without EXPENSIVE_CHECKS: CodeGen/Generic/llc-start-stop.ll and CodeGen/Generic/print-machineinstrs.ll Review: Ulrich Weigand, Simon Pilgrim, Eli Friedman https://bugs.llvm.org/show_bug.cgi?id=33047 https://reviews.llvm.org/D34143 llvm-svn: 306106
* [RuntimeLoopUnrolling] Rename exit block and move assert earlier. NFCAnna Thomas2017-06-231-23/+23
| | | | | | | The single exit block allowed in runtime unrolling is guaranteed to be the Latch's successor, so rename it as LatchExitBlock. llvm-svn: 306105
* [InstCombine] Recognize and simplify three way comparison idiomsAnna Thomas2017-06-232-4/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Many languages have a three way comparison idiom where comparing two values produces not a boolean, but a tri-state value. Typical values (e.g. as used in the lcmp/fcmp bytecodes from Java) are -1 for less than, 0 for equality, and +1 for greater than. We actually do a great job already of converting three way comparisons into binary comparisons when the result produced has one a single use. Unfortunately, such values can have more than one use, and in that case, our existing optimizations break down. The patch adds a peephole which converts a three-way compare + test idiom into a binary comparison on the original inputs. It focused on replacing the test on the result of the three way compare and does nothing about removing the three way compare itself. That's left to other optimizations (which do actually kick in commonly.) We currently recognize one idiom on signed integer compare. In the future, we plan to recognize and simplify other comparison idioms on other signed/unsigned datatypes such as floats, vectors etc. This is a resurrection of Philip Reames' original patch: https://reviews.llvm.org/D19452 Reviewers: majnemer, apilipenko, reames, sanjoy, mkazantsev Reviewed by: mkazantsev Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34278 llvm-svn: 306100
* Revert r306095: [mips] Fix reg positions in the aui/daui instructionsPetar Jovanovic2017-06-231-3/+3
| | | | | | | | | | | | | | | ELF/mips-plt-r6.s in lld-test is failing. Reverting the change. Original commit message: [mips] Fix register positions in the aui/daui instructions Swapped the position of the rt and rs register in the aut/daui instructions for mips32r6 and mips64r6. With this change, the format of the generated instructions complies with specifications and GCC. Patch by Milos Stojanovic. llvm-svn: 306099
* [ADT] Add llvm::to_floatPavel Labath2017-06-232-19/+11
| | | | | | | | | | | | | | | | | | Summary: The function matches the interface of llvm::to_integer, but as we are calling out to a C library function, I let it take a Twine argument, so we can avoid a string copy at least in some cases. I add a test and replace a couple of existing uses of strtod with this function. Reviewers: zturner Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34518 llvm-svn: 306096
* [mips] Fix register positions in the aui/daui instructionsPetar Jovanovic2017-06-231-3/+3
| | | | | | | | | | | | Swapped the position of the rt and rs register in the aut/daui instructions for mips32r6 and mips64r6. With this change, the format of the generated instructions complies with specifications and GCC. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D33988 llvm-svn: 306095
* [mips][msa] Splat.d endianness checkStefan Maksimovic2017-06-231-6/+12
| | | | | | | | | | | | | Before this change, it was always the first element of a vector that got splatted since the lower 6 bits of vshf.d $wd were always zero for little endian. Additionally, masking has been performed for vshf via which splat.d is created. Vshf has a property where if its first operand's elements have either bit 6 or 7 set, destination element is set to zero. Initially masked with 63 to avoid this property, which would result in generation of and.v + vshf.d in all cases. Masking with one results in generating a single splati.d instruction when possible. Differential Revision: https://reviews.llvm.org/D32216 llvm-svn: 306090
* [JumpThreading] Teach jump threading how to analyze (and (cmp A, C1), (cmp ↵Craig Topper2017-06-232-0/+61
| | | | | | | | | | | | | | A, C2)) after InstCombine has turned it into (cmp (add A, C3), C4) Currently JumpThreading can use LazyValueInfo to analyze an 'and' or 'or' of compare if the compare is fed by a livein of a basic block. This can be used to to prove the condition can't be met for some predecessor and the jump from that predecessor can be moved to the false path of the condition. But if the compare is something that InstCombine turns into an add and a single compare, it can't be analyzed because the livein is now an input to the add and not the compare. This patch adds a new method to LVI to get a ConstantRange on an edge. Then we teach jump threading to detect the add livein feeding a compare and to get the ConstantRange and propagate it. Differential Revision: https://reviews.llvm.org/D33262 llvm-svn: 306085
* [JumpThreading] Use some temporary variables to reduce the number of times ↵Craig Topper2017-06-231-12/+16
| | | | | | | | we call the same methods. NFC A future patch will add even more uses of these variables. llvm-svn: 306084
* COFF: Produce an error on invalid pcrel relocs.Rafael Espindola2017-06-233-9/+19
| | | | | | | | | | X86_64 COFF only has support for 32 bit pcrel relocations. Produce an error on all others. Note that gnu as has extended the relocation values to support this. It is not clear if we should support the gnu extension. llvm-svn: 306082
* [LoopSimplify] Factor the logic to form dedicated exits into a utility.Chandler Carruth2017-06-232-62/+83
| | | | | | | | | | | | | | | | | | | | | | I want to use the same logic as LoopSimplify to form dedicated exits in another pass (SimpleLoopUnswitch) so I wanted to factor it out here. I also noticed that there is a pretty significantly more efficient way to implement this than the way the code in LoopSimplify worked. We don't need to actually retain the set of unique exit blocks, we can just rewrite them as we find them and use only a set to deduplicate. This did require changing one part of LoopSimplify to not re-use the unique set of exits, but it only used it to check that there was a single unique exit. That part of the code is about to walk the exiting blocks anyways, so it seemed better to rewrite it to use those exiting blocks to compute this property on-demand. I also had to ditch a statistic, but it doesn't seem terribly valuable. Differential Revision: https://reviews.llvm.org/D34049 llvm-svn: 306081
* COFF: handle "undef - ." expressions.Rafael Espindola2017-06-231-11/+0
| | | | | | | This is another thing that the ELF implementation can do but is missing from COFF. llvm-svn: 306078
* [LVI] Teach LVI to reason about ORs of icmps similar to how it reasons about ↵Craig Topper2017-06-231-5/+5
| | | | | | | | | | | | | | | | ANDs of icmps Summary: LVI can reason about an AND of icmps on the true dest of a branch. I believe we can do similar for the false dest of ORs. This allows us to get the same answer for the demorganed versions of some of the AND test cases as you can see. Reviewers: anna, reames Reviewed By: reames Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34431 llvm-svn: 306076
* Fixed a (product) build error that was due to an unused variableFarhana Aleen2017-06-221-2/+1
| | | | | | | | | | | | | Details: There was a use but it was in the assert which was not exercised during product build. Reviewers: Andrew Kaylor Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32658 llvm-svn: 306073
* [x86] add/sub (X==0) --> sbb(cmp X, 1)Sanjay Patel2017-06-221-5/+17
| | | | | | | | | | | | | | | | | | | | | | This is very similar to the transform in: https://reviews.llvm.org/rL306040 ...but in this case, we use cmp X, 1 to set the carry bit as needed. Again, we can show that all of these are logically equivalent (although InstCombine currently canonicalizes to a form not seen here), and if we believe IACA, then this is the smallest/fastest code. Eg, with SNB: | Num Of | Ports pressure in cycles | | | Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | | --------------------------------------------------------------------- | 1 | 1.0 | | | | | | | cmp edi, 0x1 | 2 | | 1.0 | | | | 1.0 | CP | sbb eax, eax The larger motivation is to clean up all select-of-constants combining/lowering because we're missing some common cases. llvm-svn: 306072
* Restrict the definition of loop preheader to avoid EH blocksAndrew Kaylor2017-06-222-0/+19
| | | | | | Differential Revision: https://reviews.llvm.org/D34487 llvm-svn: 306070
* Define behavior of "stack-probe-size" attribute when inlining.whitequark2017-06-221-2/+28
| | | | | | | | | | Also document the attribute, since "probe-stack" already is. Reviewed By: majnemer Differential Revision: https://reviews.llvm.org/D34528 llvm-svn: 306069
* Supported lowerInterleavedStore() in X86InterleavedAccess.Farhana Aleen2017-06-222-31/+101
| | | | | | | | | | Reviewers: RKSimon, DavidKreitzer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32658 llvm-svn: 306068
* Remove the LoadCombine pass. It was never enabled and is unsupported.Eric Christopher2017-06-225-311/+0
| | | | | | Based on discussions with the author on mailing lists. llvm-svn: 306067
* Change creation of relative relocations on COFF.Rafael Espindola2017-06-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For whatever reason, when processing .globl foo foo: .data bar: .long foo-bar llvm-mc creates a relocation with the section: 0x0 IMAGE_REL_I386_REL32 .text This is different than when the relocation is relative from the beginning. For example, a file with call foo produces 0x0 IMAGE_REL_I386_REL32 foo I would like to refactor the logic for converting "foo - ." into a relative relocation so that it is shared with ELF. This is the first step and just changes the coff implementation to match what ELF (and COFF in the case of calls) does. llvm-svn: 306063
* [WebAssembly] WebAssemblyFastISel getelementptr variable index supportJacob Gravelle2017-06-221-1/+19
| | | | | | | | | | | | | | Summary: Previously -fast-isel getelementptr would constant-fold non-constant i8 load/stores. Reviewers: sunfish Subscribers: jfb, dschuff, sbc100, llvm-commits Differential Revision: https://reviews.llvm.org/D34044 llvm-svn: 306060
* [Hexagon] Properly update kill flags in HexagonNewValueJumpKrzysztof Parzyszek2017-06-221-1/+1
| | | | | | | The feeder instruction will be moved to right before the compare, so the updating code should not be looking for kills past the compare. llvm-svn: 306059
* [ORC] Switch the object layer API from addObjectSet to addObject (singular), andLang Hames2017-06-222-42/+29
| | | | | | | | | move the ObjectCache from the IRCompileLayer to SimpleCompiler. This is the first in a series of patches aimed at cleaning up and improving the robustness and performance of the ORC APIs. llvm-svn: 306058
* [MC] Allow assembling .secidx and .secrel32 for undefined symbolsReid Kleckner2017-06-221-2/+4
| | | | | | | | | | | There's nothing incorrect about emitting such relocations against symbols defined in other objects. The code in EmitCOFFSec* was missing the visitUsedExpr part of MCStreamer::EmitValueImpl, so these symbols were not being registered with the object file assembler. This will be used to make reduced test cases for LLD. llvm-svn: 306057
* [Hexagon] Use LivePhysRegs to fix up kills in HexagonGenMuxKrzysztof Parzyszek2017-06-221-50/+36
| | | | | | Remove the previous, manual shuffling of the kill flags. llvm-svn: 306054
* Simplify WinCOFFObjectWriter::recordRelocation.Rafael Espindola2017-06-221-14/+5
| | | | | | | | | It looks like that when this code was written recordRelocation could be called with A-B where A and B are in the same section. The expression evaluation logic these days makes sure those are folded, so some of this code was dead. llvm-svn: 306053
* [LoopDeletion] Update exits correctly when multiple duplicate edges from an ↵Anna Thomas2017-06-221-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | | exiting block Summary: Currently, we incorrectly update exit blocks of loops when there are multiple edges from a single exiting block to the exit block. This can happen when we have switches as the terminator of the exiting blocks. The fix here is to correctly update the phi nodes in the exit block, and remove all incoming values *except* for one which is from the preheader. Note: Currently, this error can manifest only while deleting non-executed loops. However, it is possible to trigger this error in invariant loops, once we enhance the logic around the exit conditions for the loop check. Reviewers: chandlerc, dberlin, sanjoy, efriedma Reviewed by: efriedma Subscribers: mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D34516 llvm-svn: 306048
* [AVX-512] Remove and autoupgrade the masked integer compare intrinsicsCraig Topper2017-06-222-30/+33
| | | | | | | | | | | | | | | | | Summary: These intrinsics aren't used by clang and haven't been for a while. There's some really terrible codegen in the 32-bit target for avx512bw due to i64 not being legal. But as I said these intrinsics aren't used by clang even before this patch so this codegen reflects our clang behavior today. Reviewers: spatel, RKSimon, zvi, igorb Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34389 llvm-svn: 306047
* [MC] Fix const qualifier warningEkaterina Vaartis2017-06-221-2/+2
| | | | llvm-svn: 306045
* [BasicAA] Add type check and Value equality check around code added in r305481.Craig Topper2017-06-221-5/+8
| | | | | | | | This matches the checks done at the beginning of isKnownNonEqual that this code is partially emulating. Without this we can get assertion failures due to the bit widths of the KnownBits not matching. llvm-svn: 306044
* Fix build break by using llvm::make_unique instead of std::make_unique.Adrian McCarthy2017-06-222-2/+5
| | | | llvm-svn: 306043
* Add IDs and clone methods to NativeRawSymbolAdrian McCarthy2017-06-225-10/+17
| | | | | | | | | | | | All NativeRawSymbols will have a unique symbol ID (retrievable via getSymIndexId). For now, these are initialized to 0, but soon the NativeSession will be responsible for creating the raw symbols, and it will assign unique IDs. The symbol cache in the NativeSession will also require the ability to clone raw symbols, so I've provided implementations for that as well. llvm-svn: 306042
* Make IPDBSession::getGlobalScope a non-const methodAdrian McCarthy2017-06-222-5/+4
| | | | | | | | | | | | There doesn't seem to be a compelling reason why this method should be const other than it was possible with the DIA implementation. The native session is going to act as a symbol factory and cache. This could be acheived with mutable (and the existing const_cast), but it seems cleaner to accept that this method affects the state of the session. This change eliminates an existing const_cast. llvm-svn: 306041
* [x86] add/sub (X==0) --> sbb(neg X)Sanjay Patel2017-06-221-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our handling of select-of-constants is lumpy in IR (https://reviews.llvm.org/D24480), lumpy in DAGCombiner, and lumpy in X86ISelLowering. That's why we only had the 'sbb' codegen in 1 out of the 4 tests. This is a step towards smoothing that out. First, show that all of these IR forms are equivalent: http://rise4fun.com/Alive/mx Second, show that the 'sbb' version is faster/smaller. IACA output for SandyBridge (later Intel and AMD chips are similar based on Agner's tables): This is the "obvious" x86 codegen (what gcc appears to produce currently): | Num Of | Ports pressure in cycles | | | Uops | 0 - DV | 1 | 2 - D | 3 - D | 4 | 5 | | --------------------------------------------------------------------- | 1* | | | | | | | | xor eax, eax | 1 | 1.0 | | | | | | CP | test edi, edi | 1 | | | | | | 1.0 | CP | setnz al | 1 | | 1.0 | | | | | CP | neg eax This is the adc version: | 1* | | | | | | | | xor eax, eax | 1 | 1.0 | | | | | | CP | cmp edi, 0x1 | 2 | | 1.0 | | | | 1.0 | CP | adc eax, 0xffffffff And this is sbb: | 1 | 1.0 | | | | | | | neg edi | 2 | | 1.0 | | | | 1.0 | CP | sbb eax, eax If IACA is trustworthy, then sbb became a single uop in Broadwell, so this will be clearly better than the alternatives going forward. llvm-svn: 306040
* MC: Fix dumping of MCFragment valuesSam Clegg2017-06-221-2/+4
| | | | | | | | | | Without this cast the "char" overload of operator<< is chosen and the values is output as an ascii rather than an integer. Differential Revision: https://reviews.llvm.org/D34486 llvm-svn: 306039
* Updated llvm-objdump symbolic disassembly with x86_64 Mach-O MH_KEXT_BUNDLEKevin Enderby2017-06-221-9/+30
| | | | | | | | | file types so it symbolically disassembles operands using the external relocation entries. rdar://31521343 llvm-svn: 306037
* Add a common error checking for some invalid expressions.Rafael Espindola2017-06-223-9/+14
| | | | | | | This refactors a bit of duplicated code and fixes an assertion failure on ELF. llvm-svn: 306035
* [AMDGPU] Add intrinsics for tbuffer load and store - build error fixDavid Stuttard2017-06-221-2/+1
| | | | | | | Variable was unused in non-debug build (used in assert) causing compile time warning and eventual build failure llvm-svn: 306034
* [AMDGPU] Add intrinsics for tbuffer load and storeDavid Stuttard2017-06-228-121/+535
| | | | | | | | | | | | | | | Intrinsic already existed for llvm.SI.tbuffer.store Needed tbuffer.load and also re-implementing the intrinsic as llvm.amdgcn.tbuffer.* Added CodeGen tests for the 2 new variants added. Left the original llvm.SI.tbuffer.store implementation to avoid issues with existing code Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, tpr Differential Revision: https://reviews.llvm.org/D30687 llvm-svn: 306031
* [InstCombine] Teach foldSelectICmpAndOr to recognize (select (icmp slt ↵Craig Topper2017-06-221-11/+38
| | | | | | | | | | | | | | | | | | | (trunc (X)), 0), Y, (or Y, C2)) Summary: InstCombine likes to turn (icmp eq (and X, C1), 0) into (icmp slt (trunc (X)), 0) sometimes. This breaks foldSelectICmpAndOr's ability to recognize (select (icmp eq (and X, C1), 0), Y, (or Y, C2))->(or (shl (and X, C1), C3), y). This patch tries to recover this. I had to flip around some of the early out checks so that I could create a new And instruction during the compare processing without it possibly never getting used. Reviewers: spatel, majnemer, davide Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34184 llvm-svn: 306029
* [ThinLTO] Remove unnecessary include of Linker.h (NFC)Teresa Johnson2017-06-221-1/+0
| | | | | | | | The ModuleLinker is no longer used by ThinLTO, so this is not needed. Patch by Benoit Belley <Benoit.Belley@autodesk.com> llvm-svn: 306028
* [InstCombine] Add one use checks to or/and->xnor foldingCraig Topper2017-06-221-6/+8
| | | | | | | | | | If the components of the and/or had multiple uses, this transform created an additional instruction. This patch makes sure we remove one of the components. Differential Revision: https://reviews.llvm.org/D34498 llvm-svn: 306027
* [Hexagon] Handle a global operand to A2_addi when creating duplexesKrzysztof Parzyszek2017-06-221-27/+26
| | | | llvm-svn: 306012
* [InstCombine] reverse bitcast + bitwise-logic canonicalization (PR33138)Sanjay Patel2017-06-222-16/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are 2 parts to this patch made simultaneously to avoid a regression. We're reversing the canonicalization that moves bitwise vector ops before bitcasts. We're moving bitwise vector ops *after* bitcasts instead. That's the 1st and 3rd hunks of the patch. The motivation is that there's only one fold that currently depends on the existing canonicalization (see next), but there are many folds that would automatically benefit from the new canonicalization. PR33138 ( https://bugs.llvm.org/show_bug.cgi?id=33138 ) shows why/how we have these patterns in IR. There's an or(and,andn) pattern that requires an adjustment in order to continue matching to 'select' because the bitcast changes position. This match is unfortunately complicated because it requires 4 logic ops with optional bitcast and sext ops. Test diffs: 1. The bitcast.ll and bitcast-bigendian.ll changes show the most basic difference - bitcast comes before logic. 2. There are also tests with no diffs in bitcast.ll that verify that we're still doing folds that were enabled by the previous canonicalization. 3. icmp-xor-signbit.ll shows the payoff. We don't need to adjust existing icmp patterns to look through bitcasts. 4. logical-select.ll contains several tests for the or(and,andn) --> select fold to verify that we are still handling those cases. The lone diff shows the movement of the bitcast from the new canonicalization rule. Differential Revision: https://reviews.llvm.org/D33517 llvm-svn: 306011
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