summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* [SystemZ] Define the GR64 low-word logic instructions as pseudo aliases.Richard Sandiford2013-09-258-111/+160
| | | | | | | | Another patch to avoid duplication of encoding information. Things like NILF, NILL and NILH are used as both 32-bit and 64-bit instructions. Here the 64-bit versions are defined as aliases of the 32-bit ones. llvm-svn: 191369
* MC: Add support for treating $ as a reference to the PCDavid Majnemer2013-09-253-3/+16
| | | | | | | | | | | | | | | | | The binutils assembler supports a mode called DOLLAR_DOT which treats the dollar sign token as a reference to the current program counter if the dollar sign doesn't precede a constant or identifier. This commit adds a new MCAsmInfo flag stating whether or not a given target supports this interpretation of the dollar sign token; by default, this flag is not enabled. Further, enable this flag for PPC. The system assembler for AIX and binutils both support using the dollar sign in this manner. This fixes PR17353. llvm-svn: 191368
* [SystemZ] Define the call instructions as pseudo aliases.Richard Sandiford2013-09-259-147/+97
| | | | | | | | Similar to r191364, but for calls. This patch also removes the shortening of BRASL to BRAS within a TU. Doing that was a bit controversial internally, since there's a strong expectation with the z assembler that WYWIWYG. llvm-svn: 191366
* [SystemZ] Use subregs for 64-bit truncating storesRichard Sandiford2013-09-254-41/+70
| | | | | | | | Another patch to reduce the duplication of encoding information. Rather than define separate patterns for truncating 64-bit stores, use the 32-bit stores with a subreg. No behavioral changed intended. llvm-svn: 191365
* [SystemZ] Define the return instruction as a pseudo alias of BRRichard Sandiford2013-09-253-8/+23
| | | | | | | | This is the first of a few patches to reduce the dupliation of encoding information. The return instruction is a normal BR in which one of the registers is fixed. llvm-svn: 191364
* [SystemZ] Add instruction-shortening passRichard Sandiford2013-09-258-8/+193
| | | | | | | | | | | | | | | | | | | | | When loading immediates into a GR32, the port prefered LHI, followed by LLILH or LLILL, followed by IILF. LHI and IILF are natural 32-bit operations, but LLILH and LLILL also clear the upper 32 bits of the register. This was represented as taking a 32-bit subreg of a 64-bit assignment. Using subregs for something as simple as a move immediate was probably a bad idea. Also, I have patches to add support for the high-word facility, and we don't want something like LLILH and LLILL to stop the high word of the same GPR from being used. This patch therefore uses LHI and IILF to begin with and adds a late machine-specific pass to use LLILH and LLILL if the other half of the register is not live. The high-word patches extend this behavior to IIHF, LLIHL and LLIHH. No behavioral change intended. llvm-svn: 191363
* MC: Remove vestigial PCSymbol field from AsmInfoDavid Majnemer2013-09-256-9/+0
| | | | llvm-svn: 191362
* [msan] Fix -Wreturn-type warnings in non-self-hosted build.Evgeniy Stepanov2013-09-251-0/+2
| | | | llvm-svn: 191361
* Revert r191350.Akira Hatanaka2013-09-253-94/+55
| | | | llvm-svn: 191353
* [mips] Move public functions to the beginning of the class definition.Akira Hatanaka2013-09-251-33/+33
| | | | | | No intended functionality change. llvm-svn: 191352
* [mips] Define getTargetNode as a template function.Akira Hatanaka2013-09-253-55/+94
| | | | | | No intended functionality change. llvm-svn: 191350
* [PR16882] Ignore noreturn definitions when setting isPhysRegUsed.Quentin Colombet2013-09-251-3/+39
| | | | | | | | | | | | | | | | | PEI inserts a save/restore sequence for the link register, according to the information it gets from the MachineRegisterInfo. MachineRegisterInfo is populated by the VirtRegMap pass. This pass was not aware of noreturn calls and was registering the definitions of these calls the same way as regular operations. Modify VirtRegPass so that it does not set the isPhysRegUsed information for registers only defined by noreturn calls. The rational is that a noreturn call is the "last instruction" of the program (if it returns the behavior is undefined), so everything that is defined by it cannot be used and will not interfere with anything else. Therefore, it is pointless to account for then. llvm-svn: 191349
* CriticalAntiDepBreaker is no longer needed for armv7 scheduling.Andrew Trick2013-09-251-3/+1
| | | | | | | | | | | | | | | | | This is being disabled because it is no longer needed for performance. It is only used by postRAscheduler which is also planned for removal, and it is implemented with an out-dated view of register liveness. It consideres aliases instead of register units, assumes valid kill flags, and assumes implicit uses on partial register defs. Kill flags and implicit operands are error prone and impossible to verify. We should gradually eliminate dependence on them in the postRA phases. Targets that still benefit from this should move to the MI scheduler. If that doesn't solve the problem, then we should add a hook to regalloc to optimize reload placement. llvm-svn: 191348
* MachO: Improve backend diagnostic for overalignment.Jim Grosbach2013-09-241-1/+2
| | | | | | Give the symbol's name and disengage the enchanced crash reporting. llvm-svn: 191344
* Move LTO support library to a component, allowing it to be testedPeter Collingbourne2013-09-248-2/+1397
| | | | | | more reliably across platforms. Patch by Tom Roeder! llvm-svn: 191343
* Add missing check to SETCC optimization.Eli Friedman2013-09-241-0/+1
| | | | | | PR17338. llvm-svn: 191337
* llvm-dwarfdump: add missing opening quotation mark lost in r191330David Blaikie2013-09-241-1/+1
| | | | llvm-svn: 191333
* llvm-dwarfdump: re-add field formatting for the entry kind lost in r191329David Blaikie2013-09-241-1/+1
| | | | | | CR feedback from Eric Christopher llvm-svn: 191330
* llvm-dwarfdump support for gnu_pubtypesDavid Blaikie2013-09-242-20/+33
| | | | llvm-svn: 191329
* Adding a feature flag to the llvm backend for x86 TBM instruction set.Yunzhong Gao2013-09-243-1/+13
| | | | | | | | | | Adding TBM feature to bdver2 processor; piledriver supports this instruction set according to the following document: http://developer.amd.com/wordpress/media/2012/10/New-Bulldozer-and-Piledriver-Instructions.pdf Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1692 llvm-svn: 191324
* MemoryBuiltins: Remove posix_memalign from the list and replace it with a TODO.Benjamin Kramer2013-09-241-1/+1
| | | | | | | This code isn't ready to deal with allocation functions where the return is not the allocated pointer. The checks below will reject posix_memalign anyways. llvm-svn: 191319
* Make the size and expr arguments of .fill directive optional.Roman Divacky2013-09-241-16/+21
| | | | llvm-svn: 191318
* MemoryBuiltins: Reinstate optimizing (uninitialized) loads from operator new.Benjamin Kramer2013-09-241-7/+7
| | | | llvm-svn: 191315
* set the cost of tiny trees to INT_MAX in SLP vectorizer to disable ↵Yi Jiang2013-09-241-1/+1
| | | | | | vectorization on them llvm-svn: 191314
* MemoryBuiltins: Fix operator new bits.Benjamin Kramer2013-09-241-3/+3
| | | | | | We really don't want to optimize malloc return value checks away. llvm-svn: 191313
* Comment typo.Andrew Trick2013-09-241-1/+1
| | | | llvm-svn: 191312
* Teach MemoryBuiltins and InstructionSimplify that operator new never returns ↵Benjamin Kramer2013-09-243-6/+20
| | | | | | | | | | | | NULL. This is safe per C++11 18.6.1.1p3: [operator new returns] a non-null pointer to suitably aligned storage (3.7.4), or else throw a bad_alloc exception. This requirement is binding on a replacement version of this function. Brings us a tiny bit closer to eliminating more vector push_backs. llvm-svn: 191310
* Push analysis passes to InstSimplify when they're around anyways.Benjamin Kramer2013-09-243-3/+4
| | | | llvm-svn: 191309
* [mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. ↵Daniel Sanders2013-09-244-8/+84
| | | | | | not intrinsics) llvm-svn: 191306
* [mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal ↵Daniel Sanders2013-09-244-19/+190
| | | | | | IR (i.e. not intrinsics) llvm-svn: 191304
* DAGCombiner: Unify rotate matching for extended and unextended amounts.Benjamin Kramer2013-09-241-79/+57
| | | | | | No functionality change, lots of indentation changes. llvm-svn: 191303
* [mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-246-3/+98
| | | | llvm-svn: 191302
* [mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-245-4/+106
| | | | llvm-svn: 191301
* [mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching ↵Daniel Sanders2013-09-248-247/+656
| | | | | | | | | | | | | | | | | | | | | | | | | | | BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
* [mips][msa] Non-constant BUILD_VECTOR's should be expanded to ↵Daniel Sanders2013-09-241-0/+17
| | | | | | | | INSERT_VECTOR_ELT instead of memory operations. The resulting code is the same length, but doesnt cause memory traffic or latency. llvm-svn: 191297
* [mips][msa] Added partial support for matching fmax_a from normal IR (i.e. ↵Daniel Sanders2013-09-242-0/+15
| | | | | | | | not intrinsics) This covers the case where fmax_a can be used to implement ISD::FABS. llvm-svn: 191296
* [mips][msa] Line wrapping.Daniel Sanders2013-09-241-4/+4
| | | | | | No functional change. llvm-svn: 191295
* [mips][msa] Added support for matching andi, ori, nori, and xori from normal ↵Daniel Sanders2013-09-242-10/+37
| | | | | | IR (i.e. not intrinsics) llvm-svn: 191293
* [mips][msa] Added support for matching max, maxi, min, mini from normal IR ↵Daniel Sanders2013-09-244-67/+158
| | | | | | (i.e. not intrinsics) llvm-svn: 191291
* [mips][msa] Added support for matching bsel and bseli from normal IR (i.e. ↵Daniel Sanders2013-09-242-2/+44
| | | | | | | | not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. llvm-svn: 191290
* [msan] Handling of atomic load/store, atomic rmw, cmpxchg.Evgeniy Stepanov2013-09-241-2/+96
| | | | llvm-svn: 191287
* [mips][msa] Added support for matching comparisons from normal IR (i.e. not ↵Daniel Sanders2013-09-244-73/+281
| | | | | | | | | intrinsics) MIPS SelectionDAG changes: * Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask. llvm-svn: 191286
* [mips][msa] Added support for matching slli, srai, and srli from normal IR ↵Daniel Sanders2013-09-242-20/+90
| | | | | | (i.e. not intrinsics) llvm-svn: 191285
* Followup to r191252.Bill Wendling2013-09-241-113/+127
| | | | | | | | | | Make sure that the code that handles the constant addresses is run for the GEPs. This just refactors that code and then calls it for the GEPs that are collected during the iteration. <rdar://problem/12445434> llvm-svn: 191281
* DWARFTypeUnit::dump(): Use PRIx64 to format uint64_t.NAKAMURA Takumi2013-09-241-1/+1
| | | | llvm-svn: 191266
* Initial support for Neon scalar instructions.Jiangning Liu2013-09-249-49/+285
| | | | | | | | | | Patch by Ana Pazos. 1.Added support for v1ix and v1fx types. 2.Added Scalar Pairwise Reduce instructions. 3.Added initial implementation of Scalar Arithmetic instructions. llvm-svn: 191263
* [stackprotector] Allow for copies from vreg -> vreg to be in a terminator ↵Michael Gottesman2013-09-241-6/+26
| | | | | | | | | | | sequence. Sometimes a copy from a vreg -> vreg sneaks into the middle of a terminator sequence. It is safe to slice this into the stack protector success bb. This fixes PR16979. llvm-svn: 191260
* Misc fixes for cpp backend.Eli Friedman2013-09-241-3/+16
| | | | | | PR17317. llvm-svn: 191258
* Add namespaces to the list of items that we expose via pubnames.Eric Christopher2013-09-241-0/+1
| | | | llvm-svn: 191257
* Format the index entry kind string to align.Eric Christopher2013-09-241-3/+3
| | | | llvm-svn: 191255
OpenPOWER on IntegriCloud