summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* [Orc] Add a comment about member variable dependencies to OrcMCJITReplacement.Lang Hames2017-08-311-0/+3
| | | | | | | | | The comment explains the reason behind the change in member variable order in r312086. Thanks to Philip Reames for the suggestion. llvm-svn: 312205
* Revert "Revert r312139 "Verifier: Verify the correctness of fragment ↵Adrian Prantl2017-08-311-8/+22
| | | | | | | | expressions attached to globals."" This reverts commit r312182 after fixing PR34390. llvm-svn: 312197
* Don't add a fragment expression when GlobalSRA splits up a single-member structAdrian Prantl2017-08-311-9/+12
| | | | | | | | Fixes PR34390. https://bugs.llvm.org/show_bug.cgi?id=34390 llvm-svn: 312196
* [MachineOutliner] Add missed optimization remarks for the outliner.Jessica Paquette2017-08-301-1/+36
| | | | | | | | | | | | | | This adds missed optimization remarks which report viable candidates that were not outlined because they would increase code size. Other remarks will come in separate commits. This will help to diagnose code size regressions and changes in outliner behaviour in projects using the outliner. https://reviews.llvm.org/D37085 llvm-svn: 312194
* [yaml2obj][ELF] Make symbols optional for relocationsPetr Hosek2017-08-301-1/+1
| | | | | | | | | | | | | | | | Some kinds of relocations do not have symbols, like R_X86_64_RELATIVE for instance. I would like to test this case in D36554 but currently can't because symbols are required by yaml2obj. The other option is using the empty symbol but that doesn't seem quite right to me. This change makes the Symbol field of Relocation optional and in the case where the user does not specify a symbol name the Symbol index is 0. Patch by Jake Ehrlich Differential Revision: https://reviews.llvm.org/D37276 llvm-svn: 312192
* [X86] Remove some code from fast isel that is no longer needed with i1 being ↵Craig Topper2017-08-301-31/+0
| | | | | | an illegal type. llvm-svn: 312190
* [SanitizeCoverage] Enable stack-depth coverage for -fsanitize=fuzzerMatt Morehouse2017-08-301-9/+21
| | | | | | | | | | | | | | | | | | Summary: - Don't sanitize __sancov_lowest_stack. - Don't instrument leaf functions. - Add CoverageStackDepth to Fuzzer and FuzzerNoLink. - Only enable on Linux. Reviewers: vitalybuka, kcc, george.karpenkov Reviewed By: kcc Subscribers: kubamracek, cfe-commits, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D37156 llvm-svn: 312185
* Revert r312139 "Verifier: Verify the correctness of fragment expressions ↵Hans Wennborg2017-08-301-22/+8
| | | | | | | | attached to globals." This caused PR34390. llvm-svn: 312182
* [ARM] Replace fixed-size SmallSet with a bitset.Benjamin Kramer2017-08-301-30/+30
| | | | | | It's smaller. No functionality change. llvm-svn: 312180
* AMDGPU: Correct operand types for v_mad_mix*Matt Arsenault2017-08-304-13/+37
| | | | | | | | | | | | These aren't really packed instructions, so the default op_sel_hi should be 0 since this indicates a conversion. The operand types are scalar values that behave similar to an f16 scalar that may be converted to f32. Doesn't change the default printing for op_sel_hi, just the parsing. llvm-svn: 312179
* Revert r312154 "Re-enable "[MachineCopyPropagation] Extend pass to do COPY ↵Hans Wennborg2017-08-303-577/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | source forwarding"" It caused PR34387: Assertion failed: (RegNo < NumRegs && "Attempting to access record for invalid register number!") > Issues identified by buildbots addressed since original review: > - Fixed ARMLoadStoreOptimizer bug exposed by this change in r311907. > - The pass no longer forwards COPYs to physical register uses, since > doing so can break code that implicitly relies on the physical > register number of the use. > - The pass no longer forwards COPYs to undef uses, since doing so > can break the machine verifier by creating LiveRanges that don't > end on a use (since the undef operand is not considered a use). > > [MachineCopyPropagation] Extend pass to do COPY source forwarding > > This change extends MachineCopyPropagation to do COPY source forwarding. > > This change also extends the MachineCopyPropagation pass to be able to > be run during register allocation, after physical registers have been > assigned, but before the virtual registers have been re-written, which > allows it to remove virtual register COPY LiveIntervals that become dead > through the forwarding of all of their uses. llvm-svn: 312178
* Simplify writeArchive return type.Rui Ueyama2017-08-303-17/+13
| | | | | | | | | | writeArchive returned a pair, but the first element of the pair is always its first argument on failure, so it doesn't make sense to return it from the function. This patch change the return type so that it does't return it. Differential Revision: https://reviews.llvm.org/D37313 llvm-svn: 312177
* SelectionDAG: Emit correct debug info for multi-register function arguments.Adrian Prantl2017-08-301-0/+21
| | | | | | | | | Previously we would just describe the first register and then call it quits. This patch emits fragment expressions for each register. <rdar://problem/34075307> llvm-svn: 312169
* [IR] Don't print "!DIExpression() = !DIExpression()" when dumpingReid Kleckner2017-08-301-1/+1
| | | | | | | | | Now that we print DIExpressions inline everywhere, we don't need to print them once as an operand and again as a value. This is only really visible when calling dump() or print() directly on a DIExpression during debugging. llvm-svn: 312168
* Refactor DIBuilder::createFragmentExpression into a static DIExpression memberAdrian Prantl2017-08-305-43/+46
| | | | | | NFC llvm-svn: 312165
* [ARM] Use Swift error registers on non-Darwin targetsBrian Gesiak2017-08-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Remove a check for `ARMSubtarget::isTargetDarwin` when determining whether to use Swift error registers, so that Swift errors work properly on non-Darwin ARM32 targets (specifically Android). Before this patch, generated code would save and restores ARM register r8 at the entry and returns of a function that throws. As r8 is used as a virtual return value for the object being thrown, this gets overwritten by the restore, and calling code is unable to catch the error. In turn this caused Swift code that used `do`/`try`/`catch` to work improperly on Android ARM32 targets. Addresses Swift bug report https://bugs.swift.org/browse/SR-5438. Patch by John Holdsworth. Reviewers: manmanren, rjmccall, aschwaighofer Reviewed By: aschwaighofer Subscribers: srhines, aschwaighofer, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D35835 llvm-svn: 312164
* NewGVN: Make sure we add the correct user if we swapped the comparison operandsDaniel Berlin2017-08-301-2/+4
| | | | llvm-svn: 312162
* NewGVN: Allow simplification into variablesDaniel Berlin2017-08-301-22/+21
| | | | llvm-svn: 312161
* [GISel]: Add a clean up combiner during legalization.Aditya Nandakumar2017-08-301-101/+60
| | | | | | | | | | | Added a combiner which can clean up truncs/extends that are created in order to make the types work during legalization. Also moved the combineMerges to the LegalizeCombiner. https://reviews.llvm.org/D36880 llvm-svn: 312158
* [GVNSink] Remove dependency on SmallPtrSet iteration order.Benjamin Kramer2017-08-301-0/+2
| | | | | | Found by LLVM_ENABLE_REVERSE_ITERATION. llvm-svn: 312156
* Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"Geoff Berry2017-08-303-23/+577
| | | | | | | | | | | | | | | | | | | | | | | Issues identified by buildbots addressed since original review: - Fixed ARMLoadStoreOptimizer bug exposed by this change in r311907. - The pass no longer forwards COPYs to physical register uses, since doing so can break code that implicitly relies on the physical register number of the use. - The pass no longer forwards COPYs to undef uses, since doing so can break the machine verifier by creating LiveRanges that don't end on a use (since the undef operand is not considered a use). [MachineCopyPropagation] Extend pass to do COPY source forwarding This change extends MachineCopyPropagation to do COPY source forwarding. This change also extends the MachineCopyPropagation pass to be able to be run during register allocation, after physical registers have been assigned, but before the virtual registers have been re-written, which allows it to remove virtual register COPY LiveIntervals that become dead through the forwarding of all of their uses. llvm-svn: 312154
* [X86] Remove unneed AVX512 check from fast isel.Craig Topper2017-08-301-2/+1
| | | | | | This is no longer necessary now that i1 is illegal. llvm-svn: 312146
* [WebAssembly] Add target feature for atomicsDerek Schuff2017-08-309-11/+31
| | | | | | | | | | Summary: This tracks the WebAssembly threads feature proposal at https://github.com/WebAssembly/threads/blob/master/proposals/threads/Overview.md Differential Revision: https://reviews.llvm.org/D37300 llvm-svn: 312145
* Canonicalize the representation of empty an expression in ↵Adrian Prantl2017-08-303-10/+16
| | | | | | | | | | | | | | | | DIGlobalVariableExpression This change simplifies code that has to deal with DIGlobalVariableExpression and mirrors how we treat DIExpressions in debug info intrinsics. Before this change there were two ways of representing empty expressions on globals, a nullptr and an empty !DIExpression(). If someone needs to upgrade out-of-tree testcases: perl -pi -e 's/(!DIGlobalVariableExpression\(var: ![0-9]*)\)/\1, expr: !DIExpression())/g' <MYTEST.ll> will catch 95%. llvm-svn: 312144
* [codeview] make DbgVariableLocation::extractFromMachineInstruction use OptionalBob Haarman2017-08-303-29/+31
| | | | | | | | | | | | | | | | Summary: DbgVariableLocation::extractFromMachineInstruction originally returned a boolean indicating success. This change makes it return an Optional<DbgVariableLocation> so we cannot try to access the fields of the struct if they aren't valid. Reviewers: aprantl, rnk, zturner Subscribers: llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D37279 llvm-svn: 312143
* Verifier: Verify the correctness of fragment expressions attached to globals.Adrian Prantl2017-08-301-8/+22
| | | | llvm-svn: 312139
* [AVX512] Don't use 32-bit elements version of AND/OR/XOR/ANDN during isel ↵Craig Topper2017-08-301-32/+34
| | | | | | | | | | | | unless we're matching a masked op or broadcast Selecting 32-bit element logical ops without a select or broadcast requires matching a bitconvert on the inputs to the and. But that's a weird thing to rely on. It's entirely possible that one of the inputs doesn't have a bitcast and one does. Since there's no functional difference, just remove the extra patterns and save some isel table size. Differential Revision: https://reviews.llvm.org/D36854 llvm-svn: 312138
* [GlobalISel][X86] Support variadic function call.Igor Breger2017-08-301-4/+26
| | | | | | | | | | | | | | Summary: Support variadic function call. Port the implementation from X86FastISel. Reviewers: zvi, guyblank, oren_ben_simhon Reviewed By: guyblank Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D37261 llvm-svn: 312130
* Re-land MachineInstr: Reason locally about some memory objects before going ↵Balaram Makam2017-08-301-17/+43
| | | | | | | | | | | | | | | | | | | | to AA. Summary: Reverts r311008 to reinstate r310825 with a fix. Refine alias checking for pseudo vs value to be conservative. This fixes the original failure in builtbot unittest SingleSource/UnitTests/2003-07-09-SignedArgs. Reviewers: hfinkel, nemanjai, efriedma Reviewed By: efriedma Subscribers: bjope, mcrosier, nhaehnle, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D36900 llvm-svn: 312126
* [InstCombine] remove unnecessary vector select fold; NFCISanjay Patel2017-08-301-4/+0
| | | | | | | | | | This code is double-dead: 1. We simplify all selects with constant true/false condition in InstSimplify. I've minimized/moved the tests to show that works as expected. 2. All remaining vector selects with a constant condition are canonicalized to shufflevector, so we really can't see this pattern. llvm-svn: 312123
* fix more typos; NFCSanjay Patel2017-08-301-2/+2
| | | | llvm-svn: 312120
* fix typos; NFCSanjay Patel2017-08-301-15/+15
| | | | llvm-svn: 312119
* [MIPS] Add support to match more patterns for BBIT instructionStrahinja Petrovic2017-08-301-0/+15
| | | | | | | | | | This patch supports one more pattern for bbit0 and bbit1 instructions, CBranchBitNum class is expanded so it can take 32 bit immidate. Differential Revision: https://reviews.llvm.org/D36222 llvm-svn: 312111
* [InstCombine] Fold insert sequence if first ins has multiple users.Florian Hahn2017-08-301-6/+18
| | | | | | | | | | | | | | | | | | | | | | | Summary: If the first insertelement instruction has multiple users and inserts at position 0, we can re-use this instruction when folding a chain of insertelement instructions. As we need to generate the first insertelement instruction anyways, this should be a strict improvement. We could get rid of the restriction of inserting at position 0 by creating a different shufflemask, but it is probably worth to keep the first insertelement instruction with position 0, as this is easier to do efficiently than at other positions I think. Reviewers: grosser, mkuper, fpetrogalli, efriedma Reviewed By: fpetrogalli Subscribers: gareevroman, llvm-commits Differential Revision: https://reviews.llvm.org/D37064 llvm-svn: 312110
* [AArch64] allow v4f16 types when FullFP16 is supportedSjoerd Meijer2017-08-301-57/+53
| | | | | | | | | | Support for scalars was committed in r311154, this adds support for allowing v4f16 vector types (thus avoiding conversions from/to single precision for these types). Differential Revision: https://reviews.llvm.org/D37145 llvm-svn: 312104
* [AVX512] Correct isel patterns to support selecting masked ↵Craig Topper2017-08-302-33/+59
| | | | | | | | | | | | | | | | | | | | | | | vbroadcastf32x2/vbroadcasti32x2 Summary: This patch adjusts the patterns to make the result type of the broadcast node vXf64/vXi64. Then adds a bitcast to vXi32 after that. Intrinsic lowering was also adjusted to generate this new pattern. Fixes PR34357 We should probably just drop the intrinsic entirely and use native IR, but I'll leave that for a future patch. Any idea what instruction we should be lowering the floating point 128-bit result version of this pattern to? There's a 128-bit v2i32 integer broadcast but not an fp one. Reviewers: aymanmus, zvi, igorb Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37286 llvm-svn: 312101
* [AVX512] Use 256-bit extract instructions for extracting bits [255:128] from ↵Craig Topper2017-08-301-0/+58
| | | | | | | | | | a 512-bit register This enables the use of a smaller encoding by using a VEX instruction when possible. Differential Revision: https://reviews.llvm.org/D37092 llvm-svn: 312100
* [X86] Apply SlowIncDec feature to Sandybridge/Ivybridge CPUs as wellCraig Topper2017-08-301-2/+2
| | | | | | | | Currently we start applying this on Haswell and newer. I don't believe anything changed in the Haswell architecture to make this the right cutoff point. The partial flag handling around this has been roughly the same since Sandybridge. Differential Revision: https://reviews.llvm.org/D37250 llvm-svn: 312099
* [cfi] Fixed non-determinism in codegen due to DenseSet iteration orderMandeep Singh Grang2017-08-301-2/+2
| | | | llvm-svn: 312098
* [X86] Provide a separate feature bit for macro fusion support instead of ↵Craig Topper2017-08-304-14/+35
| | | | | | | | | | | | | | | | | | | | | basing it on the AVX flag Summary: Currently we determine if macro fusion is supported based on the AVX flag as a proxy for the processor being Sandy Bridge". This is really strange as now AMD supports AVX. It also means if user explicitly disables AVX we disable macro fusion. This patch adds an explicit macro fusion feature. I've also enabled for the generic 64-bit CPU (which doesn't have AVX) This is probably another candidate for being in the MI layer, but for now I at least wanted to correct the overloading of the AVX feature. Reviewers: spatel, chandlerc, RKSimon, zvi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37280 llvm-svn: 312097
* AMDGPU: Don't look for DS merge candidates with one use addressMatt Arsenault2017-08-301-3/+10
| | | | | | | | | | | | | The merge is only possible if the base address register is the same for the two instructions. If there is only the one use, there's no point in doing an expensive forward scan checking for memory interference looking for a merge candidate. This gives a signficant improvement in one extreme testcase. The code to do the scan is still algorithmically terrible, so this is still the slowest pass in that example. llvm-svn: 312096
* [AMDGPU] Use v_max_f* for fcanonicalizeStanislav Mekhanoshin2017-08-302-3/+33
| | | | | | | | | | If denorms are not flushed we can use max instead of multiplication by 1. For double that is simply faster, while for float and half it is shorter, because mul uses constant bus and VOP3. Differential Revision: https://reviews.llvm.org/D36856 llvm-svn: 312095
* AMDGPU: Select clamp pattern with v2f16Matt Arsenault2017-08-302-15/+36
| | | | llvm-svn: 312087
* [Orc] Fix member variable ordering issue in OrcMCJITReplacement.Lang Hames2017-08-301-2/+3
| | | | | | | | | | | | | | | | https://reviews.llvm.org/D36888 From that review description: When an OrcMCJITReplacement object gets destructed, LazyEmitLayer may still contain a shared_ptr of a module, which requires ShouldDelete in the deleter. But ShouldDelete gets destructed before LazyEmitLayer due to the order of declaration in OrcMCJITReplacement, which leads to a crash, when the destructor of LazyEmitLayer is executed. Changing the order of declaration fixes this. Patch by Moritz Kroll. Thanks Moritz! llvm-svn: 312086
* [X86] Finish the subtarget and predicate implementation of CLWB.Craig Topper2017-08-292-0/+5
| | | | | | We don't have an intrinsic implemented for this instruction yet, but it looked odd that we were missing the accessor method from the subtarget. llvm-svn: 312064
* [codeview] add missing break in CodeGen/AsmPrinter/DebugHandlerBase.cppBob Haarman2017-08-291-0/+1
| | | | llvm-svn: 312055
* [cfi] Avoid branch veneers in jump tables when possible.Evgeniy Stepanov2017-08-291-8/+56
| | | | | | | | | | | | | | | | | | | Summary: When jumptable encoding does not match target code encoding (arm vs thumb), a veneer is inserted by the linker. We can not avoid this in all cases, because entries within one jumptable must have the same encoding, but we can make it less common by selecting the jumptable encoding to match the majority of its targets. This change only covers FullLTO, and not ThinLTO. Reviewers: pcc Subscribers: aemerson, mehdi_amini, javed.absar, kristof.beyls, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D37171 llvm-svn: 312054
* [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-08-298-180/+332
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 312053
* [cfi] Build __cfi_check as Thumb when applicable.Evgeniy Stepanov2017-08-291-0/+6
| | | | | | | | | | | | | | Summary: Cross-DSO CFI needs all __cfi_check exports to use the same encoding (ARM vs Thumb). Reviewers: pcc Subscribers: aemerson, srhines, kristof.beyls, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D37243 llvm-svn: 312052
* Revert "[SanitizeCoverage] Enable stack-depth coverage for -fsanitize=fuzzer"Matt Morehouse2017-08-291-21/+9
| | | | | | This reverts r312026 due to bot breakage. llvm-svn: 312047
OpenPOWER on IntegriCloud