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* [AMDGPU] Insert nop pass: take care of outstanding feedbackKonstantin Zhuravlyov2016-04-222-21/+18
| | | | | | | | | | | - Switch few loops to range-based for loops - Fix nop insertion at the end of BB - Fix formatting - Check for endpgm Differential Revision: http://reviews.llvm.org/D19380 llvm-svn: 267167
* [mips][microMIPS] Revert commit r266861.Zoran Jovanovic2016-04-2210-170/+8
| | | | | | Commit r266861 was the reason for failing tests in LLVM test suite. llvm-svn: 267166
* [Hexagon] Teach mux expansion how to deal with undef predicatesKrzysztof Parzyszek2016-04-221-5/+13
| | | | llvm-svn: 267165
* [Hexagon] Add definitions for trap/pause instructionsKrzysztof Parzyszek2016-04-221-0/+21
| | | | | | Also add tests for other instructions from HexagonSystemInst.td. llvm-svn: 267162
* PostRAHazardRecocgnizer: Fix unused-private-field warningTom Stellard2016-04-221-1/+0
| | | | llvm-svn: 267160
* [MemorySSA] Fix bug in CachingMemorySSAWalker::invalidateInfoGeoff Berry2016-04-221-11/+20
| | | | | | | | | | | | | | | | | | | | | Summary: CachingMemorySSAWalker::invalidateInfo was using IsCall to determine which cache map needed to be cleared of entries referring to the invalidated MemoryAccess, but there could also be entries referring to it in the other cache map (value entries, not key entries). This change just clears both tables to be conservatively correct. Also add a verifyRemoved() function, called when expensive checks (i.e. XDEBUG) are enabled to verify that the invalidated MemoryAccess object is not referenced in any of the caches. Reviewers: dberlin, george.burgess.iv Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D19388 llvm-svn: 267157
* CodeGen: Add a stand-alone hazard recognizer passTom Stellard2016-04-223-0/+103
| | | | | | | | | | | | | | | | Summary: This new pass allows targets to use the hazard recognizer without having to also run one of the schedulers. This is useful when compiling with optimizations disabled for targets that still need noop hazards to be handled correctly. Reviewers: hfinkel, atrick Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18594 llvm-svn: 267156
* [EarlyCSE] Don't add the overflow flags to the hashDavid Majnemer2016-04-221-9/+0
| | | | | | | | We take the intersection of overflow flags while CSE'ing. This permits us to consider two instructions with different overflow behavior to be replaceable. llvm-svn: 267153
* Emit code16 in assembly in 16-bit modeNirav Dave2016-04-221-0/+6
| | | | | | | | | | | | | | | Summary: When generating assembly using -m16 we must explicitly mark it as 16-bit. Emit .code16 at beginning of file. Fixes wrong results when using -fno-integrated-as. Reviewers: dwmw2 Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19392 llvm-svn: 267152
* [mips] Fix select patterns for MIPS64Simon Dardis2016-04-221-1/+1
| | | | | | | | | | | | | | When targetting MIPS64R6 some of the patterns for select were guarded by a broken predicate. The predicate was supposed to test if a constant value could fit in a 16 bit zero-extended field. Instead the value was tested to fit in a 16 bit sign-extended field. For negative constants of native word width this resulted in wrong code generation. Reviewers: vkalintiris, dsanders Differential Review: http://reviews.llvm.org/D19378 llvm-svn: 267151
* [mips] Fix a small typo that would leave BLTZC out of getAnalyzableBrOpc().'Vasileios Kalintiris2016-04-221-1/+1
| | | | llvm-svn: 267149
* Revert r267049, r26706[16789], r267071 - Refactor raw pdb dumper into libraryDaniel Sanders2016-04-225-468/+3
| | | | | | r267049 broke multiple buildbots (e.g. clang-cmake-mips, and clang-x86_64-linux-selfhost-modules) which the follow-ups have not yet resolved and this is preventing subsequent committers from being notified about additional failures on the affected buildbots. llvm-svn: 267148
* [InstCombine] Preserve fast math flags when combining PHIsSilviu Baranga2016-04-221-38/+11
| | | | | | | | | | | | | | | | | | | | Summary: When optimizing PHIs which have inputs floating point binary operators, we preserve all IR flags except the fast math flags. This change removes the logic which tracked some of the IR flags (no wrap, exact) and replaces it by doing an and on the IR flags of all inputs to the PHI - which will also handle the fast math flags. Reviewers: majnemer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19370 llvm-svn: 267139
* [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructionsHrvoje Varga2016-04-224-3/+14
| | | | | | Differential Revision: http://reviews.llvm.org/D19354 llvm-svn: 267137
* [mips][microMIPS] Add R_MICROMIPS_PC18_S3 relocationZoran Jovanovic2016-04-224-2/+23
| | | | | | Differential Revision: http://reviews.llvm.org/D15026 llvm-svn: 267130
* Fix -Wunused-variable in non-asserts build.Eric Liu2016-04-221-0/+1
| | | | llvm-svn: 267128
* Revert r267098 - [MachineCombiner] Support for floating-point FMA on ARM64Daniel Sanders2016-04-227-584/+39
| | | | | | It introduced buildbot failures on clang-cmake-mips, clang-ppc64le-linux, among others. llvm-svn: 267127
* [X86]: Changing cost for “TRUNCATE v16i32 to v16i8” in SSE4.1 mode.Ashutosh Nema2016-04-221-2/+0
| | | | | | | | | | | | | | Summary: rL256194 transforms truncations between vectors of integers into PACKUS/PACKSS operations during DAG combine. This generates better code for truncate, so cost of truncate needs to be changed but looks like it got changed only in SSE2 table Whereas this change is also applicable for SSE4.1, so the cost of truncate needs to be changed for that as well. Cost of “TRUNCATE v16i32 to v16i8” & “TRUNCATE v16i16 to v16i8” should be same in SSE4.1 & SSE2 table. Removing their cost from SSE4.1, so it will fall back to SSE2. Reviewers: Simon Pilgrim llvm-svn: 267123
* [Sparc] This provides support for itineraries on Sparc.Chris Dewhurst2016-04-225-159/+417
| | | | | | | | | | | | Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future. The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this. As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary. Phabricator Review: http://reviews.llvm.org/D19359 llvm-svn: 267121
* The following code would not work before this patch, due to the inability to ↵Chris Dewhurst2016-04-221-1/+1
| | | | | | | | | | | | | | | | | | | | | take the address of a global object: void func1() { ... } int main(int argc, char** argv) { void (*pFunc)(); pFunc = &func1 pFunc(); ... } Phabricator review: http://reviews.llvm.org/D19368 llvm-svn: 267120
* Revert "Initial implementation of optimization bisect support."Vedant Kumar2016-04-2289-435/+69
| | | | | | | | This reverts commit r267022, due to an ASan failure: http://lab.llvm.org:8080/green/job/clang-stage2-cmake-RgSan_check/1549 llvm-svn: 267115
* [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructionsZlatko Buljan2016-04-223-1/+60
| | | | | | Differential Revision: http://reviews.llvm.org/D18687 llvm-svn: 267114
* [GVN] Respect fast-math-flags on fcmpsDavid Majnemer2016-04-222-32/+40
| | | | | | | We assumed that flags were only present on binary operators. This is not true, they may also be present on calls and fcmps. llvm-svn: 267113
* Fix some spelling mistakesDavid Majnemer2016-04-221-2/+2
| | | | llvm-svn: 267112
* [EarlyCSE] Take the intersection of flags on instructionsDavid Majnemer2016-04-223-66/+58
| | | | | | | | | | | | | EarlyCSE had inconsistent behavior with regards to flag'd instructions: - In some cases, it would pessimize if the available instruction had different flags by not performing CSE. - In other cases, it would miscompile if it replaced an instruction which had no flags with an instruction which has flags. Fix this by being more consistent with our flag handling by utilizing andIRFlags. llvm-svn: 267111
* [SCEV] Extract out a `isSCEVExprNeverPoison` helper; NFCISanjoy Das2016-04-221-29/+41
| | | | | | | | | | | | | | Summary: Also adds a small comment blurb on control flow + no-wrap flags, since that question came up a few days back on llvm-dev. Reviewers: bjarke.roune, broune Subscribers: sanjoy, mcrosier, llvm-commits, mzolotukhin Differential Revision: http://reviews.llvm.org/D19209 llvm-svn: 267110
* [SystemZ] Mark CTTZ_ZERO_UNDEF/CTLZ_ZERO_UNDEF as Expand instead of Custom ↵Craig Topper2016-04-221-8/+2
| | | | | | since the custom logic just did what Expand does when CTTZ/CTLZ are Legal. NFC llvm-svn: 267109
* [Lanai] Set CTLZ_ZERO_UNDEF/CTTZ_ZERO_UNDEF to Expand instead of Legal so ↵Craig Topper2016-04-222-11/+2
| | | | | | they will be converted to CTLZ/CTTZ by LegalizeDAG. Remove extra instructions that only existed to to contain patterns that match the zero_undef operations. NFC llvm-svn: 267108
* [Lanai] Remove unused methods declarations. NFCCraig Topper2016-04-221-3/+0
| | | | llvm-svn: 267107
* Clean the API for CollectAsmUndefinedRefs, taking a Triple and a String ↵Mehdi Amini2016-04-221-5/+3
| | | | | | | InlineAsm instead of a Module (NFC) From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 267106
* IRObjectFile, clang-format fixup for r267104Mehdi Amini2016-04-221-4/+5
| | | | | From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 267105
* Use std::move on the enum to insert it into the pair to please MSVCMehdi Amini2016-04-221-1/+1
| | | | | | | | (I have no idea why is it needed) Fixup for r267103 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 267104
* Refactor IRObjectFile, extract a static CollectAsmUndefinedRefs() method to ↵Mehdi Amini2016-04-221-4/+15
| | | | | | | | | parse inline assembly (NFC) I plan to call this from ThinLTOCodeGenerator. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 267103
* AMDGPU/SI: add llvm.amdgcn.ps.live intrinsicNicolai Haehnle2016-04-225-16/+66
| | | | | | | | | | | | | | | | | | | | | | | Summary: This intrinsic returns true if the current thread belongs to a live pixel and false if it belongs to a pixel that we are executing only for derivative computation. It will be used by Mesa to implement gl_HelperInvocation. Note that for pixels that are killed during the shader, this implementation also returns true, but it doesn't matter because those pixels are always disabled in the EXEC mask. This unearthed a corner case in the instruction verifier, which complained about a v_cndmask 0, 1, exec, exec<imp-use> instruction. That's stupid but correct code, so make the verifier accept it as such. Reviewers: arsenm, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19191 llvm-svn: 267102
* [AVX512] Teach lowering to use vplzcntd/q to implement 128/256-bit ↵Craig Topper2016-04-221-9/+6
| | | | | | CTTZ_ZERO_UNDEF even without VLX support. We can just extend to 512-bits and extract like we do for CTLZ. llvm-svn: 267100
* ValueMapper/Enumerator: Clean up code in post-order traversals, NFCDuncan P. N. Exon Smith2016-04-223-76/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Re-layer the functions in the new (i.e., newly correct) post-order traversals in ValueEnumerator (r266947) and ValueMapper (r266949). Instead of adding a node to the worklist in a helper function and returning a flag to say what happened, return the node itself. This makes the code way cleaner: the worklist is local to the main function, there is no flag for an early loop exit (since we can cleanly bury the loop), and it's perfectly clear when pointers into the worklist might be invalidated. I'm fixing both algorithms in the same commit to avoid repeating the commit message; if you take the time to understand one the other should be easy. The diff itself isn't entirely obvious since the traversals have some noise (i.e., things to do), but here's the high-level change: auto helper = [&WL](T *Op) { auto helper = [](T **&I, T **E) { => while (I != E) { if (shouldVisit(Op)) { T *Op = *I++; WL.push(Op, Op->begin()); if (shouldVisit(Op)) { return true; return Op; } } return false; return nullptr; }; }; => WL.push(S, S->begin()); WL.push(S, S->begin()); while (!empty()) { while (!empty()) { auto *N = WL.top().N; auto *N = WL.top().N; auto *&I = WL.top().I; auto *&I = WL.top().I; bool DidChange = false; while (I != N->end()) if (helper(*I++)) { => if (T *Op = helper(I, N->end()) { DidChange = true; WL.push(Op, Op->begin()); break; continue; } } if (DidChange) continue; POT.push(WL.pop()); => POT.push(WL.pop()); } } Thanks to Mehdi for helping me find a better way to layer this. llvm-svn: 267099
* [MachineCombiner] Support for floating-point FMA on ARM64Gerolf Hoflehner2016-04-227-39/+584
| | | | | | | | | | | | | | | | Evaluates fmul+fadd -> fmadd combines and similar code sequences in the machine combiner. It adds support for float and double similar to the existing integer implementation. The key features are: - DAGCombiner checks whether it should combine greedily or let the machine combiner do the evaluation. This is only supported on ARM64. - It gives preference to throughput over latency: the heuristic used is to combine always in loops. The targets decides whether the machine combiner should optimize for throughput or latency. - Supports for fmadd, f(n)msub, fmla, fmls patterns - On by default at O3 ffast-math llvm-svn: 267098
* [ThinLTO] Remove unused/incomplete lazy summary reading support (NFC)Teresa Johnson2016-04-223-84/+14
| | | | | | | | | | | | | | This removes the interfaces added (and not yet complete) to support lazy reading of summaries. This support is not expected to be needed since we are moving to a model where the full index is only being traversed in the thin link step, instead of the back ends. (The second part of this that I plan to do next is remove the GlobalValueInfo from the ModuleSummaryIndex - it was mostly needed to support lazy parsing of summaries. The index can instead reference the summary structures directly.) llvm-svn: 267097
* [WebAssembly] Limit alignment hints to natural alignment.Dan Gohman2016-04-211-3/+9
| | | | | | This follows the current binary format rules. llvm-svn: 267082
* ARM: restrict register class for WIN__DBZCHKSaleem Abdulrasool2016-04-211-2/+2
| | | | | | | | | | | WIN__DBZCHK will insert a CBZ instruction into the stream. This instruction reserves 3 bits for the condition register (rn). As such, we must ensure that we restrict the register to a low register. Use the tGPR class instead of GPR to ensure that this is properly constrained. In debug builds, we would attempt to use lr as a condition register which would silently get truncated with no hint that the register selection was incorrect. llvm-svn: 267080
* Fix more -Wunused-variable in non-asserts build.David Blaikie2016-04-211-3/+2
| | | | llvm-svn: 267077
* MachO: enable .data_region directives everywhereTim Northover2016-04-213-6/+1
| | | | | | | | | | We'd disabled them on x86 because back in the early days some host tools couldn't handle the new load commands. This no longer holds: anyone capable of deploying Clang should be able to deploy its copies of ar/ranlib/etc. rdar://25254790 llvm-svn: 267075
* Fix some -Wunused-variable warnings in non-asserts builds.David Blaikie2016-04-211-5/+6
| | | | llvm-svn: 267073
* Fix PDB warnings and testReid Kleckner2016-04-212-22/+9
| | | | llvm-svn: 267071
* Improve error message reporting for MachineFunctionPropertiesDerek Schuff2016-04-212-2/+4
| | | | | | | | When printing the properties required by a pass, only print the properties that are set, and not those that are clear (only properties that are set are verified, clear properties are "don't-care"). llvm-svn: 267070
* Remove dead code. NFCAmaury Sechet2016-04-211-4/+0
| | | | llvm-svn: 267069
* Fix -Wreturn-type warning with HAVE_DIA_SDK is false.Zachary Turner2016-04-211-0/+2
| | | | llvm-svn: 267068
* Fix for case sensitive filename failure.Zachary Turner2016-04-211-1/+1
| | | | llvm-svn: 267066
* Fixed flag descriptionMike Aizatsky2016-04-211-3/+3
| | | | | | | | | | | | | | Summary: asan-use-after-return control feature we call use-after-return or stack-use-after-return. Reviewers: kcc, aizatsky, eugenis Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D19284 llvm-svn: 267064
* Remove various warnings. NFCAmaury Sechet2016-04-212-5/+4
| | | | llvm-svn: 267061
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