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* [LoopDist] Move loop-versioning helper functions to Cloning, NFCAdam Nemet2015-07-102-66/+70
| | | | | | | | | | | | | | Summary: This makes them available to the LoopVersioning class as that is moved to its own module in the next patch. Reviewers: ashutosh.nema, hfinkel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10576 llvm-svn: 241931
* ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common codeMatthias Braun2015-07-101-166/+186
| | | | | | | | | | | | This commit factors out common code from MergeBaseUpdateLoadStore() and MergeBaseUpdateLSMultiple() and introduces a new function MergeBaseUpdateLSDouble() which merges adds/subs preceding/following a strd/ldrd instruction into an strd/ldrd instruction with writeback where possible. Differential Revision: http://reviews.llvm.org/D10676 llvm-svn: 241928
* ComputeKnownBits: be a bit smarter about ADDsFiona Glaser2015-07-101-5/+14
| | | | | | | | If our two inputs have known top-zero bit counts M and N, we trivially know that the output cannot have any bits set in the top (min(M, N)-1) bits, since nothing could carry past that point. llvm-svn: 241927
* ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2Matthias Braun2015-07-101-29/+96
| | | | | | Differential Revision: http://reviews.llvm.org/D10623 llvm-svn: 241926
* WebAssembly: basic instructions todo, and basic register info.JF Bastien2015-07-1016-19/+331
| | | | | | | | | | | | | | Summary: This code is based on AArch64 for modern backend good practice, and NVPTX for virtual ISA concerns. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11070 llvm-svn: 241923
* MIR Serialization: Initial serialization of stack objects.Alex Lorenz2015-07-102-3/+39
| | | | | | | | | | | | | | This commit implements the initial serialization of stack objects from the MachineFrameInfo class. It can only serialize the ordinary stack objects (including ordinary spill slots), but it doesn't serialize variable sized or fixed stack objects yet. The stack objects are serialized using a YAML sequence of YAML inline mappings. Each mapping has the object's ID, type, size, offset and alignment. The stack objects are a part of machine function's YAML mapping. Reviewers: Duncan P. N. Exon Smith llvm-svn: 241922
* Target RegisterInfo: devirtualize TargetFrameLoweringJF Bastien2015-07-108-61/+50
| | | | | | | | | | | | | Summary: The target frame lowering's concrete type is always known in RegisterInfo, yet it's only sometimes devirtualized through a static_cast. This change adds an auto-generated static function <Target>GenRegisterInfo::getFrameLowering(const MachineFunction &MF) which does this devirtualization, and uses this function in all targets which can. This change was suggested by sunfish in D11070 for WebAssembly, I figure that I may as well improve the other targets while I'm here. Subscribers: sunfish, ted, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11093 llvm-svn: 241921
* ARMLoadStoreOptimizer: Rewrite LDM/STM matching logic.Matthias Braun2015-07-101-551/+481
| | | | | | | | | | | | | | | | | | | | | This improves the logic in several ways and is a preparation for followup patches: - First perform an analysis and create a list of merge candidates, then transform. This simplifies the code in that you have don't have to care to much anymore that you may be holding iterators to MachineInstrs that get removed. - Analyze/Transform basic blocks in reverse order. This allows to use LivePhysRegs to find free registers instead of the RegisterScavenger. The RegisterScavenger will become less precise in the future as it relies on the deprecated kill-flags. - Return the newly created node in MergeOps so there's no need to look around in the schedule to find it. - Rename some MBBI iterators to InsertBefore to make their role clear. - General code cleanup. Differential Revision: http://reviews.llvm.org/D10140 llvm-svn: 241920
* Actually support volatile memcpys in NVPTX loweringEli Bendersky2015-07-101-8/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D11091 llvm-svn: 241914
* NFC. Added a blank line for consistency.Nemanja Ivanovic2015-07-101-0/+1
| | | | llvm-svn: 241913
* [InstSimplify] Fold away ord/uno fcmps when nnan is present.Benjamin Kramer2015-07-102-10/+19
| | | | | | | This is important to fold away the slow case of complex multiplies emitted by clang. llvm-svn: 241911
* Add support for fast-math flags to the FCmp instruction.James Molloy2015-07-103-18/+47
| | | | | | | | | | | | | | FCmp behaves a lot like a floating-point binary operator in many ways, and can benefit from fast-math information. Flags such as nsz and nnan can affect if this fcmp (in combination with a select) can be treated as a fminnum/fmaxnum operation. This adds backwards-compatible bitcode support, IR parsing and writing, LangRef changes and IRBuilder changes. I'll need to audit InstSimplify and InstCombine in a followup to find places where flags should be copied. llvm-svn: 241901
* Add missing builtins to the PPC back end for ABI compliance (vol. 3)Nemanja Ivanovic2015-07-101-0/+2
| | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D10973 Back end portion of the third round of additions to altivec.h. llvm-svn: 241900
* Disable loop re-rotation for -Oz (patch by Andrey Turetsky)Alexey Bataev2015-07-101-2/+2
| | | | | | | After changes in rL231820 loop re-rotation is performed even in -Oz mode. Since loop rotation is disabled for -Oz, it seems loop re-rotation should be disabled too. Differential Revision: http://reviews.llvm.org/D10961 llvm-svn: 241897
* Revert the new EH instructionsDavid Majnemer2015-07-1022-1014/+21
| | | | | | This reverts commits r241888-r241891, I didn't mean to commit them. llvm-svn: 241893
* Tighten the verifier check for catchblock.David Majnemer2015-07-101-3/+4
| | | | llvm-svn: 241891
* Address Joseph's review comments.David Majnemer2015-07-103-3/+78
| | | | llvm-svn: 241890
* Address Reid's review feedback.David Majnemer2015-07-102-10/+14
| | | | llvm-svn: 241889
* New EH representation for MSVC compatibilityDavid Majnemer2015-07-1022-19/+932
| | | | | | | | | | | | | | | Summary: This introduces new instructions neccessary to implement MSVC-compatible exception handling support. Most of the middle-end and none of the back-end haven't been audited or updated to take them into account. Reviewers: rnk, JosephTremoulet, reames, nlewycky, rjmccall Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11041 llvm-svn: 241888
* [InstCombine] Employ AliasAnalysis in FindAvailableLoadedValueBjorn Steinbrink2015-07-103-8/+18
| | | | llvm-svn: 241887
* [InstCombine] Properly combine metadata when replacing a load with anotherBjorn Steinbrink2015-07-101-1/+18
| | | | | | | | Not doing this can lead to misoptimizations down the line, e.g. because of range metadata on the replacing load excluding values that are valid for the load that is being replaced. llvm-svn: 241886
* [NVPTX] declare no vector registersJingyue Wu2015-07-102-0/+8
| | | | | | | | | | | | | | | | | Summary: Without this patch, LoopVectorizer in certain cases (see loop-vectorize.ll) produces code with complex control flow which hurts later optimizations. Since NVPTX doesn't have vector registers in LLVM's sense (NVPTXTTI::getRegisterBitWidth(true) == 32), we for now declare no vector registers to effectively disable loop vectorization. Reviewers: jholewinski Subscribers: jingyue, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11089 llvm-svn: 241884
* [WinEH] Make sure LSDA tables are 4 byte alignedReid Kleckner2015-07-102-2/+6
| | | | | | | | | | Apparently this is important, otherwise _except_handler3 assumes that the registration node is corrupted and ignores it. Also fix a bug in WinEHPrepare where we would insert code after a terminator instruction. llvm-svn: 241877
* Replace index-loops by range-based loopsEli Bendersky2015-07-091-6/+3
| | | | | | NFC llvm-svn: 241875
* [x86] enable machine combiner reassociations for scalar double-precision ↵Sanjay Patel2015-07-091-1/+3
| | | | | | multiplies llvm-svn: 241873
* [x86] enable machine combiner reassociations for scalar double-precision addsSanjay Patel2015-07-091-0/+2
| | | | llvm-svn: 241871
* MIR Serialization: Serialize the virtual register definitions.Alex Lorenz2015-07-092-6/+62
| | | | | | | | | | | | The virtual registers are serialized using a YAML sequence of YAML inline mappings. Each mapping has the id of the virtual register and the register class. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10981 llvm-svn: 241868
* [LAA] Fix grammar in debug outputAdam Nemet2015-07-091-1/+1
| | | | llvm-svn: 241867
* [LAA] Hide NeedRTCheck logic completely inside canCheckPtrAtRT, NFCAdam Nemet2015-07-091-31/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently canCheckPtrAtRT returns two flags NeedRTCheck and CanDoRT. NeedRTCheck says whether we need checks and CanDoRT whether we can generate the checks. The idea is to encode three states with these: Need/Can: (1) false/dont-care: no checks are needed (2) true/false: we need checks but can't generate them (3) true/true: we need checks and we can generate them This is pretty unnecessary since the caller (analyzeLoop) is only interested in whether we can generate the checks if we actually need them (i.e. 1 or 3). So this change cleans up to return just that (CanDoRTIfNeeded) and pulls all the underlying logic into canCheckPtrAtRT. By doing all this, we simplify analyzeLoop which is the complex function in LAA. There is further room for improvement here by using RtCheck.Need directly rather than a new local variable NeedRTCheck but that's for a later patch. llvm-svn: 241866
* [WinEH] Give up on using CSRs across 32-bit invokes for nowReid Kleckner2015-07-091-2/+17
| | | | | | | | | | | The runtime does not restore CSRs when transferring control back to the function handling the exception. According to the experts on IRC, LLVM's register allocator has no way to model register clobbers that only happen on one edge of the CFG. For now, don't worry about trying to use the meager three CSRs available on 32-bit X86 and just say that such invokes preserve nothing. llvm-svn: 241865
* Expose sjlj preparation through opt for my own debugging purposesReid Kleckner2015-07-091-0/+2
| | | | llvm-svn: 241864
* MIR Parser: Report an error when parsing machine function with an empty body.Alex Lorenz2015-07-091-0/+3
| | | | | | | | | | This commit adds a new error which is reported when the MIR Parser encounters a machine function without any machine basic blocks. The machine verifier expects that the machine functions have at least one MBB, and this error will prevent machine functions without MBBs from reaching the machine verifier and crashing with an assertion. llvm-svn: 241862
* AMDGPU: Add helper function for implicit parameter offsets.Tom Stellard2015-07-094-4/+28
| | | | | | Patch by: Zoltan Gilian llvm-svn: 241861
* Unbreak WebAssembly buildJF Bastien2015-07-094-26/+6
| | | | | | | | | | | | Summary: D11021 and D11045 didn't update the WebAssembly target's code. It's still experimental so all tests passed. Reviewers: sunfish, joker.eph, echristo Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11084 llvm-svn: 241859
* [ImplicitNullChecks] Fix a memory leak.Sanjoy Das2015-07-091-1/+1
| | | | llvm-svn: 241851
* [ImplicitNullChecks] Be smarter in picking the memory op.Sanjoy Das2015-07-091-8/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Before this change ImplicitNullChecks would only pick loads of the form: ``` test Reg, Reg jz elsewhere fallthrough: movl 32(Reg), Reg2 ``` but not (say) ``` test Reg, Reg jz elsewhere fallthrough: inc Reg3 movl 32(Reg), Reg2 ``` This change teaches ImplicitNullChecks to look through "unrelated" instructions like `inc Reg3` when searching for a load instruction to convert to a trapping load. Reviewers: atrick, JosephTremoulet, reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11044 llvm-svn: 241850
* MIR Serialization: Serialize the simple MachineFrameInfo attributes.Alex Lorenz2015-07-092-0/+45
| | | | | | | | | | | | This commit serializes the 13 scalar boolean and integer attributes from the MachineFrameInfo class: IsFrameAddressTaken, IsReturnAddressTaken, HasStackMap, HasPatchPoint, StackSize, OffsetAdjustment, MaxAlignment, AdjustsStack, HasCalls, MaxCallFrameSize, HasOpaqueSPAdjustment, HasVAStart, and HasMustTailInVarArgFunc. These attributes are serialized as part of the frameInfo YAML mapping, which itself is a part of the machine function's YAML mapping. llvm-svn: 241844
* llvm-ar: Pad the symbol table to 4 bytes.Rafael Espindola2015-07-091-2/+5
| | | | | | | It looks like ld64 requires it. With this we seem to be able to bootstrap using llvm-ar+/usr/bin/true instead of ar+ranlib (currently on stage2). llvm-svn: 241842
* AMDGPU/R600: Return correct chain when lowering loadsMatt Arsenault2015-07-091-8/+2
| | | | | | The other LowerLOAD should be returning the correct chain. llvm-svn: 241839
* [IndVars] Try to use existing values in RewriteLoopExitValues.Sanjoy Das2015-07-091-2/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In RewriteLoopExitValues, before expanding out an SCEV expression using SCEVExpander, try to see if an existing LLVM IR expression already computes the value we're interested in. If so use that existing expression. Apart from reducing IndVars' reliance on the rest of the compilation pipeline, this also prevents IndVars from concluding some expressions as "high cost" when they're not. For instance, `InductiveRangeCheckElimination` often emits code of the following form: ``` len = umin(len_A, len_B) loop: ... if (i++ < len) goto loop outside_loop: use(i) ``` `SCEVExpander` refuses to rewrite the use of `i` in `outside_loop`, since it thinks the value of `i` on loop exit, `len`, is a high cost expansion since it contains an `umax` in it. With this change, `IndVars` can see that it can re-use `len` instead of creating a new expression to compute `umin(len_A, len_B)`. I considered putting this cleverness in `SCEVExpander`, but I was worried that it may then have a deterimental effect on other passes that use it. So I decided it was better to just do this in the one place where it seems like an obviously good idea, with the intent of generalizing later if needed. Reviewers: atrick, reames Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10782 llvm-svn: 241838
* Remove dead code from old 64-bit SEH loweringReid Kleckner2015-07-092-26/+0
| | | | llvm-svn: 241829
* Allow {e,r}bp as the target of {read,write}_register.Pat Gavlin2015-07-0911-17/+46
| | | | | | | | | | This patch allows the read_register and write_register intrinsics to read/write the RBP/EBP registers on X86 iff the targeted register is the frame pointer for the containing function. Differential Revision: http://reviews.llvm.org/D10977 llvm-svn: 241827
* fix an invisible bug when combining repeated FP divisorsSanjay Patel2015-07-091-2/+9
| | | | | | | | | | | | | | | | | | | | | | | This patch fixes bugs that were exposed by the addition of fast-math-flags in the DAG: r237046 ( http://reviews.llvm.org/rL237046 ): 1. When replacing a division node, it's not enough to RAUW. We should call CombineTo() to delete dead nodes and combine again. 2. Because we are changing the DAG, we can't return an empty SDValue after the transform. As the code comments say: Visitation implementation - Implement dag node combining for different node types. The semantics are as follows: Return Value: SDValue.getNode() == 0 - No change was made SDValue.getNode() == N - N was replaced, is dead and has been handled. otherwise - N should be replaced by the returned Operand. The new test case shows no difference with or without this patch, but it will crash if we re-apply r237046 or enable FMF via the current -enable-fmf-dag cl::opt. Differential Revision: http://reviews.llvm.org/D9893 llvm-svn: 241826
* [StackMap] Use lambdas to specify the sort and erase conditions. NFC.Juergen Ributzka2015-07-091-6/+14
| | | | llvm-svn: 241823
* [StackMap] Rename variables to be more consistent. NFC.Juergen Ributzka2015-07-091-40/+38
| | | | | | Rename a few variables and use auto for long iterator names. llvm-svn: 241822
* [StackMaps] Use emplace_back when possible. NFC.Juergen Ributzka2015-07-091-5/+5
| | | | llvm-svn: 241821
* AMDGPU/SI: The SIShrinkInstructions pass should only fold immediates with ↵Tom Stellard2015-07-091-1/+1
| | | | | | | | | one use This is convered by existing testcases and will be exposed by a future commit. llvm-svn: 241817
* AMDGPU/SI: Fix crash on physical registers in SIInstrInfo::isOperandLegal()Tom Stellard2015-07-091-1/+4
| | | | | | | No test case for this. I ran into it while working on some improvements to SIShrinkInstructions.cpp. llvm-svn: 241816
* Basic support for BSD symbol tables in archives.Rafael Espindola2015-07-091-17/+39
| | | | | | | This could be optimized and for now we only produce __.SYMDEF and not "__.SYMDEF SORTED". llvm-svn: 241814
* [Hexagon] Add missing preamble to a source fileKrzysztof Parzyszek2015-07-091-0/+9
| | | | llvm-svn: 241813
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