| Commit message (Collapse) | Author | Age | Files | Lines |
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Functions explicitly marked inline will get an inlining threshold slightly
more aggressive than the default for -O3. This means than -O3 builds are
mostly unaffected while -Os builds will be a bit bigger and faster.
The difference depends entirely on how many 'inline's are sprinkled on the
source.
In the CINT2006 suite, only these tests are significantly affected under -Os:
Size Time
471.omnetpp +1.63% -1.85%
473.astar +4.01% -6.02%
483.xalancbmk +4.60% 0.00%
Note that 483.xalancbmk runs too quickly to give useful timing results.
llvm-svn: 96066
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llvm-svn: 96065
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avoid fixups for obvious cases like '-(16)'.
llvm-svn: 96064
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llvm-svn: 96063
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We still have the templated X86 JIT emitter, *and* the
almost-copy in X86InstrInfo for getting instruction sizes.
llvm-svn: 96059
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fix swapgs to be spelled right.
llvm-svn: 96058
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phi cycles. Adjust a few tests to keep dead instructions from being optimized
away. This (together with my previous change for phi cycles) fixes Apple
radar 7627077.
llvm-svn: 96057
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SCEVAddRecExpr doesn't necessarily dominate blocks merely dominated
by all of its operands. This fixes an abort compiling 403.gcc.
llvm-svn: 96056
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llvm-svn: 96055
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separate LLVMContexts.
llvm-svn: 96051
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encoder and decoder by using new MRM_ forms.
llvm-svn: 96048
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rip-relative addresses, and add a testcase.
llvm-svn: 96040
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The solution there produces correct code, but is seriously
deficient in several ways.
llvm-svn: 96039
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llvm-svn: 96038
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Patch by Shivram K!
llvm-svn: 96037
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addressing. This isn't complete because I need an MCContext
to generate new MCExprs.
llvm-svn: 96036
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Plus add two formats: MiscFrm and ThumbMiscFrm. Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.
llvm-svn: 96032
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llvm-svn: 96031
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llvm-svn: 96029
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llvm-svn: 96028
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is pc relative or not, mark call and branches as pcrel.
llvm-svn: 96026
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up with a reasonable test case.
llvm-svn: 96023
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llvm-svn: 96020
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llvm-svn: 96019
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stack frame, the prolog/epilog code was using the same
register for the copy of CR and the address of the save slot. Oops.
This is fixed here for Darwin, sort of, by reserving R2 for this case.
A better way would be to do the store before the decrement of SP,
which is safe on Darwin due to the red zone.
SVR4 probably has the same problem, but I don't know how to fix it;
there is no red zone and R2 is already used for something else.
I'm going to leave it to someone interested in that target.
Better still would be to rewrite the CR-saving code completely;
spilling each CR subregister individually is horrible code.
llvm-svn: 96015
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llvm-svn: 96011
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llvm-svn: 96010
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llvm-svn: 96008
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llvm-svn: 96007
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llvm-svn: 96006
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llvm-svn: 96005
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offset distributions it doesn't expect.
llvm-svn: 96002
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llvm-svn: 95999
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didn't handle
X =
Y<dead> = use X
DBG_VALUE(X)
I was hoping to avoid this approach as it's slower,
but I don't think it can be done.
llvm-svn: 95996
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2. don't bother trying to merge globals in non-default sections,
doing so is quite dubious at best anyway.
3. fix a bug reported by Arnaud de Grandmaison where we'd try to
merge two globals in different address spaces.
llvm-svn: 95995
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is breaking llvm-gcc bootstrap.
llvm-svn: 95988
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llvm-svn: 95981
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This should fix alot of problems we saw so far, e.g. PRs 5851 & 2936
llvm-svn: 95980
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doesn't matter, except that ScalarEvolution tends to need less time
to fold the results this way.
llvm-svn: 95979
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bug fixes, and with improved heuristics for analyzing foreign-loop
addrecs.
This change also flattens IVUsers, eliminating the stride-oriented
groupings, which makes it easier to work with.
llvm-svn: 95975
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costs.
* Enabled R1/R2 application for nodes with infinite spill costs in the Briggs heuristic (made
safe by the changes to the normalization proceedure).
* Removed a redundant header.
llvm-svn: 95973
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This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.
llvm-svn: 95960
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great solution for the disassembler, we'll go with "plan b".
llvm-svn: 95957
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MRRC, MRRc2. For disassembly only.
llvm-svn: 95955
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reduce down to a single value. InstCombine already does this transformation
but DAG legalization may introduce new opportunities. This has turned out to
be important for ARM where 64-bit values are split up during type legalization:
InstCombine is not able to remove the PHI cycles on the 64-bit values but
the separate 32-bit values can be optimized. I measured the compile time
impact of this (running llc on 176.gcc) and it was not significant.
llvm-svn: 95951
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with "tied memory operands", which is wrong.
llvm-svn: 95950
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llvm-svn: 95949
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movq (%ecx,%edx,2), %xmm2
movhps (%ecx,%eax,2), %xmm2
rather than:
movq (%eax, %edx, 2), %xmm2
movq (%eax, %ebx, 2), %xmm3
movlhps %xmm3, %xmm2
Testcase forthcoming.
llvm-svn: 95948
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busted in both encoders. I'm not bothering to fix it in the
old one at this point.
llvm-svn: 95947
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Kees van Reeuwijk!
llvm-svn: 95946
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