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* Enable the inlinehint attribute in the Inliner.Jakob Stoklund Olesen2010-02-131-13/+12
| | | | | | | | | | | | | | | | | | | | Functions explicitly marked inline will get an inlining threshold slightly more aggressive than the default for -O3. This means than -O3 builds are mostly unaffected while -Os builds will be a bit bigger and faster. The difference depends entirely on how many 'inline's are sprinkled on the source. In the CINT2006 suite, only these tests are significantly affected under -Os: Size Time 471.omnetpp +1.63% -1.85% 473.astar +4.01% -6.02% 483.xalancbmk +4.60% 0.00% Note that 483.xalancbmk runs too quickly to give useful timing results. llvm-svn: 96066
* Fixed encodings for invlpg, invept, and invvpid.Sean Callanan2010-02-131-3/+3
| | | | llvm-svn: 96065
* MC/AsmParser: Attempt to constant fold expressions up-front. This ensures we ↵Daniel Dunbar2010-02-131-2/+10
| | | | | | avoid fixups for obvious cases like '-(16)'. llvm-svn: 96064
* Added a bunch of saturating add/subtract instructions for disassembly only.Johnny Chen2010-02-131-0/+72
| | | | llvm-svn: 96063
* rip out the 'heinous' x86 MCCodeEmitter implementation.Chris Lattner2010-02-133-338/+2
| | | | | | | We still have the templated X86 JIT emitter, *and* the almost-copy in X86InstrInfo for getting instruction sizes. llvm-svn: 96059
* remove special cases for vmlaunch, vmresume, vmxoff, and swapgsChris Lattner2010-02-135-12/+36
| | | | | | fix swapgs to be spelled right. llvm-svn: 96058
* Besides removing phi cycles that reduce to a single value, also remove deadBob Wilson2010-02-132-21/+72
| | | | | | | | phi cycles. Adjust a few tests to keep dead instructions from being optimized away. This (together with my previous change for phi cycles) fixes Apple radar 7627077. llvm-svn: 96057
* Override dominates and properlyDominates for SCEVAddRecExpr, as aDan Gohman2010-02-131-0/+15
| | | | | | | SCEVAddRecExpr doesn't necessarily dominate blocks merely dominated by all of its operands. This fixes an abort compiling 403.gcc. llvm-svn: 96056
* MC/X86: Push immediate operands as immediates not expressions when possible.Daniel Dunbar2010-02-131-4/+12
| | | | llvm-svn: 96055
* Make PassRegistrar thread-safe since it can be modified by code running inJeffrey Yasskin2010-02-131-0/+9
| | | | | | separate LLVMContexts. llvm-svn: 96051
* Remove special cases for [LM]FENCE, MONITOR and MWAIT fromChris Lattner2010-02-123-38/+9
| | | | | | encoder and decoder by using new MRM_ forms. llvm-svn: 96048
* implement the rest of correct x86-64 encoder support for Chris Lattner2010-02-121-5/+9
| | | | | | rip-relative addresses, and add a testcase. llvm-svn: 96040
* Add the problem I just hacked around in 96015/96020.Dale Johannesen2010-02-121-0/+17
| | | | | | | The solution there produces correct code, but is seriously deficient in several ways. llvm-svn: 96039
* give MCCodeEmitters access to the current MCContext.Chris Lattner2010-02-124-9/+16
| | | | llvm-svn: 96038
* Make JIT::runFunction clean up the generated stub function.Jeffrey Yasskin2010-02-121-2/+6
| | | | | | Patch by Shivram K! llvm-svn: 96037
* implement infrastructure to support fixups for rip-rel Chris Lattner2010-02-122-13/+32
| | | | | | | addressing. This isn't complete because I need an MCContext to generate new MCExprs. llvm-svn: 96036
* Add YIELD, WFE, WFI, and SEV instructions for disassembly only.Johnny Chen2010-02-122-5/+36
| | | | | | | Plus add two formats: MiscFrm and ThumbMiscFrm. Some of the for disassembly only instructions are changed from Pseudo Format to MiscFrm Format. llvm-svn: 96032
* pull the rip-relative addressing mode case up early.Chris Lattner2010-02-121-5/+12
| | | | llvm-svn: 96031
* fixme resolved!Chris Lattner2010-02-121-1/+0
| | | | llvm-svn: 96029
* start producing reloc_pcrel_4byte/reloc_pcrel_1byte for calls.Chris Lattner2010-02-121-23/+28
| | | | llvm-svn: 96028
* enhance the immediate field encoding to know whether the immediateChris Lattner2010-02-123-23/+59
| | | | | | is pc relative or not, mark call and branches as pcrel. llvm-svn: 96026
* Load / store multiple instructions cannot load / store sp. Sorry, can't come ↵Evan Cheng2010-02-121-1/+2
| | | | | | up with a reasonable test case. llvm-svn: 96023
* This should have gone in with 26015, see comments there.Dale Johannesen2010-02-121-0/+12
| | | | llvm-svn: 96020
* Add halfword multiply accumulate long SMLALBB/BT/TB/TT for disassembly only.Johnny Chen2010-02-121-1/+33
| | | | llvm-svn: 96019
* When save/restoring CR at prolog/epilog, in a largeDale Johannesen2010-02-121-14/+30
| | | | | | | | | | | | | | | | | stack frame, the prolog/epilog code was using the same register for the copy of CR and the address of the save slot. Oops. This is fixed here for Darwin, sort of, by reserving R2 for this case. A better way would be to do the store before the decrement of SP, which is safe on Darwin due to the red zone. SVR4 probably has the same problem, but I don't know how to fix it; there is no red zone and R2 is already used for something else. I'm going to leave it to someone interested in that target. Better still would be to rewrite the CR-saving code completely; spilling each CR subregister individually is horrible code. llvm-svn: 96015
* Add support for a union type in LLVM IR. Patch by Talin!Chris Lattner2010-02-1215-18/+363
| | | | llvm-svn: 96011
* Add SWP (Swap) and SWPB (Swap Byte) for disassembly only.Johnny Chen2010-02-121-0/+21
| | | | llvm-svn: 96010
* Also recognize armv6t2-* and armv5te-* triplets.Evan Cheng2010-02-121-5/+12
| | | | llvm-svn: 96008
* Fix a case of mismatched types in an Add that turned up in 447.dealII.Dan Gohman2010-02-121-0/+2
| | | | llvm-svn: 96007
* Add ARM bitcode file magic.Evan Cheng2010-02-121-3/+32
| | | | llvm-svn: 96006
* Reapply 95979, a compile-time speedup, now that the bug it exposed is fixed.Dan Gohman2010-02-121-1/+1
| | | | llvm-svn: 96005
* Fix this code to avoid dereferencing an end() iterator inDan Gohman2010-02-121-1/+5
| | | | | | offset distributions it doesn't expect. llvm-svn: 96002
* Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only.Johnny Chen2010-02-121-0/+44
| | | | llvm-svn: 95999
* Rewrite handling of DBG_VALUE; previous algorithmDale Johannesen2010-02-121-16/+24
| | | | | | | | | | | didn't handle X = Y<dead> = use X DBG_VALUE(X) I was hoping to avoid this approach as it's slower, but I don't think it can be done. llvm-svn: 95996
* 1. modernize the constantmerge pass, using densemap/smallvector.Chris Lattner2010-02-121-19/+22
| | | | | | | | | 2. don't bother trying to merge globals in non-default sections, doing so is quite dubious at best anyway. 3. fix a bug reported by Arnaud de Grandmaison where we'd try to merge two globals in different address spaces. llvm-svn: 95995
* Revert "Reverse the order for collecting the parts of an addrec. The order", itDaniel Dunbar2010-02-121-1/+1
| | | | | | is breaking llvm-gcc bootstrap. llvm-svn: 95988
* Setup correct data layout to match gcc's expectations on mingw32.Anton Korobeynikov2010-02-121-1/+1
| | | | llvm-svn: 95981
* Cleanup stdcall / fastcall name mangling.Anton Korobeynikov2010-02-127-151/+61
| | | | | | This should fix alot of problems we saw so far, e.g. PRs 5851 & 2936 llvm-svn: 95980
* Reverse the order for collecting the parts of an addrec. The orderDan Gohman2010-02-121-1/+1
| | | | | | | doesn't matter, except that ScalarEvolution tends to need less time to fold the results this way. llvm-svn: 95979
* Reapply the new LoopStrengthReduction code, with compile time andDan Gohman2010-02-125-2476/+2884
| | | | | | | | | | bug fixes, and with improved heuristics for analyzing foreign-loop addrecs. This change also flattens IVUsers, eliminating the stride-oriented groupings, which makes it easier to work with. llvm-svn: 95975
* * Updated the cost matrix normalization proceedure to better handle infinite ↵Lang Hames2010-02-122-13/+21
| | | | | | | | | | costs. * Enabled R1/R2 application for nodes with infinite spill costs in the Briggs heuristic (made safe by the changes to the normalization proceedure). * Removed a redundant header. llvm-svn: 95973
* add a bunch of mod/rm encoding types for fixed mod/rm bytes.Chris Lattner2010-02-125-0/+61
| | | | | | | This will work better for the disassembler for modeling things like lfence/monitor/vmcall etc. llvm-svn: 95960
* revert r95949, it turns out that adding new prefixes is not a Chris Lattner2010-02-122-10/+10
| | | | | | great solution for the disassembler, we'll go with "plan b". llvm-svn: 95957
* Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2,Johnny Chen2010-02-121-0/+84
| | | | | | MRRC, MRRc2. For disassembly only. llvm-svn: 95955
* Add a new pass on machine instructions to optimize away PHI cycles that Bob Wilson2010-02-123-0/+143
| | | | | | | | | | | reduce down to a single value. InstCombine already does this transformation but DAG legalization may introduce new opportunities. This has turned out to be important for ARM where 64-bit values are split up during type legalization: InstCombine is not able to remove the PHI cycles on the 64-bit values but the separate 32-bit values can be optimized. I measured the compile time impact of this (running llc on 176.gcc) and it was not significant. llvm-svn: 95951
* X86: Fix definition for RCL/RCR.*m? operations -- they were getting representedDaniel Dunbar2010-02-122-58/+63
| | | | | | with "tied memory operands", which is wrong. llvm-svn: 95950
* add another bit of space for new kinds of instruction prefixes.Chris Lattner2010-02-122-10/+10
| | | | llvm-svn: 95949
* Add a missing pattern for movhps so that we get:Nate Begeman2010-02-121-0/+3
| | | | | | | | | | | | | | | movq (%ecx,%edx,2), %xmm2 movhps (%ecx,%eax,2), %xmm2 rather than: movq (%eax, %edx, 2), %xmm2 movq (%eax, %ebx, 2), %xmm3 movlhps %xmm3, %xmm2 Testcase forthcoming. llvm-svn: 95948
* fix the encodings of monitor and mwait, which were completelyChris Lattner2010-02-121-7/+2
| | | | | | | busted in both encoders. I'm not bothering to fix it in the old one at this point. llvm-svn: 95947
* improve support for minix, PR6280, patch byChris Lattner2010-02-122-2/+11
| | | | | | Kees van Reeuwijk! llvm-svn: 95946
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