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* s/u_int32_t/uint32_t/Rafael Espindola2013-05-221-2/+2
| | | | llvm-svn: 182444
* Fix warning in non-assert build.Rafael Espindola2013-05-221-0/+2
| | | | llvm-svn: 182443
* Mips16 does not use register scavenger from TargetRegisterInfo. It allocatesReed Kotler2013-05-211-2/+2
| | | | | | | a RegScavenger object on it's own. llvm-svn: 182430
* Put RTDyldMemoryManager into its own file, and make it linked into Filip Pizlo2013-05-214-96/+117
| | | | | | | | | | | | | | | | | | libExecutionEngine. Move method implementations that aren't specific to allocation out of SectionMemoryManager and into RTDyldMemoryManager. This is in preparation for exposing RTDyldMemoryManager through the C API. This is a fixed version of r182407 and r182411. That first revision broke builds because I forgot to move the conditional includes of various POSIX headers from SectionMemoryManager into RTDyldMemoryManager. Those includes are necessary because of how getPointerToNamedFunction works around the glibc libc_nonshared.a thing. The latter revision still broke things because I forgot to include llvm/Config/config.h. llvm-svn: 182418
* Roll out r182411 and 182412 because it's still broken.Filip Pizlo2013-05-214-116/+96
| | | | llvm-svn: 182415
* Fix busted comment. This conditional include block used to be in ↵Filip Pizlo2013-05-211-1/+1
| | | | | | SectionMemoryManager, but is now in RTDyldMemoryManager. llvm-svn: 182412
* Put RTDyldMemoryManager into its own file, and make it linked into Filip Pizlo2013-05-214-96/+116
| | | | | | | | | | | | | | | | libExecutionEngine. Move method implementations that aren't specific to allocation out of SectionMemoryManager and into RTDyldMemoryManager. This is in preparation for exposing RTDyldMemoryManager through the C API. This is a fixed version of r182407. That revision broke builds because I forgot to move the conditional includes of various POSIX headers from SectionMemoryManager into RTDyldMemoryManager. Those includes are necessary because of how getPointerToNamedFunction works around the glibc libc_nonshared.a thing. llvm-svn: 182411
* Roll out r182407 and r182408 because they broke builds.Filip Pizlo2013-05-216-221/+89
| | | | llvm-svn: 182409
* Expose the RTDyldMemoryManager through the C API. This allows clients of Filip Pizlo2013-05-212-3/+115
| | | | | | | | the C API to provide their own way of allocating JIT memory (both code and data) and finalizing memory permissions (page protections, cache flush). llvm-svn: 182408
* Put RTDyldMemoryManager into its own file, and make it linked into Filip Pizlo2013-05-214-86/+106
| | | | | | | | | | libExecutionEngine. Move method implementations that aren't specific to allocation out of SectionMemoryManager and into RTDyldMemoryManager. This is in preparation for exposing RTDyldMemoryManager through the C API. llvm-svn: 182407
* [mips] Rename option to make it compatible with gcc.Akira Hatanaka2013-05-211-1/+1
| | | | llvm-svn: 182397
* [mips] Add instruction selection patterns for blez and bgez.Akira Hatanaka2013-05-212-0/+10
| | | | llvm-svn: 182396
* [NVPTX] Add @llvm.nvvm.sqrt.f() intrinsicJustin Holewinski2013-05-214-0/+24
| | | | llvm-svn: 182394
* Hexagon: SelectionDAG should not use MVT::Other to check the legality of BR_CC.Jyotsna Verma2013-05-211-1/+0
| | | | llvm-svn: 182390
* Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.Justin Holewinski2013-05-212-0/+11
| | | | | | | | | | The intrinsic calls are dropped, but the annotated value is propagated. Fixes PR 15253 Original patch by Zeng Bin! llvm-svn: 182387
* Fix PPC branch selection for counter-based branchesHal Finkel2013-05-211-3/+9
| | | | | | | | | | | | Although I had added some support for the BDZ/BDNZ branches into the selector (in r158204), I had not correctly adjusted the condition at the top of the loop. As a result, these branches were still essentially unsupported. This fixes PR16086. Unfortunately, any test case would be very large (because it would need to force the loop backedge to exceed the range of the 16-bit immediate). llvm-svn: 182385
* removed commented linesElena Demikhovsky2013-05-211-2/+0
| | | | llvm-svn: 182377
* [msan] A no-op implementation of VarArg handling.Evgeniy Stepanov2013-05-211-2/+23
| | | | | | | This stuff is used on platforms where MSan does not have a proper VarArg implementation (anything other than x86_64 at the moment). llvm-svn: 182375
* Removed SSEPacked domain from all forms (AVX, SSE, signed, unsigned) scalar ↵Elena Demikhovsky2013-05-212-25/+27
| | | | | | | | compare instructions, like COMISS, COMISD. No functional changes. llvm-svn: 182371
* X86: When emulating unsigned PCMPGTQ with PCMPGTD, fix the sign bit for the ↵Benjamin Kramer2013-05-211-15/+19
| | | | | | | | | smaller type. Otherwise we'll get a mix of signed and unsigned compares. Fixes PR15977. llvm-svn: 182364
* DAGCombine: Avoid an edge case where it tried to create an i0 type for (x & ↵Benjamin Kramer2013-05-211-1/+2
| | | | | | | | 0) == 0. Fixes PR16083. llvm-svn: 182357
* Fix indentationRichard Sandiford2013-05-211-9/+9
| | | | llvm-svn: 182356
* Add cmake bits for md5.Eric Christopher2013-05-211-0/+1
| | | | llvm-svn: 182349
* Add an md5 library derived from a public domain implementation for dwarf4Eric Christopher2013-05-211-0/+266
| | | | | | type signature computation. llvm-svn: 182348
* Dwarf: use a single line table to generate assembly when .loc is used.Manman Ren2013-05-211-3/+14
| | | | | | | | | This is to fix PR15408 where an undefined symbol Lline_table_start1 is used. Since we do not generate the debug_line section when .loc is used, Lline_table_start1 is not emitted and we can't refer to it when calculating at_stmt_list for a compile unit. llvm-svn: 182344
* Add some additional functions to the list of helper functions forReed Kotler2013-05-211-2/+13
| | | | | | | | | | pic calls. These need to be there so we don't try and use helper functions when we call those. As part of this, make sure that we properly exclude helper functions in pic mode when indirect calls are involved. llvm-svn: 182343
* PR14606: Debug Info for namespace aliases/DW_TAG_imported_moduleDavid Blaikie2013-05-203-11/+44
| | | | | | | | | This resolves the last of the PR14606 failures in the GDB 7.5 test suite by implementing an optional name field for DW_TAG_imported_modules/DIImportedEntities and using that to implement C++ namespace aliases (eg: "namespace X = Y;"). llvm-svn: 182328
* The DWARF EH pass doesn't need the TargetMachine, only the ↵Bill Wendling2013-05-202-5/+5
| | | | | | TargetLoweringBase like the other EH passes. llvm-svn: 182321
* No need to store the TargetMachine variable in this class.Bill Wendling2013-05-201-4/+2
| | | | llvm-svn: 182317
* Remove unused #include.Bill Wendling2013-05-201-1/+0
| | | | llvm-svn: 182315
* Rename LoopSimplify.h to LoopUtils.hHal Finkel2013-05-202-2/+2
| | | | | | As discussed, LoopUtils.h is a better name. llvm-svn: 182314
* [mips] Add (setne $lhs, 0) instruction selection pattern.Akira Hatanaka2013-05-201-0/+2
| | | | llvm-svn: 182307
* [mips] Trap on integer division by zero.Akira Hatanaka2013-05-204-5/+58
| | | | | | | By default, a teq instruction is inserted after integer divide. No divide-by-zero checks are performed if option "-mnocheck-zero-division" is used. llvm-svn: 182306
* Remove copied preheader insertion logic from PPCCTRLoopsHal Finkel2013-05-201-85/+3
| | | | | | | | | Now that the preheader insertion logic in LoopSimplify is externally exposed, use it, and remove the copy-and-pasted version. No functionality change intended. llvm-svn: 182300
* Expose InsertPreheaderForLoop from LoopSimplify to other passesHal Finkel2013-05-201-11/+12
| | | | | | | | | | | Other passes, PPC counter-loop formation for example, also need to add loop preheaders outside of the regular loop simplification pass. This makes InsertPreheaderForLoop a global function so that it can be used by other passes. No functionality change intended. llvm-svn: 182299
* [NVPTX] Fix mis-use of CurrentFnSym in NVPTXAsmPrinter. This was causing a ↵Justin Holewinski2013-05-201-9/+7
| | | | | | symbol name error in the output PTX. llvm-svn: 182298
* [NVPTX] Add programmatic interface to NVVMReflect passJustin Holewinski2013-05-202-3/+24
| | | | llvm-svn: 182297
* Rename PPC MTCTRse to MTCTRloopHal Finkel2013-05-203-7/+7
| | | | | | | | | | As the pairing of this instruction form with the bdnz/bdz branches is now enforced by the verification pass, make it clear from the name that these are used only for counter-based loops. No functionality change intended. llvm-svn: 182296
* Add a PPCCTRLoops verification passHal Finkel2013-05-203-0/+164
| | | | | | | | | | | | | | | | | | When asserts are enabled, this adds a verification pass for PPC counter-loop formation. Unfortunately, without sacrificing code quality, there is no better way of forming counter-based loops except at the (late) IR level. This means that we need to recognize, at the IR level, anything which might turn into a function call (or indirect branch). Because this is currently a finite set of things, and because SelectionDAG lowering is basic-block local, this can be done. Nevertheless, it is fragile, and failure results in a miscompile. This verification pass checks that all (reachable) counter-based branches are dominated by a loop mtctr instruction, and that no instructions in between clobber the counter register. If these conditions are not satisfied, then an ICE will be triggered. In short, this is to help us sleep better at night. llvm-svn: 182295
* R600: Fix bug detected by GCC warning.Benjamin Kramer2013-05-201-2/+2
| | | | | | | | | R600TextureIntrinsicsReplacer.cpp:232: warning: the address of ‘ArgsType’ will always evaluate as ‘true’ This doesn't have any effect on the output as a vararg intrinsic behaves the same way as a non-vararg one. llvm-svn: 182293
* R600/SI: Use a multiclass for MUBUF_Load_HelperTom Stellard2013-05-202-20/+30
| | | | | | | This will simplify the instructions and also the pattern definitions. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182288
* R600/SI: Add a pattern for S_LOAD_DWORDX2_* instructionsTom Stellard2013-05-201-0/+1
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182287
* R600/SI: Add pattern for rotrTom Stellard2013-05-201-0/+2
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182286
* R600: Swap the legality of rotl and rotrTom Stellard2013-05-207-28/+11
| | | | | | The hardware supports rotr and not rotl. llvm-svn: 182285
* R600/SI: Add patterns for 64-bit shift operationsTom Stellard2013-05-202-3/+22
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182284
* R600/SI: Use the same names for VOP3 operands and encoding fieldsTom Stellard2013-05-202-37/+37
| | | | | | | | This makes it possible to reorder the operands without breaking the encoding. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182283
* R600/SI: Make fitsRegClass() operands constTom Stellard2013-05-202-2/+3
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 182282
* VSTn instructions have a number of encoding constraints which are not ↵Mihai Popa2013-05-202-21/+72
| | | | | | implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review). llvm-svn: 182281
* Q registers are encoded in fields of the same length as D registers. As Q ↵Mihai Popa2013-05-201-1/+1
| | | | | | registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL). llvm-svn: 182279
* [SystemZ] Add long branch passRichard Sandiford2013-05-2011-34/+399
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this change, the SystemZ backend would use BRCL for all branches and only consider shortening them to BRC when generating an object file. E.g. a branch on equal would use the JGE alias of BRCL in assembly output, but might be shortened to the JE alias of BRC in ELF output. This was a useful first step, but it had two problems: (1) The z assembler isn't traditionally supposed to perform branch shortening or branch relaxation. We followed this rule by not relaxing branches in assembler input, but that meant that generating assembly code and then assembling it would not produce the same result as going directly to object code; the former would give long branches everywhere, whereas the latter would use short branches where possible. (2) Other useful branches, like COMPARE AND BRANCH, do not have long forms. We would need to do something else before supporting them. (Although COMPARE AND BRANCH does not change the condition codes, the plan is to model COMPARE AND BRANCH as a CC-clobbering instruction during codegen, so that we can safely lower it to a separate compare and long branch where necessary. This is not a valid transformation for the assembler proper to make.) This patch therefore moves branch relaxation to a pre-emit pass. For now, calls are still shortened from BRASL to BRAS by the assembler, although this too is not really the traditional behaviour. The first test takes about 1.5s to run, and there are likely to be more tests in this vein once further branch types are added. The feeling on IRC was that 1.5s is a bit much for a single test, so I've restricted it to SystemZ hosts for now. The patch exposes (and fixes) some typos in the main CodeGen/SystemZ tests. A later patch will remove the {{g}}s from that directory. llvm-svn: 182274
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