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* [InstCombine] break up foldICmpEqualityWithConstant(); NFCISanjay Patel2016-07-212-148/+161
| | | | | | | Almost all of these folds require changes to allow vector types. Splitting up the logic should make that easier to do incrementally. llvm-svn: 276360
* GVH-hoist: only clone GEPs (PR28606)Sebastian Pop2016-07-211-14/+7
| | | | | | | | | Do not clone stored values unless they are GEPs that are special cased to avoid hoisting them without hoisting their associated ld/st. Differential revision: https://reviews.llvm.org/D22652 llvm-svn: 276358
* [Profile] deprecate __llvm_profile_override_default_filenameXinliang David Li2016-07-211-16/+16
| | | | | | | | This eliminates unncessary calls and init functions. Differential Revision: http://reviews.llvm.org/D22613 llvm-svn: 276354
* [PM] Port NaryReassociate to the new PMWei Mi2016-07-214-112/+78
| | | | | | Differential Revision: https://reviews.llvm.org/D22648 llvm-svn: 276349
* [MIRTesting] Abort when failing to parse a function.Quentin Colombet2016-07-211-2/+4
| | | | | | | | | | When we failed to parse a function in the mir parser, we should abort the whole compilation instead of continuing in a weird state. Indeed, this was creating strange machine function passes failures that were hard to understand, until we notice that the function actually did not get parsed correctly! llvm-svn: 276348
* [X86] Do not use AND8ri8 in AVX512 patternMichael Kuperstein2016-07-211-1/+1
| | | | | | | This variant is (as documented in the TD) for disassembler use only, and should not be used in patterns - it is longer, and is broken on 64-bit. llvm-svn: 276347
* [InstSimplify] don't crash handling a pointer or aggregate typeSanjay Patel2016-07-211-0/+3
| | | | llvm-svn: 276345
* [AArch64][Inline-Asm] Return the 32-bit floating point register classAkira Hatanaka2016-07-211-1/+1
| | | | | | | | | | | | | | | when constraint "w" is used on a 32-bit operand. This enables compiling the following code, which used to error out in the backend: void foo1(int a) { asm volatile ("sqxtn h0, %s0\n" : : "w"(a):); } Fixes PR28633. llvm-svn: 276344
* [InstSimplify] recognize trunc + icmp sgt/slt variants of select ↵Sanjay Patel2016-07-211-7/+33
| | | | | | | | | | | | | | | | | | simplifications (PR28466) rL245171 exposed a hole in InstSimplify that manifested in a strange way in PR28466: https://llvm.org/bugs/show_bug.cgi?id=28466 It's possible to use trunc + icmp sgt/slt in place of an and + icmp eq/ne, so we need to recognize that pattern to eliminate selects that are choosing between some value and some bitmasked version of that value. Note that there is significant room for improvement (refactoring) and enhancement (more patterns, possibly in InstCombine rather than here). Differential Revision: https://reviews.llvm.org/D22537 llvm-svn: 276341
* [OptDiag,LDist] Convert remaining opt remarks to use the new APIAdam Nemet2016-07-211-6/+5
| | | | llvm-svn: 276340
* [LV] Move vector int induction update to end of latchMatthew Simpson2016-07-211-3/+12
| | | | | | | | | | | This patch moves the update instruction for vectorized integer induction phi nodes to the end of the latch block. This ensures consistent placement of all induction updates across all the kinds of int inductions we create (scalar, splat vector, or vector phi). Differential Revision: https://reviews.llvm.org/D22416 llvm-svn: 276339
* Fix the clang-cl self-host with VS 2013 headersReid Kleckner2016-07-211-2/+1
| | | | | | | | std::numeric_limits<int64_t>::max() is not constexpr in VC 2013 headers, and Clang complains that it isn't. MSVC 2013 itself is emitting a dynamic initializer for this thing. Instead, use an enum. llvm-svn: 276334
* Normalize file docs. NFC.George Burgess IV2016-07-211-1/+1
| | | | | | | | Having the added `\brief` made doxygen interpret it as the summary for the `llvm` namespace (visible at: http://llvm.org/doxygen/namespaces.html). llvm-svn: 276331
* [PGO] Make needsComdatForCounter() available (NFC)Rong Xu2016-07-212-27/+26
| | | | | | | | | | Move needsComdatForCounter() to lib/ProfileData/InstrProf.cpp from lib/Transforms/Instrumentation/InstrProfiling.cpp to make is available for other files. Differential Revision: https://reviews.llvm.org/D22643 llvm-svn: 276330
* Revert "Invariant start/end intrinsics overloaded for address space"Anna Thomas2016-07-211-27/+1
| | | | | | This reverts commit r276316. llvm-svn: 276320
* [IndVars] Reflow oddly formatted condition; NFCSanjoy Das2016-07-211-2/+2
| | | | llvm-svn: 276319
* Invariant start/end intrinsics overloaded for address spaceAnna Thomas2016-07-211-1/+27
| | | | | | | | | | | | | | | | | | | | | Summary: The llvm.invariant.start and llvm.invariant.end intrinsics currently support specifying invariant memory objects only in the default address space. With this change, these intrinsics are overloaded for any adddress space for memory objects and we can use these llvm invariant intrinsics in non-default address spaces. Example: llvm.invariant.start.p1i8(i64 4, i8 addrspace(1)* %ptr) This overloaded intrinsic is needed for representing final or invariant memory in managed languages. Reviewers: tstellarAMD, reames, apilipenko Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22519 llvm-svn: 276316
* make InstCombine compare helper functions private; NFCSanjay Patel2016-07-212-68/+69
| | | | | | Also, rename some of them for consistency and to follow current conventions. llvm-svn: 276312
* Avoid a string copy, NFCVedant Kumar2016-07-211-1/+1
| | | | llvm-svn: 276310
* [IRTranslator] Add G_SUB opcode.Quentin Colombet2016-07-211-0/+2
| | | | | | This commit adds a generic SUB opcode to global-isel. llvm-svn: 276308
* [IRTranslator] Add comments to explain the ordering of the switch. NFC.Quentin Colombet2016-07-211-0/+3
| | | | | | Group arithmetic operations, bitwise operations, and branch operations. llvm-svn: 276305
* [InstCombine] break up visitICmpInstWithInstAndIntCst(); NFCISanjay Patel2016-07-212-155/+166
| | | | | | | Making smaller pieces out of some of these ~1000 line functions should make it easier to incrementally upgrade them to handle vector types. llvm-svn: 276304
* [AMDGPU] Emit read-only data to .rodata for hsaKonstantin Zhuravlyov2016-07-211-1/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D22538 llvm-svn: 276298
* [IRTranslator] Add G_AND opcode.Quentin Colombet2016-07-211-0/+2
| | | | | | This commit adds a generic AND opcode to global-isel. llvm-svn: 276297
* AMDGPU/SI: Add support for R_AMDGPU_ABS32Konstantin Zhuravlyov2016-07-211-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D21646 llvm-svn: 276294
* [AArch64] Load/store opt: Don't count transient instructions towards search ↵Geoff Berry2016-07-211-15/+14
| | | | | | | | | | | | | | | | | | limits. Summary: This change also changes findMatchingInsn and findMatchingUpdateInsnForward to take DBG_VALUE opcodes into account when tracking register defs and uses, which could potentially inhibit these optimizations in the presence of debug information. Reviewers: mcrosier Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D22582 llvm-svn: 276293
* [X86][SSE] Allow folding of store/zext with PEXTRW of 0'th elementSimon Pilgrim2016-07-211-6/+15
| | | | | | | | | | | | | | Under normal circumstances we prefer the higher performance MOVD to extract the 0'th element of a v8i16 vector instead of PEXTRW. But as detailed on PR27265, this prevents the SSE41 implementation of PEXTRW from folding the store of the 0'th element. Additionally it prevents us from making use of the fact that the (SSE2) reg-reg version of PEXTRW implicitly zero-extends the i16 element to the i32/i64 destination register. This patch only preferentially lowers to MOVD if we will not be zero-extending the extracted i16, nor prevent a store from being folded (on SSSE41). Fix for PR27265. Differential Revision: https://reviews.llvm.org/D22509 llvm-svn: 276289
* [X86][SSE] Pull out duplicate EXTRW lowering code. NFCI.Simon Pilgrim2016-07-211-26/+16
| | | | | | As requested on D22509, I've pulled out the v8i16 extraction lowering as the SSE41 and pre-SSE41 implementations are effectively the same. llvm-svn: 276285
* [X86][AVX] Added support for lowering to VBROADCASTF128/VBROADCASTI128Simon Pilgrim2016-07-214-12/+72
| | | | | | | | | | | | As reported on PR26235, we don't currently make use of the VBROADCASTF128/VBROADCASTI128 instructions (or the AVX512 equivalents) to load+splat a 128-bit vector to both lanes of a 256-bit vector. This patch enables lowering from subvector insertion/concatenation patterns and auto-upgrades the llvm.x86.avx.vbroadcastf128.pd.256 / llvm.x86.avx.vbroadcastf128.ps.256 intrinsics to match. We could possibly investigate using VBROADCASTF128/VBROADCASTI128 to load repeated constants as well (similar to how we already do for scalar broadcasts). Differential Revision: https://reviews.llvm.org/D22460 llvm-svn: 276281
* [DemandedBits] Reduce number of duplicated DenseMap lookups.Benjamin Kramer2016-07-211-5/+4
| | | | | | No functionality change intended. llvm-svn: 276278
* Rename StringMap::emplace_second to try_emplace.Benjamin Kramer2016-07-212-2/+2
| | | | | | | Coincidentally this function maps to the C++17 try_emplace. Rename it for consistentcy with C++17 std::map. NFC. llvm-svn: 276276
* [AMDGPU] Some code cleaning in SIRegisterInfo.tdSam Kolton2016-07-211-33/+23
| | | | | | | | | | Reviewers: tstellarAMD, vpykhtin Subscribers: arsenm, kzhuravl Differential Revision: https://reviews.llvm.org/D22620 llvm-svn: 276274
* ExecutionDepsFix - Fix bug in clearance calculationMarina Yatsina2016-07-211-2/+0
| | | | | | | | The clearance calculation did not take into account registers defined as outputs or clobbers in inline assembly machine instructions because these register defs are implicit. Differential Revision: http://reviews.llvm.org/D22580 llvm-svn: 276266
* [GCOV] Remove a layer of indirection.Benjamin Kramer2016-07-211-18/+10
| | | | | | | StringMap is designed to hold large values. No functionality change intended. llvm-svn: 276265
* AMDGPU: Fix phis from blocks split due to register indexingMatt Arsenault2016-07-211-15/+22
| | | | llvm-svn: 276257
* [GVNHoist] Preserve optimization hints which agreeDavid Majnemer2016-07-211-3/+17
| | | | | | | If we have optimization hints with agree with each other along different paths, preserve them. llvm-svn: 276248
* [GVNHoist] Don't wrongly preserve TBAADavid Majnemer2016-07-211-0/+12
| | | | | | | We hoisted loads/stores without taking into account which can cause miscompiles. llvm-svn: 276240
* [MergedLoadStoreMotion] Remove out of date commentDavid Majnemer2016-07-211-1/+0
| | | | llvm-svn: 276239
* Add missing import to fix the buildAmaury Sechet2016-07-211-0/+1
| | | | llvm-svn: 276237
* Expose AttributeSetNode, use it to provide aggregate getter for attribute in ↵Amaury Sechet2016-07-213-68/+126
| | | | | | | | | | | | | | the C API. Summary: See D19181 for context. Reviewers: whitequark, Wallbraker, jyknight, echristo, bkramer, void Subscribers: mehdi_amini Differential Revision: http://reviews.llvm.org/D21265 llvm-svn: 276236
* IPRA: Fix RegMask calculation for alias registersMatthias Braun2016-07-211-12/+1
| | | | | | | | | | | | | | | | | | | | | | | This patch fixes a very subtle bug in regmask calculation. Thanks to zan jyu Wong <zyfwong@gmail.com> for bringing this to notice. For example if CL is only clobbered than CH should not be marked clobbered but CX, RCX and ECX should be mark clobbered. Previously for each modified register all of its aliases are marked clobbered by markRegClobbred() in RegUsageInfoCollector.cpp but that is wrong because when CL is clobbered then MRI::isPhysRegModified() will return true for CL, CX, ECX, RCX which is correct behavior but then for CX, EXC, RCX we mark CH also clobbered as CH is aliased to CX,ECX,RCX so markRegClobbred() is not required because isPhysRegModified already take cares of proper aliasing register. A very simple test case has been added to verify this change. Please find relevant bug report here : http://llvm.org/PR28567 Patch by Vivek Pandya <vivekvpandya@gmail.com> Differential Revision: https://reviews.llvm.org/D22400 llvm-svn: 276235
* [OptDiag] Missed these when making the IR Value a const pointerAdam Nemet2016-07-211-2/+4
| | | | llvm-svn: 276224
* [OptDiag,LV] Add hotness attribute to applied-optimization remarksAdam Nemet2016-07-212-7/+22
| | | | | | | Test coverage is provided by modifying the function in the FP-math testcase that we are allowed to vectorize. llvm-svn: 276223
* X86InstrInfo: No need for liveness analysis in classifyLEAReg()Matthias Braun2016-07-211-18/+2
| | | | | | | | | | | | | | | | | | | | classifyLEAReg() deals with switching operands from 32bit to 64bit in order to use a LEA64_32 instruction (for three address code goodness). It currently performs a liveness analysis to determine the kill/undef flag for the newly added operand. This should not be necessary: - If the previous operand had a kill flag, then the 32bit part of the register gets killed, this will kill the super register as well. - If the previous operand had an undef flag then we didn't care what value we read, just use the same flag on the new operand. (No matter what an operand with an undef flag won't affect liveness) This makes the code independent of the presence of kill flags because it avoids a call to MachineBasicBlock::computeRegisterLiveness(). Differential Revision: http://reviews.llvm.org/D22283 llvm-svn: 276222
* [InstCombine] LogicOpc (zext X), C --> zext (LogicOpc X, C) (PR28476)Sanjay Patel2016-07-212-28/+16
| | | | | | | | | | | | | | | | The benefits of this change include: 1. Remove DeMorgan-matching code that was added specifically to work-around the missing transform in http://reviews.llvm.org/rL248634. 2. Makes the DeMorgan transform work for vectors too. 3. Fix PR28476: https://llvm.org/bugs/show_bug.cgi?id=28476 Extending this transform to other casts and other associative operators may be useful too. See https://reviews.llvm.org/D22421 for a prerequisite for doing that though. Differential Revision: https://reviews.llvm.org/D22271 llvm-svn: 276221
* [OptDiag,LV] Add hotness attribute to the derived analysis remarksAdam Nemet2016-07-202-7/+31
| | | | | | | | This includes FPCompute and Aliasing. Testcase is based on no_fpmath.ll. llvm-svn: 276211
* [InstSimplify][InstCombine] don't crash when folding vector selects of icmpSanjay Patel2016-07-202-2/+8
| | | | | | Differential Revision: https://reviews.llvm.org/D22602 llvm-svn: 276209
* Make help text more consistent. NFC.George Burgess IV2016-07-201-1/+1
| | | | llvm-svn: 276205
* [CFLAA] Add offset tracking in CFLGraph.George Burgess IV2016-07-201-13/+122
| | | | | | | | | | | | | | | | (Also, refactor our constexpr handling to be less insane). This patch lets us track field offsets in the CFL Graph, which is the first step to making CFLAA field/offset sensitive. Woohoo! Note that this patch shouldn't visibly change our behavior (since we make no use of the offsets we're now tracking), so we can't quite add tests for this yet. Patch by Jia Chen. Differential Revision: https://reviews.llvm.org/D22598 llvm-svn: 276201
* [NVPTX] Enable the load-store vectorizer on nvptx.Justin Lebar2016-07-202-1/+11
| | | | | | | | | | Reviewers: tra Subscribers: jholewinski, arsenm, asbirlea Differential Revision: https://reviews.llvm.org/D22592 llvm-svn: 276196
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