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* [ARM] Allow the scheduler to clone a node with glue to avoid a copy CPSR ↔ ↵Roger Ferrer Ibanez2018-01-313-4/+30
| | | | | | | | | | | | | | | | | | | | | | GPR. In Thumb 1, with the new ADDCARRY / SUBCARRY the scheduler may need to do copies CPSR ↔ GPR but not all Thumb1 targets implement them. The schedule can attempt, before attempting a copy, to clone the instructions but it does not currently do that for nodes with input glue. In this patch we introduce a target-hook to let the hook decide if a glued machinenode is still eligible for copying. In this case these are ARM::tADCS and ARM::tSBCS . As a follow-up of this change we should actually implement the copies for the Thumb1 targets that do implement them and restrict the hook to the targets that can't really do such copy as these clones are not ideal. This change fixes PR35836. Differential Revision: https://reviews.llvm.org/D42051 llvm-svn: 323857
* [WebAssembly] Remove some unused code and tidy logging. NFC.Sam Clegg2018-01-311-14/+7
| | | | | | | | Patch by Nicholas Wilson! Differential Revision: https://reviews.llvm.org/D42540 llvm-svn: 323846
* LTO: Drop comdats when converting definitions to declarations.Peter Collingbourne2018-01-311-0/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D42715 llvm-svn: 323844
* Revert r323559 due to EXPENSIVE_CHECKS regression.Eli Friedman2018-01-311-2/+2
| | | | | | | I have a fix for the issue (https://reviews.llvm.org/D42655) but it's taking a while to get reviewed, so reverting in the meantime. llvm-svn: 323841
* [RDF] Clear the renamable flag when copy propagating reserved registersKrzysztof Parzyszek2018-01-301-2/+6
| | | | llvm-svn: 323831
* LLParser: add an argument for overriding data layout and do not check alloca ↵Yaxun Liu2018-01-305-32/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | addr space Sometimes users do not specify data layout in LLVM assembly and let llc set the data layout by target triple after loading the LLVM assembly. Currently the parser checks alloca address space no matter whether the LLVM assembly contains data layout definition, which causes false alarm since the default data layout does not contain the correct alloca address space. The parser also calls verifier to check debug info and updating invalid debug info. Currently there is no way to let the verifier to check debug info only. If the verifier finds non-debug-info issues the parser will fail. For llc, the fix is to remove the check of alloca addr space in the parser and disable updating debug info, and defer the updating of debug info and verification to be after setting data layout of the IR by target. For other llvm tools, since they do not override data layout by target but instead can override data layout by a command line option, an argument for overriding data layout is added to the parser. In cases where data layout overriding is necessary for the parser, the data layout can be provided by command line. Differential Revision: https://reviews.llvm.org/D41832 llvm-svn: 323826
* [Hexagon] Handle truncates in polynomial multiply idiom recognitionKrzysztof Parzyszek2018-01-301-12/+70
| | | | | | | This is in anticipation of https://reviews.llvm.org/D42424, which would otherwise break one of the pmpy testcases. llvm-svn: 323824
* [X86] Remove redundant check for hasAVX512 before calling hasBWI. NFCCraig Topper2018-01-301-3/+2
| | | | | | hasBWI implies hasAVX512. llvm-svn: 323823
* Turn two static functions into methods, to simplify calling them.Paul Robinson2018-01-301-14/+6
| | | | llvm-svn: 323821
* [LLVM-C] Add Accessors For A Module's Source File NameRobert Widmann2018-01-301-0/+9
| | | | | | | | | | | | | | Summary: Also unblocks some cleanup in the echo-test. Reviewers: whitequark, deadalnix Reviewed By: whitequark Subscribers: harlanhaskins, llvm-commits Differential Revision: https://reviews.llvm.org/D42618 llvm-svn: 323819
* [ThinLTO/gold] Write empty imports even for modules with symbolsVitaly Buka2018-01-301-7/+15
| | | | | | | | | | | | Summary: ThinLTO may skip object for other reasons, e.g. if there is no summary. Reviewers: pcc, eugenis Subscribers: mehdi_amini, inglorion, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D42514 llvm-svn: 323818
* Teach ValueMapper to use ODR uniqued types when availableTeresa Johnson2018-01-301-4/+15
| | | | | | | | | | | | | | | | | Summary: This is exposed during ThinLTO compilation, when we import an alias by creating a clone of the aliasee. Without this fix the debug type is unnecessarily cloned and we get a duplicate, undoing the uniquing. Fixes PR36089. Reviewers: mehdi_amini, pcc Subscribers: eraman, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D41669 llvm-svn: 323813
* [GlobalISel] Bail out on calls to dllimported functionsMartin Storsjo2018-01-301-0/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D42568 llvm-svn: 323811
* [AArch64] Properly handle dllimport of variables when using fast-iselMartin Storsjo2018-01-302-11/+15
| | | | | | Differential Revision: https://reviews.llvm.org/D42567 llvm-svn: 323810
* [Hexagon] Handle non-aligned offsets in globals in extender optimizationKrzysztof Parzyszek2018-01-301-18/+52
| | | | | | | | | | Instructions like memd(r0+##global+1) are legal as long as the entire address is properly aligned. Assuming that "global" is aligned at an 8-byte boundary, the expression "global+1" appears to be misaligned. Handle such cases in HexagonConstExtenders, and make sure that any non- extended offsets generated are still aligned accordingly. llvm-svn: 323799
* Revert: [Hexagon] Make sure that offset on globals matches alignment ↵Krzysztof Parzyszek2018-01-302-41/+14
| | | | | | | | | | | | | requirements This reverts r323562, since it wasn't actually necessary. Constant- extended offsets do not need to be aligned, as long as the effective address is aligned. Keep the testcase, with a modification which checks that such offsets are not unnecessarily avoided. llvm-svn: 323798
* [X86][XOP] Update isVectorShiftByScalarCheap with cases covered by XOPSimon Pilgrim2018-01-301-0/+5
| | | | | | | | Similar to D42437, XOP supports variable shift for v16i8/v8i16/v4i32/v2i64 types. Differential Revision: https://reviews.llvm.org/D42526 llvm-svn: 323797
* [AMDGPU] isRenamable fixes to support copy forwardingGeoff Berry2018-01-304-4/+12
| | | | | | | | | | | Mark more opcodes as hasExtraSrcRegAllocReq so that their operands will be marked as not renamable, to avoid copy forwarding violating the constraint that only one operand may use the constant bus. These changes fix a few mis-compiles when copy forwarding is enabled in MachineCopyPropagation by D41835 (and were reviewed as part of that change). llvm-svn: 323794
* [AMDGPU] Revert "[AMDGPU] Add options for waitcnt pass debugging; add instr ↵Mark Searles2018-01-301-63/+8
| | | | | | | | | | | | | count in debug output." Patch caused a buildbot failure; arg; http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/17373/s\ teps/build_Lld/logs/stdio : /Users/buildslave/as-bldslv9/lld-x86_64-darwin13/llvm.src/lib/Target/AMDGPU/SIInsertWaitcnts.cpp:1563:18: error: unused variable 'InstCnt' [-Werror,-Wunused-variable] static int32_t InstCnt = 0; " This reverts commit 4f4a7d61e306b67044d9f16bc2016fee806bc2cc. llvm-svn: 323791
* [CodeView] Micro-optimizations to speed up type merging.Zachary Turner2018-01-302-115/+91
| | | | | | | | | | | | Based on a profile, a couple of hot spots were identified in the main type merging loop. The code was simplified, a few loops were re-arranged, and some outlined functions were inlined. This speeds up type merging by a decent amount, shaving around 3-4 seconds off of a 40 second link in my test case. Differential Revision: https://reviews.llvm.org/D42559 llvm-svn: 323790
* [AMDGPU] Add options for waitcnt pass debugging; add instr count in debug ↵Mark Searles2018-01-301-8/+63
| | | | | | | | | | | | | | | output. -amdgpu-waitcnt-forcezero={1|0} Force all waitcnt instrs to be emitted as s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -amdgpu-waitcnt-forceexp=<n> Force emit a s_waitcnt expcnt(0) before the first <n> instrs -amdgpu-waitcnt-forcelgkm=<n> Force emit a s_waitcnt lgkmcnt(0) before the first <n> instrs -amdgpu-waitcnt-forcevm=<n> Force emit a s_waitcnt vmcnt(0) before the first <n> instrs This patch was pushed ( abb190fd51cd2f9a9eef08c024e109f7f7e909fc ), which caused a buildbot failure, reverted ( 6227480d74da507cf8e1b4bcaffbdb9fb875b4b8 ), and then updated to fix buildbot failures (this patch). Differential Revision: https://reviews.llvm.org/D40091 llvm-svn: 323788
* AMDGPU/SI: Add decoding in the GFX80_UNPACKED decoding namespace.Changpeng Fang2018-01-301-0/+5
| | | | | | | | | | Reviewer: Dmitry (dp). Differential Revision: https://reviews.llvm.org/D42596 llvm-svn: 323785
* [DeadArgumentElimination] Preserve llvm.dbg.values's first argumentPetar Jovanovic2018-01-301-8/+16
| | | | | | | | | | | | | When removing return value Dead Argument Elimination pass clobbers first llvm.dbg.value’s argument for live arguments of that function by replacing it with nullptr. In the next pass it will be deleted, so debug location about those arguments are lost. This change fixes it. Patch by Djordje Todorovic. Differential Revision: https://reviews.llvm.org/D42541 llvm-svn: 323784
* CodeGen: support an extension to pass linker options on ELFSaleem Abdulrasool2018-01-305-1/+24
| | | | | | | | | | | | | | | | | | Introduce an extension to support passing linker options to the linker. These would be ignored by older linkers, but newer linkers which support this feature would be able to process the linker. Emit a special discarded section `.linker-option`. The content of this section is a pair of strings (key, value). The key is a type identifier for the parameter. This allows for an argument free parameter that will be processed by the linker with the value being the parameter. As an example, `lib` identifies a library to be linked against, traditionally the `-l` argument for Unix-based linkers with the parameter being the library name. Thanks to James Henderson, Cary Coutant, Rafael Espinolda, Sean Silva for the valuable discussion on the design of this feature. llvm-svn: 323783
* [AArch64] Add new target feature to fuse address generation with load or storeEvandro Menezes2018-01-303-0/+40
| | | | | | | | | This feature enables the fusion of the address generation and a corresponding load or store together. Differential revision: https://reviews.llvm.org/D42393 llvm-svn: 323782
* [mips] Fix incorrect sign extension for fpowi libcallSimon Dardis2018-01-302-8/+9
| | | | | | | | | | | | | | | | | PR36061 showed that during the expansion of ISD::FPOWI, that there was an incorrect zero extension of the integer argument which for MIPS64 would then give incorrect results. Address this with the existing mechanism for correcting sign extensions. This resolves PR36061. Thanks to James Cowgill for reporting the issue! Reviewers: atanasyan, hfinkel Differential Revision: https://reviews.llvm.org/D42537 llvm-svn: 323781
* Re-commit : [PowerPC] Add handling for ColdCC calling convention and a pass ↵Zaara Syeda2018-01-309-12/+275
| | | | | | | | | | | | | | | | | | | | | to mark candidates with coldcc attribute. This recommits r322721 reverted due to sanitizer memory leak build bot failures. Original commit message: This patch adds support for the coldcc calling convention for Power. This changes the set of non-volatile registers. It includes a pass to stress test the implementation by marking all static directly called functions with the coldcc attribute through the option -enable-coldcc-stress-test. It also includes an option, -ppc-enable-coldcc, to add the coldcc attribute to functions which are cold at all call sites based on BlockFrequencyInfo when the containing function does not call any non cold functions. Differential Revision: https://reviews.llvm.org/D38413 llvm-svn: 323778
* Add more initializers to quiet a clang warningDaniel Sanders2018-01-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: `struct crashreporter_annotations_t` gained one more `uint64_t` field in `CRASHREPORTER_ANNOTATIONS_VERSION` 5 causing an annoying clang warning: ``` llvm/lib/Support/PrettyStackTrace.cpp:92:65: warning: missing field 'abort_cause' initializer [-Wmissing-field-initializers] = { CRASHREPORTER_ANNOTATIONS_VERSION, 0, 0, 0, 0, 0, 0 }; ^ 1 warning generated ``` Let's fix it. Patch by Roman Tereshin Reviewers: qcolombet, echristo, beanz, dexonsmith Reviewed By: echristo Subscribers: dsanders, dexonsmith, beanz, echristo, qcolombet, llvm-commits Differential Revision: https://reviews.llvm.org/D42268 llvm-svn: 323777
* [AArch64] Add new target feature to handle cheap as move for ExynosEvandro Menezes2018-01-303-5/+11
| | | | | | | | | This feature enables special handling of cheap as move in the existing custom handling specifically for Exynos processors. Differential revision: https://reviews.llvm.org/D42387 llvm-svn: 323774
* [AArch64] Add pipeline model for Exynos M3Evandro Menezes2018-01-306-7/+895
| | | | | | | | Add the scheduling and cost model for Exynos M3. Differential revision: https://reviews.llvm.org/D42387 llvm-svn: 323773
* [RS4GC] Handle call/invoke instructions as base defining values of vectorsDaniel Neilson2018-01-301-0/+6
| | | | | | | | | | | | | | | | | | Summary: There's an asymmetry in the definitions of findBaseDefiningValueOfVector() and findBaseDefiningValue() of RS4GC. The later handles call and invoke instructions, and the former does not. This appears to be simple oversight. This patch remedies the oversight by adding the call and invoke cases to findBaseDefiningValueOfVector(). Reviewers: DaniilSuchkov, anna Reviewed By: anna Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42653 llvm-svn: 323764
* Revert "[X86] Avoid using high register trick for test instruction"Eric Liu2018-01-304-22/+68
| | | | | | This reverts commit r323690. This causes crash in llc. See the original commit thread for details. llvm-svn: 323761
* [DSE] make sure memory is not modified before partial store merging (PR36129)Sanjay Patel2018-01-301-1/+2
| | | | | | | | | | | | We missed a critical check in D30703. We must make sure that no intermediate store is sitting between the stores that we want to merge. This should fix: https://bugs.llvm.org/show_bug.cgi?id=36129 Differential Revision: https://reviews.llvm.org/D42663 llvm-svn: 323759
* [XRay] clarify error messages when parsing broken tracesMartin Pelikan2018-01-301-3/+4
| | | | | | | | | | | | | | | Summary: When there's a mismatch of a function argument being right after the wrong function, print an offset into the file where that happened, to ease further debugging. Reviewers: dberris, eizan, kpw Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42492 llvm-svn: 323758
* [AccelTable] Move print methods to implementation. NFCJonas Devlieghere2018-01-301-0/+83
| | | | | | | This patch moves the implementation of the print methods from the header to the cpp file. llvm-svn: 323757
* Test commit.Brock Wyma2018-01-301-2/+2
| | | | | | As per the LLVM Developer Policy under "Obtainiing Commit Access". llvm-svn: 323754
* Spelling mistake in comment. NFCI.Simon Pilgrim2018-01-301-1/+1
| | | | llvm-svn: 323752
* [ARM GlobalISel] Map G_SITOFP and G_UITOFPDiana Picus2018-01-301-0/+14
| | | | | | | Straightforward mapping (integer operand to GPR, floating point operand to FPR). llvm-svn: 323731
* [ARM GlobalISel] Legalize G_SITOFP and G_UITOFPDiana Picus2018-01-302-0/+30
| | | | | | | | Legal if we have hardware support, libcall otherwise. Also add supporting code to the legalizer helper for libcalls. llvm-svn: 323730
* [ARM GlobalISel] Map G_FPTOSI and G_FPTOUIDiana Picus2018-01-301-0/+14
| | | | | | | Straightforward mapping (integer operand goes to GPR, floating point operand goes to FPR). llvm-svn: 323727
* [ARM GlobalISel] Legalize G_FPTOSI and G_FPTOUIDiana Picus2018-01-302-3/+30
| | | | | | | | | Legal if we have hardware support for floating point, libcalls otherwise. Also add the necessary support for libcalls in the legalizer helper. llvm-svn: 323726
* [InstSimplify] (X * Y) / Y --> X for relaxed floating-point opsSanjay Patel2018-01-301-0/+6
| | | | | | | | | This is the FP counterpart that was mentioned in PR35709: https://bugs.llvm.org/show_bug.cgi?id=35709 Differential Revision: https://reviews.llvm.org/D42385 llvm-svn: 323716
* [SelectionDAG]: Ignore "returned" in the presence of an implicit sret.Dan Gohman2018-01-301-2/+4
| | | | | | | | | | | | | | | | When a function return value can't be directly lowered, such as returning an i128 on WebAssembly, as indicated by the CanLowerReturn target hook, SelectionDAGBuilder can translate it to return the value through a hidden sret-like argument. If such a function has an argument with the "returned" attribute, the attribute can't be automatically lowered, because the function no longer has a normal return value. For now, just discard the "returned" attribute. This fixes PR36128. llvm-svn: 323715
* [RAFast] Don't dereference MBB::endQuentin Colombet2018-01-291-5/+6
| | | | | | | | | | | | | | | | When RAFast sees liveins in on a basic block, it uses that information to initialize the availability of the registers. The called method uses an instruction as one of its argument and in the liveins case, RAFast was dereferencing MBB::begin which can be MBB::end for empty basic block. Change the API of definePhysReg to use MachineBasicBlock::iterator instead of MachineInstr so that we don't dereference an invalid iterator while making the call. rdar://problem/36952401 llvm-svn: 323710
* AMDGPU: Move ADDRIndirect complex pattern into R600Instructions.tdTom Stellard2018-01-292-1/+1
| | | | | | | | | | | | | | Summary: This is only used by R600. Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, mgorny, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D37114 llvm-svn: 323709
* [X86] Use VMOVDQA64 for aligned vXi32 stores.Craig Topper2018-01-291-3/+12
| | | | | | I meant to do this with the unaligned stores in r322820, but looks like I missed it. llvm-svn: 323708
* AMDGPU: Allow a SGPR for the conditional KILL operandMarek Olsak2018-01-291-23/+31
| | | | | | | | | | | | | | | | | | Patch by: Bas Nieuwenhuizen Just use the _e64 variant if needed. This should be possible as per def : Pat < (int_amdgcn_kill (i1 (setcc f32:$src, InlineFPImm<f32>:$imm, cond:$cond))), (SI_KILL_F32_COND_IMM_PSEUDO $src, (bitcast_fpimm_to_i32 $imm), (cond_as_i32imm $cond)) > ; I don't think we can get an immediate for the other operand for which we need the second 32-bit word. https://reviews.llvm.org/D42302 llvm-svn: 323706
* LiveInterval: Print weight in print() function.Matthias Braun2018-01-291-0/+1
| | | | llvm-svn: 323702
* Stop tracking .debug_line_str in DWARFUnit. NFC.Paul Robinson2018-01-292-14/+13
| | | | llvm-svn: 323701
* [X86] Add FeaturePOPCNTFalseDeps to skylake server CPU to match skylake client.Craig Topper2018-01-291-1/+2
| | | | llvm-svn: 323700
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