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* [SelectionDAG] Don't use simple VT in generic shuffle codeSimon Pilgrim2018-02-031-1/+1
| | | | | | | | Better to assume that any value type may be commuted, not just MVTs. No test case right now, but discovered while investigating possible shuffle combines. llvm-svn: 324179
* [X86] Remove and autoupgrade kand/kandn/kor/kxor/kxnor/knot intrinsics.Craig Topper2018-02-033-30/+37
| | | | | | | | Clang already stopped using these a couple months ago. The test cases aren't great as there is nothing forcing the operations to stay in k-registers so some of them moved back to scalar ops due to the bitcasts being moved around. llvm-svn: 324177
* [ORC] Rename NullResolver to NullLegacyResolver.Lang Hames2018-02-031-2/+3
| | | | | | | | | This resolver conforms to the LegacyJITSymbolResolver interface, and will be replaced with a null-returning resolver conforming to the newer orc::SymbolResolver interface in the near future. This patch renames the class to avoid a clash. llvm-svn: 324175
* [InstCombine] Allow common type conversions to i8/i16/i32David Green2018-02-031-1/+9
| | | | | | | | | | | This, in instcombine, allows conversions to i8/i16/i32 (very common cases) even if the resulting type is not legal according to the data layout. This can often open up extra combine opportunities. Differential Revision: https://reviews.llvm.org/D42424 llvm-svn: 324174
* Fix MSVC signed/unsigned comparison warning. NFCI.Simon Pilgrim2018-02-031-1/+1
| | | | llvm-svn: 324171
* [InstCombine] Use getDestAlignment in SimplifyMemSet (NFC)Daniel Neilson2018-02-021-2/+2
| | | | | | | | Summary: Small NFC change to change the name of the function used getting and setting the alignment of a memset. llvm-svn: 324148
* [X86] Prefer to create a ISD::SETCC over X86ISD::PCMPEQ in ↵Craig Topper2018-02-021-3/+3
| | | | | | | | combineVectorSizedSetCCEquality. This is running pre-legalize, we should try to use target independent nodes. This will give the best opportunity for target independent optimizations. llvm-svn: 324147
* [X86] Pass SDLoc by const reference in a few more places in ↵Craig Topper2018-02-021-6/+8
| | | | | | X86ISelLowering.cpp. NFC llvm-svn: 324135
* [GISel][NFC]: Move RegisterBankInfo::getSizeInBits into TargetRegisterInfo.Aditya Nandakumar2018-02-022-13/+27
| | | | llvm-svn: 324125
* [InstCombine] simplify logic for swapMayExposeCSEOpportunities; NFCISanjay Patel2018-02-021-23/+9
| | | | llvm-svn: 324122
* [InstCombine] fix typos, formatting; NFCSanjay Patel2018-02-021-7/+6
| | | | llvm-svn: 324118
* [AArch64][GlobalISel] Use getRegClassForTypeOnBank() in selectCopy.Amara Emerson2018-02-021-23/+15
| | | | | | Differential Revision: https://reviews.llvm.org/D42832 llvm-svn: 324110
* [X86] Remove checks for FeatureAVX512 from the X86 assembly parser. Remove ↵Craig Topper2018-02-021-83/+73
| | | | | | | | | | | | | | | | | | | | | mcpu/mattr from assembly test command lines. Summary: We should always be able to accept AVX512 registers and instructions in llvm-mc. The only subtarget mode that should be checked is 16-bit vs 32-bit vs 64-bit mode. I've also removed all the mattr/mcpu lines from test RUN lines to be consistent with this. Most were due to AVX512, but a few were for other features. Fixes PR36202 Reviewers: RKSimon, echristo, bkramer Reviewed By: echristo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42824 llvm-svn: 324106
* [AMDGPU] Switch to the new addr space mapping by defaultYaxun Liu2018-02-022-20/+3
| | | | | | | | This requires corresponding clang change. Differential Revision: https://reviews.llvm.org/D40955 llvm-svn: 324101
* Fix type sizes that were causing incorrect string formattingJames Henderson2018-02-021-2/+2
| | | | llvm-svn: 324096
* [ThinLTO] - Add comment. NFC.George Rimar2018-02-021-0/+2
| | | | | | Was requested during review of D42798. llvm-svn: 324095
* [Analysis] Support aggregate access types in TBAAIvan A. Kosarev2018-02-021-96/+217
| | | | | | | | | This patch implements analysis for new-format TBAA access tags with aggregate types as their final access types. Differential Revision: https://reviews.llvm.org/D41501 llvm-svn: 324092
* Add missing new files from r324077James Henderson2018-02-022-0/+218
| | | | | | Differential Revision: https://reviews.llvm.org/D42481 llvm-svn: 324078
* [DWARF v5] Add limited support for dumping .debug_rnglistsJames Henderson2018-02-023-12/+29
| | | | | | | | | | | | | | | | | | | | | This change adds support to llvm-dwarfdump for dumping DWARF5 .debug_rnglists sections in regular ELF files. It is not complete, in that several DW_RLE_* encodings are currently not supported, but does dump the headert and the basic ranges for DW_RLE_start_length and DW_RLE_start_end encodings. Obvious next steps are to add verbose dumping that dumps the raw encodings, rather than the interpreted contents, to add -verify support of the section (e.g. to show that the correct number of offsets are specified), add dumping of .debug_rnglists.dwo, and to add support for other encodings. Reviewed by: dblaikie, JDevlieghere Differential Revision: https://reviews.llvm.org/D42481 llvm-svn: 324077
* [LTO] - Simplify. NFC.George Rimar2018-02-021-3/+2
| | | | llvm-svn: 324076
* [ThinLTO] - Fix for "ThinLTO inlines variables that should be discarded".George Rimar2018-02-021-6/+12
| | | | | | | | | | | This fixes PR36187. Patch teaches ThinLTO to drop non-prevailing variables, just like we recently did for functions (in r323633). Differential revision: https://reviews.llvm.org/D42798 llvm-svn: 324075
* [GlobalOpt] Include padding in debug fragmentsMikael Holmen2018-02-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When creating the debug fragments for a SRA'd variable, use the types' allocation sizes. This fixes issues where the pass would emit too small fragments, placed at the wrong offset, for padded types. An example of this is long double on x86. The type is represented using x86_fp80, which is 10 bytes, but the value is aligned to 12/16 bytes. The padding is included in the type's DW_AT_byte_size attribute; therefore, the fragments should also include that. Newer GCC releases (I tested 7.2.0) emit 12/16-byte pieces for long double. Earlier releases, e.g. GCC 5.5.0, behaved as LLVM did, i.e. by emitting a 10-byte piece, followed by an empty 2/6-byte piece for the padding. Failing to cover all `DW_AT_byte_size' bytes of a value with non-empty pieces results in the value being printed as <optimized out> by GDB. Patch by: David Stenberg Reviewers: aprantl, JDevlieghere Reviewed By: aprantl, JDevlieghere Subscribers: llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D42807 llvm-svn: 324066
* [SelectionDAG] Consider endianness in scalarizeVectorStore().Jonas Paulsson2018-02-021-2/+5
| | | | | | | | | | | | When handling vectors with non byte-sized elements, reverse the order of the elements in the built integer if the target is Big-Endian. SystemZ tests updated. Review: Eli Friedman, Ulrich Weigand. https://reviews.llvm.org/D42786 llvm-svn: 324063
* [SelectionDAG] Add an assert in getNode() for EXTRACT_VECTOR_ELT.Jonas Paulsson2018-02-021-0/+4
| | | | | | | | When getNode() is called to create an EXTRACT_VECTOR_ELT, assert that the result VT is at least as wide as the vector element type. Review: Eli Friedman llvm-svn: 324061
* [RISCV] Add ELFObjectFileBase::getRISCVFeatures let llvm-objdump could get ↵Shiva Chen2018-02-021-0/+13
| | | | | | | | | | | RISCV target feature llvm-objdump could get C feature by ELF::EF_RISCV_RVC e_flag, so then we don't have to add -mattr=+c on the command line. Differential Revision: https://reviews.llvm.org/D42629 llvm-svn: 324058
* [X86] Legalize (v64i1 (bitcast (i64 X))) on 32-bit targets by extracting ↵Craig Topper2018-02-021-0/+16
| | | | | | | | 32-bit halves from i32, bitcasting each to v32i1, and concatenating. This prevents the scalarization that would otherwise occur. llvm-svn: 324057
* [X86] Legalize (i64 (bitcast (v64i1 X))) on 32-bit targets by extracting to ↵Craig Topper2018-02-021-0/+17
| | | | | | | | v32i1 and bitcasting to i32. This saves a trip through memory and seems to open up other combining opportunities. llvm-svn: 324056
* [RISCV] Fix c.addi and c.addi16sp immediate constraints which should be non-zeroShiva Chen2018-02-022-9/+34
| | | | | | Differential Revision: https://reviews.llvm.org/D42782 llvm-svn: 324055
* [RISCV] Define getSetCCResultType for setting vector setCC typeShiva Chen2018-02-022-0/+10
| | | | | | | | To avoid trigger "No default SetCC type for vectors!" Assertion Differential Revision: https://reviews.llvm.org/D42675 llvm-svn: 324054
* Fix debug spelling in ResetMachineFunction pass.Amara Emerson2018-02-021-2/+2
| | | | llvm-svn: 324048
* [GlobalISel] Constrain the dest reg of IMPLICT_DEF.Amara Emerson2018-02-021-0/+6
| | | | | | | | | | This fixes a crash where the user is a COPY, which deliberately does not constrain its source operands, resulting in a vreg without a reg class escaping selection. Differential Revision: https://reviews.llvm.org/D42697 llvm-svn: 324047
* Remove non-modular header containing static utility functionsDavid Blaikie2018-02-022-203/+178
| | | | | | | | | | The one place that uses these functions isn't particularly long/complicated, so it's easier to just have these inline at that location than trying to split it out into a true header. (in part also because of the use of the DEBUG macros, which make this not really a standalone header even if the static functions were made inline instead) llvm-svn: 324044
* Add missing includesDavid Blaikie2018-02-021-0/+3
| | | | llvm-svn: 324040
* SplitKit: Fix liveness recomputation in some remat cases.Matthias Braun2018-02-022-11/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Example situation: ``` BB0: %0 = ... use %0 ; ... condjump BB1 jmp BB2 BB1: %0 = ... ; rematerialized def from above (from earlier split step) jmp BB2 BB2: ; ... use %0 ``` %0 will have a live interval with 3 value numbers (for the BB0, BB1 and BB2 parts). Now SplitKit tries and succeeds in rematerializing the value number in BB2 (This only works because it is a secondary split so SplitKit is can trace this back to a single original def). We need to recompute all live ranges affected by a value number that we rematerialize. The case that we missed before is that when the value that is rematerialized is at a join (Phi VNI) then we also have to recompute liveness for the predecessor VNIs. rdar://35699130 Differential Revision: https://reviews.llvm.org/D42667 llvm-svn: 324039
* [X86] Separate the call to LowerVectorAllZeroTest from EmitTest. NFCICraig Topper2018-02-011-17/+21
| | | | | | | | | | Every instruction that has the word TEST in its name seems to have been buried into EmitTest. But that code is largely concerned with trying to reuse the flags from instructions that update flags in a pretty normal way. PTEST/TESTP/KTEST do not update flags in a normal way. They only update Z and C and the C flag update is non-standard. Rather than try to bend EmitTest's already complex logic to accomodate this, just move the call up to LowerSETCC and replicate the few pre-checks that are needed. While there add a FIXME for using the C flag for checking for all 1s which we definitely couldn't do from EmitTEST. llvm-svn: 324029
* [GlobalISel][Legalizer] Relax a legalization loop detecting assert.Amara Emerson2018-02-011-1/+3
| | | | | | | Legalizing vectors may keep the element type the same but change the number of elements, the assert didn't take this into account. llvm-svn: 324028
* [InstCombine] allow multi-use values in canEvaluate* if all uses are in 1 instSanjay Patel2018-02-011-5/+13
| | | | | | | | | | | | | | | | This is the enhancement suggested in D42536 to fix a shortcoming in regular InstCombine's canEvaluate* functionality. When we have multiple uses of a value, but they're all in one instruction, we can allow that expression to be narrowed or widened for the same cost as a single-use value. AFAICT, this can only matter for multiply: sub/and/or/xor/select would be simplified away if the operands are the same value; add becomes shl; shifts with a variable shift amount aren't handled. Differential Revision: https://reviews.llvm.org/D42739 llvm-svn: 324014
* [PowerPC] Tell VSX swap removal that scalar conversions are lane-sensitiveNemanja Ivanovic2018-02-011-0/+2
| | | | | | | | This is a rather non-controversial change. We were missing these instructions from the list of instructions that are lane-sensitive. These two put the result into lane 0 (BE) or 3 (LE) regardless of the input. This patch fixes PR36068. llvm-svn: 324005
* [DAGCombiner] When folding (insert_subvector undef, (bitcast ↵Craig Topper2018-02-011-1/+3
| | | | | | | | | | | | (extract_subvector N1, Idx)), Idx) -> (bitcast N1) make sure that N1 has the same total size as the original output We were only checking the element count, but not the total width. This could cause illegal bitcasts to be created if for example the output was 512-bits, but N1 is 256 bits, and the extraction size was 128-bits. Fixes PR36199 Differential Revision: https://reviews.llvm.org/D42809 llvm-svn: 324002
* [GlobalISel] Fix assert failure when legalizing non-power-2 loads.Amara Emerson2018-02-011-3/+6
| | | | | | | Until we support extending loads properly we're going to fall back for these. We already handle stores in the same way, so this is just being consistent. llvm-svn: 324001
* [CodeView] Class record member counts should include base classes and ...Brock Wyma2018-02-011-0/+2
| | | | | | | | | Increment the field list member count for base classes and virtual base classes. Differential Revision: https://reviews.llvm.org/D41874 llvm-svn: 324000
* [ADT] Replace sys::MemoryFence with standard atomics.Benjamin Kramer2018-02-011-6/+2
| | | | | | | | This is a bit faster in theory, in practice it's cold code that's only active in !NDEBUG, so it probably doesn't make a difference. This is one of the last users of our homegrown Atomic.h. llvm-svn: 323999
* [AArch64] remove bogus comment; NFCSanjay Patel2018-02-011-3/+0
| | | | | | | I added this comment with D42323, but as discussed in D42806, the architecture does the right thing for denorms. We don't even need the select on 0.0 here? llvm-svn: 323996
* Remove CallGraphTraits and use equivalent methods in GraphTraitsEaswaran Raman2018-02-011-2/+2
| | | | | | | | | | | | | | | | Summary: D42698 adds child_edge_{begin|end} and children_edges to GraphTraits which are used here. The reason for this change is to make it easy to use count propagation on ModulesummaryIndex. As it stands, CallGraphTraits is in Analysis while ModuleSummaryIndex is in IR. Reviewers: davidxl, dberlin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42703 llvm-svn: 323994
* [MachineCopyPropagation] Extend pass to do COPY source forwardingGeoff Berry2018-02-012-1/+210
| | | | | | | | | | | | | | | | | | | | | | Summary: This change extends MachineCopyPropagation to do COPY source forwarding and adds an additional run of the pass to the default pass pipeline just after register allocation. This version of this patch uses the newly added MachineOperand::isRenamable bit to avoid forwarding registers is such a way as to violate constraints that aren't captured in the Machine IR (e.g. ABI or ISA constraints). This change is a continuation of the work started in D30751. Reviewers: qcolombet, javed.absar, MatzeB, jonpa, tstellar Subscribers: tpr, mgorny, mcrosier, nhaehnle, nemanjai, jyknight, hfinkel, arsenm, inouehrs, eraman, sdardis, guyblank, fedor.sergeev, aheejin, dschuff, jfb, myatsina, llvm-commits Differential Revision: https://reviews.llvm.org/D41835 llvm-svn: 323991
* AMDGPU/SI: Adjust the encoding family for D16 buffer instructions when the ↵Changpeng Fang2018-02-012-4/+10
| | | | | | | | | | | | target has UnpackedD16VMem feature. Reviewers: Matt and Brian Differential Revision: https://reviews.llvm.org/D42548 llvm-svn: 323988
* [X86][SSE] LowerBUILD_VECTORAsVariablePermute - add support for scaling ↵Simon Pilgrim2018-02-011-5/+44
| | | | | | | | | | index vectors This allows us to use PSHUFB for v8i16/v4i32 and VPERMD/PERMPS for v4i64/v4f64 variable shuffles. Differential Revision: https://reviews.llvm.org/D42487 llvm-svn: 323987
* [X86] Remove custom lowering vXi1 extending loads and truncating stores.Craig Topper2018-02-011-174/+0
| | | | | | | | | | | | | | Summary: Now that v2i1/v4i1 are legal without VLX. And v32i1 is legalized by splitting rather than widening. And isVectorLoadExtDesirable returns false for vXi1. It appears this handling is dead because the operations simply don't exist. Reviewers: RKSimon, zvi, guyblank, delena, spatel Reviewed By: delena Subscribers: llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D42781 llvm-svn: 323983
* [X86] Turn X86ISD::AND nodes that have no flag users back into ISD::AND just ↵Craig Topper2018-02-012-2/+14
| | | | | | | | | | | | | | | | | | | | | before isel to enable test instruction matching Summary: EmitTest sometimes creates X86ISD::AND specifically to hide the AND from DAG combine. But this prevents isel patterns that look for (cmp (and X, Y), 0) from being able to see it. So we end up with an AND and a TEST. The TEST gets removed by compare instruction optimization during the peephole pass. This patch attempts to fix this by converting X86ISD::AND with no flag users back into ISD::AND during the DAG preprocessing just before isel. In order to do this correctly I had to make the X86ISD::AND node created by EmitTest in this case really have a flag output. Which arguably it should have had anyway so that the number of operands would be consistent for the opcode in all cases. Then I had to modify the ReplaceAllUsesWith to understand that we might be looking at an instruction with 2 outputs. Though in this case there are no uses to replace since we just created the node, but that's what the code did before so I just made it keep working. Reviewers: spatel, RKSimon, niravd, deadalnix Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42764 llvm-svn: 323982
* [DAGCombiner] filter out denorm inputs when calculating sqrt estimate (PR34994)Sanjay Patel2018-02-012-11/+28
| | | | | | | | | | | | | | | | | | | | | | | As shown in the example in PR34994: https://bugs.llvm.org/show_bug.cgi?id=34994 ...we can return a very wrong answer (inf instead of 0.0) for square root when using a reciprocal square root estimate instruction. Here, I've conditionalized the filtering out of denorms based on the function having "denormal-fp-math"="ieee" in its attributes. The other options for this attribute are 'preserve-sign' and 'positive-zero'. So we don't generate this extra code by default with just '-ffast-math' (because then there's no denormal attribute string at all), but it works if you specify '-ffast-math -fdenormal-fp-math=ieee' from clang. As noted in the review, there may be other problems in clang that affect the results depending on platform (Linux x86 at least), but this should allow creating the desired codegen. Differential Revision: https://reviews.llvm.org/D42323 llvm-svn: 323981
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